- added dedicated sys_clk_out frequency synthesis
- SDRAM clocks use sys_clk_out for clock generation - added cpu_clk_out which is the same as sys_clk_in Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@727 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -34,89 +34,61 @@ entity clockgen is
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generic
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(
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clk_in_freq_hz : integer := 100E6;
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vga_clk_out_freq_hz : integer := 0;
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sdr_clk0_out_phaseshift : integer := 0;
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sdr_clk1_out_phaseshift : integer := 0
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vga_clk_out_freq_hz : integer := 100E6;
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sys_clk_out_freq_hz : integer := 100E6;
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sdr0_clk_out_phaseshift : integer := 0;
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sdr1_clk_out_phaseshift : integer := 0
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);
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port
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(
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-- Clocks and Reset
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rst : in std_logic; -- external async reset, low active
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rst_in : in std_logic; -- external async reset, low active
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clk_in : in std_logic; -- system clock (e.g. 100MHz), from board
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sys_clk_out : out std_logic;
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cpu_clk_out : out std_logic;
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vga_clk_out : out std_logic;
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sdr_clk0_fb_in : in std_logic; -- feedback clock
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sdr_clk0_0_out : out std_logic; -- System clock #0, dcm#0 output 0°
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sdr_clk0_270_out : out std_logic; -- System clock #0, dcm#0 output 270°
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sdr_clk1_0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
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sdr_clk1_270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
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locked_out : out std_logic; -- DCM locked status
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error_out : out std_logic -- indicates DCM Errors
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sdr0_clk_fb_in : in std_logic; -- feedback clock
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sdr0_clk0_out : out std_logic; -- System clock #0, dcm#0 output 0°
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sdr0_clk270_out : out std_logic; -- System clock #0, dcm#0 output 270°
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sdr1_clk0_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
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sdr1_clk270_out : out std_logic; -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
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sys_rst_out : out std_logic -- DCM locked status
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);
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end;
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architecture tech of clockgen is
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signal locked : unsigned(2 downto 0);
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signal dcm_rst : unsigned(2 downto 0);
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signal dcm0_clk0 : std_logic;
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signal dcm0_clk0_bufg : std_logic;
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signal dcm0_clkfx : std_logic;
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signal dcm1_clk0 : std_logic;
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signal dcm1_clk270 : std_logic;
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signal dcm1_clk0_bufg : std_logic;
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signal dcm1_clk270_bufg : std_logic;
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signal dcm2_clk0 : std_logic;
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signal dcm2_clk270 : std_logic;
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signal dcm2_clk0_bufg : std_logic;
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signal dcm2_clk270_bufg : std_logic;
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signal dcm0_locked : unsigned(2 downto 0);
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signal dcm1_locked : unsigned(2 downto 0);
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signal dcm2_locked : unsigned(2 downto 0);
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signal cnt_q : unsigned(4 downto 0);
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signal vga_clk0 : std_logic;
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signal vga_clkfx : std_logic;
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signal vga_clk0_bufg : std_logic;
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signal sys_clk0 : std_logic;
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signal sys_clkfx : std_logic;
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signal sys_clk0_bufg : std_logic;
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signal sys_clkfx_bufg : std_logic;
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signal sdr0_clk0 : std_logic;
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signal sdr0_clk270 : std_logic;
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signal sdr1_clk0 : std_logic;
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signal sdr1_clk270 : std_logic;
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signal sdr1_clk0_bufg : std_logic;
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signal reset_cnt : unsigned(4 downto 0);
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signal reset_pipe0 : unsigned(19 downto 0);
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signal reset_pipe1 : unsigned(19 downto 0);
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signal reset_pipe2 : unsigned(19 downto 0);
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signal vga_fx_lock : std_logic;
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signal sys_fx_lock : std_logic;
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signal sdr0_lock : std_logic;
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signal sdr1_lock : std_logic;
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type STATE_TYPE is (s0, s1, s2, s3, s4);
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signal state_q : STATE_TYPE;
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begin
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sdr_clk0_0_out <= dcm1_clk0_bufg;
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sdr_clk0_270_out <= dcm1_clk270_bufg;
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sdr_clk1_0_out <= dcm2_clk0_bufg;
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sdr_clk1_270_out <= dcm2_clk270_bufg;
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bufg11: bufg
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port map
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(
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o => dcm1_clk0_bufg,
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i => dcm1_clk0
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);
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bufg12: bufg
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port map (
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o => dcm1_clk270_bufg,
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i => dcm1_clk270
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);
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bufg13: bufg
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port map
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(
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o => dcm2_clk0_bufg,
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i => dcm2_clk0
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);
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bufg14: bufg
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port map (
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o => dcm2_clk270_bufg,
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i => dcm2_clk270
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);
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-------------------------------------------------------------------------------------------------------
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-- Clock generation
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-------------------------------------------------------------------------------------------------------
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-- Compnent instantiation
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inst_DCM_BASE_0 : DCM_BASE
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inst_DCM_VGA_FX : DCM_BASE
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generic map
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(
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CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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@@ -128,7 +100,7 @@ bufg14: bufg
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CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
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CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
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DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
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DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
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-- an integer from 0 to 15
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DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
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DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
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@@ -139,38 +111,92 @@ bufg14: bufg
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)
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port map
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(
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CLK0 => dcm0_clk0, -- 0 degree DCM CLK ouptput
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CLK0 => vga_clk0, -- 0 degree DCM CLK ouptput
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CLK180 => open, -- 180 degree DCM CLK output
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CLK270 => open, -- 270 degree DCM CLK output
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CLK2X => open, -- 2X DCM CLK output
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CLK2X180 => open, -- 2X, 180 degree DCM CLK out
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CLK90 => open, -- 90 degree DCM CLK output
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CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
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CLKFX => dcm0_clkfx, -- DCM CLK synthesis out (M/D)
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CLKFX => vga_clkfx, -- DCM CLK synthesis out (M/D)
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CLKFX180 => open, -- 180 degree CLK synthesis out
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LOCKED => locked(0), -- DCM LOCK status output
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CLKFB => dcm0_clk0_bufg, -- DCM clock feedback
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LOCKED => vga_fx_lock, -- DCM LOCK status output
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CLKFB => vga_clk0_bufg, -- DCM clock feedback
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CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
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RST => dcm_rst(0) -- DCM asynchronous reset input
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);
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BUFG_dcm_clk_fb : BUFG
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BUFG_vga_clk0 : BUFG
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port map
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(
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O => dcm0_clk0_bufg, -- Clock buffer output
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I => dcm0_clk0 -- Clock buffer input
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O => vga_clk0_bufg, -- Clock buffer output
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I => vga_clk0 -- Clock buffer input
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);
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BUFG_clk_out : BUFG
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BUFG_vga_clkfx : BUFG
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port map
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(
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O => vga_clk_out, -- Clock buffer output
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I => dcm0_clkfx -- Clock buffer input
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I => vga_clkfx -- Clock buffer input
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);
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sys_clk_out <= dcm0_clk0_bufg;
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inst_DCM_BASE_1 : DCM_BASE
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-- Compnent instantiation
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inst_DCM_SYS_FX : DCM_BASE
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generic map
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(
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CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
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CLKFX_DIVIDE => UTILS_FREQ_D(clk_in_freq_hz, sys_clk_out_freq_hz), -- Can be any interger from 1 to 32
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CLKFX_MULTIPLY => UTILS_FREQ_M(clk_in_freq_hz, sys_clk_out_freq_hz), -- Can be any integer from 2 to 32
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CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
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CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
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CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED
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CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
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DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE
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DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
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-- an integer from 0 to 15
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DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis
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DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
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DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
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FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
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PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023
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STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
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)
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port map
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(
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CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput
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CLK180 => open, -- 180 degree DCM CLK output
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CLK270 => open, -- 270 degree DCM CLK output
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CLK2X => open, -- 2X DCM CLK output
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CLK2X180 => open, -- 2X, 180 degree DCM CLK out
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CLK90 => open, -- 90 degree DCM CLK output
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CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
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CLKFX => sys_clkfx, -- DCM CLK synthesis out (M/D)
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CLKFX180 => open, -- 180 degree CLK synthesis out
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LOCKED => sys_fx_lock, -- DCM LOCK status output
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CLKFB => sys_clk0_bufg, -- DCM clock feedback
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CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM)
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RST => dcm_rst(0) -- DCM asynchronous reset input
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);
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BUFG_sys_clk0 : BUFG
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port map
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(
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O => sys_clk0_bufg, -- Clock buffer output
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I => sys_clk0 -- Clock buffer input
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);
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BUFG_sys_clkfx : BUFG
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port map
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(
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O => sys_clkfx_bufg, -- Clock buffer output
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I => sys_clkfx -- Clock buffer input
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);
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cpu_clk_out <= sys_clk0_bufg;
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sys_clk_out <= sys_clkfx_bufg;
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inst_DCM_SDRCLK_0 : DCM_BASE
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generic map
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(
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CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
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@@ -178,7 +204,7 @@ inst_DCM_BASE_1 : DCM_BASE
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CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
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CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
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CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
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CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
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CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
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CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
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CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
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DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
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@@ -189,29 +215,40 @@ inst_DCM_BASE_1 : DCM_BASE
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DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
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DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
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FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
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PHASE_SHIFT => sdr_clk0_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
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PHASE_SHIFT => sdr0_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
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STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
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)
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port map
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(
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CLK0 => dcm1_clk0, -- 0 degree DCM CLK ouptput
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CLK0 => sdr0_clk0, -- 0 degree DCM CLK ouptput
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CLK180 => open, -- 180 degree DCM CLK output
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CLK270 => dcm1_clk270, -- 270 degree DCM CLK output
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CLK270 => sdr0_clk270, -- 270 degree DCM CLK output
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CLK2X => open, -- 2X DCM CLK output
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CLK2X180 => open, -- 2X, 180 degree DCM CLK out
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CLK90 => open, -- 90 degree DCM CLK output
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CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
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CLKFX => open, -- DCM CLK synthesis out (M/D)
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CLKFX180 => open, -- 180 degree CLK synthesis out
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LOCKED => locked(1), -- DCM LOCK status output
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CLKFB => sdr_clk0_fb_in, -- DCM clock feedback
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CLKIN => dcm0_clk0_bufg, -- Clock input (from IBUFG, BUFG or DCM)
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LOCKED => sdr0_lock, -- DCM LOCK status output
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CLKFB => sdr0_clk_fb_in, -- DCM clock feedback
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CLKIN => sys_clkfx_bufg, -- Clock input (from IBUFG, BUFG or DCM)
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RST => dcm_rst(1) -- DCM asynchronous reset input
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);
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dcm_rst(1) <= not locked(0);
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inst_DCM_BASE_2 : DCM_BASE
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bufg_sdr0_clk0: bufg
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port map
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(
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o => sdr0_clk0_out,
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i => sdr0_clk0
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);
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bufg_sdr0_clk270: bufg
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port map (
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o => sdr0_clk270_out,
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i => sdr0_clk270
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);
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inst_DCM_SDRCLK_1 : DCM_BASE
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generic map
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(
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CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
|
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@@ -219,7 +256,7 @@ inst_DCM_BASE_1 : DCM_BASE
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CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
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CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32
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CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
|
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CLKIN_PERIOD => UTILS_PERIOD_NS(clk_in_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
|
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CLKIN_PERIOD => UTILS_PERIOD_NS(sys_clk_out_freq_hz), -- Specify period of input clock in ns from 1.25 to 1000.00
|
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CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED
|
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CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X
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DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE
|
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@@ -230,79 +267,95 @@ inst_DCM_BASE_1 : DCM_BASE
|
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DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL
|
||||
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
|
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FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0"
|
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PHASE_SHIFT => sdr_clk1_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
|
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PHASE_SHIFT => sdr1_clk_out_phaseshift, -- Amount of fixed phase shift from -255 to 1023
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STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
|
||||
)
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||||
port map
|
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(
|
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CLK0 => dcm2_clk0, -- 0 degree DCM CLK ouptput
|
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CLK0 => sdr1_clk0, -- 0 degree DCM CLK ouptput
|
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CLK180 => open, -- 180 degree DCM CLK output
|
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CLK270 => dcm2_clk270, -- 270 degree DCM CLK output
|
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CLK270 => sdr1_clk270, -- 270 degree DCM CLK output
|
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CLK2X => open, -- 2X DCM CLK output
|
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CLK2X180 => open, -- 2X, 180 degree DCM CLK out
|
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CLK90 => open, -- 90 degree DCM CLK output
|
||||
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
|
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CLKFX => open, -- DCM CLK synthesis out (M/D)
|
||||
CLKFX180 => open, -- 180 degree CLK synthesis out
|
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LOCKED => locked(2), -- DCM LOCK status output
|
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CLKFB => dcm2_clk0_bufg, -- DCM clock feedback
|
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CLKIN => sdr_clk0_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
|
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LOCKED => sdr1_lock, -- DCM LOCK status output
|
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CLKFB => sdr1_clk0_bufg, -- DCM clock feedback
|
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CLKIN => sdr0_clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM)
|
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RST => dcm_rst(2) -- DCM asynchronous reset input
|
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);
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dcm_rst(2) <= not locked(1);
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sdr1_clk0_out <= sdr1_clk0_bufg;
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bufg_sdr1_clk0: bufg
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port map
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(
|
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o => sdr1_clk0_bufg,
|
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i => sdr1_clk0
|
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);
|
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dcm_fsm:
|
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process(rst, clk_in)
|
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bufg_sdr1_clk270: bufg
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port map (
|
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o => sdr1_clk270_out,
|
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i => sdr1_clk270
|
||||
);
|
||||
|
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dcm_rst(0) <= reset_pipe0(reset_pipe0'left);
|
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|
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dcm_reset0:
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process(rst_in, clk_in)
|
||||
begin
|
||||
if rst = '1' then
|
||||
state_q <= s0;
|
||||
dcm_rst(0) <= '0';
|
||||
cnt_q <= "11111";
|
||||
error_out <= '0';
|
||||
locked_out <= '0';
|
||||
dcm0_locked <= (others => '0');
|
||||
dcm1_locked <= (others => '0');
|
||||
dcm2_locked <= (others => '0');
|
||||
if rst_in = '1' then
|
||||
reset_pipe0 <= (others => '1');
|
||||
elsif rising_edge(clk_in) then
|
||||
case state_q is
|
||||
when s0 =>
|
||||
state_q <= s1;
|
||||
|
||||
when s1 =>
|
||||
cnt_q <= cnt_q - 1;
|
||||
if cnt_q = 0 then
|
||||
dcm_rst(0) <= '1';
|
||||
state_q <= s2;
|
||||
end if;
|
||||
|
||||
when s2 =>
|
||||
cnt_q <= cnt_q - 1;
|
||||
if cnt_q = 0 then
|
||||
dcm_rst(0) <= '0';
|
||||
state_q <= s3;
|
||||
end if;
|
||||
|
||||
when s3 =>
|
||||
if dcm0_locked(2)='1' and dcm1_locked(2)='1' and dcm2_locked(2)='1' then
|
||||
state_q <= s4;
|
||||
error_out <= '0';
|
||||
end if;
|
||||
|
||||
when s4 =>
|
||||
if dcm0_locked(2)='1' and dcm1_locked(2)='1' and dcm2_locked(2)='1' then
|
||||
locked_out <= '1';
|
||||
else
|
||||
error_out <= '1';
|
||||
end if;
|
||||
end case;
|
||||
|
||||
-- synchronize 'dcm1_locked'
|
||||
dcm0_locked <= dcm0_locked(1 downto 0) & locked(0);
|
||||
dcm1_locked <= dcm1_locked(1 downto 0) & locked(1);
|
||||
dcm2_locked <= dcm2_locked(1 downto 0) & locked(2);
|
||||
|
||||
reset_pipe0 <= reset_pipe0(reset_pipe0'left-1 downto 0) & '0';
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
dcm_rst(1) <= reset_pipe1(reset_pipe1'left);
|
||||
|
||||
dcm_reset1:
|
||||
process(vga_fx_lock, clk_in)
|
||||
begin
|
||||
if vga_fx_lock = '0' then
|
||||
reset_pipe1 <= (others => '1');
|
||||
elsif rising_edge(clk_in) then
|
||||
reset_pipe1 <= reset_pipe1(reset_pipe1'left-1 downto 0) & '0';
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
dcm_rst(2) <= reset_pipe2(reset_pipe2'left);
|
||||
|
||||
dcm_reset2:
|
||||
process(sdr0_lock, clk_in)
|
||||
begin
|
||||
if sdr0_lock = '0' then
|
||||
reset_pipe2 <= (others => '1');
|
||||
elsif rising_edge(clk_in) then
|
||||
reset_pipe2 <= reset_pipe2(reset_pipe2'left-1 downto 0) & '0';
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
reset_out_logic:
|
||||
process(rst_in, clk_in)
|
||||
begin
|
||||
if rst_in = '1' or sdr0_lock = '0' or sdr1_lock = '0' or sys_fx_lock = '0' or vga_fx_lock = '0' then
|
||||
sys_rst_out <= '1';
|
||||
reset_cnt <= (reset_cnt'left downto reset_cnt'right => '1');
|
||||
elsif rising_edge(clk_in) then
|
||||
if reset_cnt /= (reset_cnt'left downto reset_cnt'right => '0') then
|
||||
reset_cnt <= reset_cnt - 1;
|
||||
else
|
||||
sys_rst_out <= '0';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
end architecture tech;
|
||||
|
||||
Reference in New Issue
Block a user