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- added dedicated sys_clk_out frequency synthesis

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- SDRAM clocks use sys_clk_out for clock generation
- added cpu_clk_out which is the same as sys_clk_in

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git-svn-id: http://moon:8086/svn/vhdl/trunk@727 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-07 19:16:11 +00:00
parent c42c0ba5b8
commit 023b7e42a3
5 changed files with 251 additions and 175 deletions
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projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
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@@ -31,6 +31,10 @@ NET "vga_clk" TNM_NET = "vga_clk";
TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 8.0 ns HIGH 50 %;
TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
NET "cpu_clk" TNM_NET = "cpu_clk";
TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %;
TIMESPEC "TS_unrelate_CPU" = FROM sys_clk TO cpu_clk TIG;
NET "sys_clk_in" LOC = "AE14";
NET sys_clk_in IOSTANDARD = LVCMOS33;
NET "sys_rst_n_in" LOC = "D6";