jens
0a601d2dd2
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@784 cc03376c-175c-47c8-b038-4cd826a8556b
294 lines
6.6 KiB
VHDL
294 lines
6.6 KiB
VHDL
-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/misc/flash_port_wb.vhd,v 1.2 2010-03-13 11:06:43 Jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.async_types.all;
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------------------------------------------------------------------
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entity flash_port_wb is
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Generic
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(
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f_sysclk : real := 100.0;
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addr_width : natural := 32;
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data_width : natural := 32;
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async_timespec : async_timespec_t
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);
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Port
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(
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CLK_I : in STD_LOGIC;
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RST_I : in STD_LOGIC;
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CYC_I : in STD_LOGIC;
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STB_I : in STD_LOGIC;
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WE_I : in STD_LOGIC;
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ACK_O : out STD_LOGIC;
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SRDY_O : out STD_LOGIC;
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MRDY_I : in STD_LOGIC;
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ADDR_I : in unsigned(31 downto 0);
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DAT_I : in unsigned(31 downto 0);
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DAT_O : out unsigned(31 downto 0);
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port_bsyi : in std_logic;
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port_bsyo : out std_logic;
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port_a : out unsigned(addr_width-1 downto 0);
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port_di : in unsigned(data_width-1 downto 0);
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port_do : out unsigned(data_width-1 downto 0);
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port_d_drv : out STD_LOGIC;
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port_wr : out STD_LOGIC;
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port_rd : out STD_LOGIC;
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flash_cs : out std_logic;
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flash_rst : out std_logic
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);
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end flash_port_wb;
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architecture Behavioral of flash_port_wb is
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type async_t is record
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cs : std_logic;
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wr : std_logic;
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rd : std_logic;
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rst : std_logic;
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drive_d : std_logic;
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end record;
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type async_state_t is (start, reset, idle, go, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
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signal s, sn : async_state_t;
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signal as : async_t;
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signal ack : std_logic;
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signal cc_rst : std_logic;
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signal cycle_cnt : natural range 0 to 31;
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signal cycle_reload : natural range 0 to 31;
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signal rdy : std_logic;
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signal rdyo : std_logic;
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signal en : std_logic;
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signal we_reg : std_logic;
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signal data_reg : unsigned(data_width-1 downto 0);
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signal addr_reg : unsigned(addr_width-1 downto 0);
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------------------------------------------------------------------
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begin
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SRDY_O <= CYC_I and rdyo;
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en <= CYC_I and STB_I;
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port_a <= addr_reg;
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port_do <= data_reg;
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port_d_drv <= as.drive_d;
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port_wr <= (not async_timespec.pol_we) xor as.wr;
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port_rd <= (not async_timespec.pol_oe) xor as.rd;
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proc_cycle_counter:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if cc_rst = '1' then
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cycle_cnt <= cycle_reload;
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elsif cycle_cnt /= 0 then
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cycle_cnt <= cycle_cnt - 1;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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proc_state_next:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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s <= start;
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else
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s <= sn;
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end if;
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end if;
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end process;
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proc_state:
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process(s, cycle_cnt, en, we_reg, port_bsyi)
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begin
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cycle_reload <= to_cycles(async_timespec.T_pulse_rst, f_sysclk);
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cc_rst <= '0';
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as.rst <= '0';
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as.cs <= '0';
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as.wr <= '0';
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as.rd <= '0';
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as.drive_d <= '0';
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ack <= '0';
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rdy <= '0';
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port_bsyo <= '1';
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sn <= s;
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case s is
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when start =>
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cc_rst <= '1';
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sn <= reset;
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when reset =>
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as.rst <= '1';
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if cycle_cnt = 0 then
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sn <= idle;
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end if;
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when idle =>
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port_bsyo <= '0';
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rdy <= '1';
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if en = '1' then
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sn <= go;
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end if;
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when go =>
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port_bsyo <= '0';
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if port_bsyi = '0' then
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as.cs <= '1';
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cc_rst <= '1';
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cycle_reload <= to_cycles(async_timespec.T_leadin, f_sysclk)-1;
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if we_reg = '0' then
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sn <= leadin_rd;
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else
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sn <= leadin_wr;
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end if;
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end if;
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when leadin_rd =>
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as.cs <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= to_cycles(async_timespec.T_pulse_rd, f_sysclk)-1;
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as.rd <= '1';
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sn <= read;
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end if;
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when leadin_wr =>
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as.cs <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= to_cycles(async_timespec.T_pulse_wr, f_sysclk)-1;
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as.wr <= '1';
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as.drive_d <= '1';
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sn <= write;
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end if;
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when read =>
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as.cs <= '1';
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as.rd <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
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-- as.rd <= '0';
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sn <= leadout_rd;
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ack <= '1';
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end if;
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when write =>
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as.drive_d <= '1';
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as.cs <= '1';
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as.wr <= '1';
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if cycle_cnt = 0 then
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as.wr <= '0';
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cc_rst <= '1';
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cycle_reload <= to_cycles(async_timespec.T_leadout, f_sysclk)-1;
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sn <= leadout_wr;
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-- ack <= '1';
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end if;
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when leadout_rd =>
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as.cs <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
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sn <= release;
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as.cs <= '0';
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end if;
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when leadout_wr =>
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as.cs <= '1';
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as.drive_d <= '1';
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if cycle_cnt = 0 then
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cc_rst <= '1';
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cycle_reload <= to_cycles(async_timespec.T_release, f_sysclk)-1;
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sn <= release;
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as.cs <= '0';
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end if;
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when release =>
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if cycle_cnt = 0 then
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sn <= idle;
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end if;
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when others =>
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sn <= idle;
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end case;
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end process;
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------------------------------------------------------------------
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output_ctrl:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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flash_cs <= (not async_timespec.pol_cs) xor as.cs;
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flash_rst <= (not async_timespec.pol_rst) xor as.rst;
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end if;
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end process;
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------------------------------------------------------------------
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din_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if as.rd = '1' then
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DAT_O(data_width-1 downto 0) <= port_di;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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data_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if en = '1' and rdy = '1' then
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we_reg <= WE_I;
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data_reg <= DAT_I(data_width-1 downto 0);
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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addr_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if en = '1' and rdy = '1' then
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addr_reg <= ADDR_I(addr_width-1 downto 0);
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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output_SRDY:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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rdyo <= '1';
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elsif en = '1' then
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rdyo <= rdy and not rdyo;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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output_ACK:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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ACK_O <= '0';
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else
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ACK_O <= ack;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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end Behavioral;
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