jens
2edaa4d7cb
git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
358 lines
8.2 KiB
VHDL
358 lines
8.2 KiB
VHDL
---------------------------------------------------------------------------------
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--COMMAND FORMAT --
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-- --
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-- write(column address(integer), bank(bit_vector), first data(integer), dqm(bit), cke(bit));--
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-- read(column address(integer), bank(bit_vector), dqm(bit), cke(bit)); --
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-- active(row address(integer), bank(bit_vector), data bus (integer), dqm(bit), cke(bit));--
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-- precharge(bank(bit_vector), address (integer), data bus(integer), dqm(bit), cke(bit)); --
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-- nop(data bus(integer), dqm(bit), cke(bit)); --
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-- burst_term(data bus(integer), dqm(bit_vector), cke(bit)); --
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-- load_array('1'); --
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-- load_mode_reg(register(integer), cke(bit)); --
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-- next_cycle(clk); This is used after every command(incl. nop) to clock --
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-- at the correct clock frequency entered in the clock --
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-- period constant below --
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-- unload_array(row_start(integer), row_end(integer), bank(bit_vector)) --
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-- load_mode_reg(op_code(integer)) --
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-- --
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---------------------------------------------------------------------------------
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LIBRARY work;
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE std.textio.all;
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USE work.generate_vectors.all;
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ENTITY vector_generate IS
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END vector_generate;
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ARCHITECTURE vector_generate OF vector_generate IS
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SIGNAL stim_done : BOOLEAN := FALSE;
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SIGNAL clk : BIT := '0';
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CONSTANT clk_start : time := 15 ns;
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CONSTANT clk_period : time := 10 ns;
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CONSTANT Z : INTEGER := -100;
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BEGIN
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PROCESS
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BEGIN
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WAIT UNTIL clk = '1' AND clk'EVENT;
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--------------------ENTER COMMANDS BELOW THIS LINE-----------------------------
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--******************DO NOT USE -100 FOR A DQ VALUE*************************----
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--*******************Z WILL PLACE HI-Z ON THE BUS**************************----
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--*******USE next_cycle(clk) FOR ADVANCING TO NEXT CLOCK CYCLE*************----
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nop(Z, "00", '1'); -- Always begin with one nop when using Micron's testbench
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next_cycle(clk); -- Load Memory Array
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load_array('1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk); -- Precharge All Banks
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precharge("00", 1024, Z, "00", '1');
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FOR i IN 1 to 2 LOOP
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next_cycle(clk);
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nop(Z, "00", '1');
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END LOOP;
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next_cycle(clk); -- First Auto Refresh
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auto_refresh;
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FOR i IN 1 TO 8 LOOP
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next_cycle(clk);
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nop(Z, "00", '1');
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END LOOP;
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next_cycle(clk); -- Second Auto Refresh
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auto_refresh;
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FOR i IN 1 TO 8 LOOP
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next_cycle(clk);
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nop(Z, "00", '1');
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END LOOP;
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next_cycle(clk); -- Load Mode Register (CAS Latency = 3, Burst Length = 8)
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load_mode_reg(51, '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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-- Write Section
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next_cycle(clk);
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active(0, "00", Z, "00", '1'); -- Activate Bank 0
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk); -- Write Bank 0
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write(0, "00", 10, "00", '1');
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next_cycle(clk);
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nop(11, "00", '1');
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next_cycle(clk);
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active(0, "01", 12, "00", '1'); -- Activate Bank 1
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next_cycle(clk);
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nop(13, "00", '1');
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next_cycle(clk);
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nop(14, "00", '1');
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next_cycle(clk);
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nop(15, "00", '1');
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next_cycle(clk);
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nop(16, "00", '1');
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next_cycle(clk);
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nop(17, "00", '1');
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next_cycle(clk);
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write(0, "01", 20, "00", '1'); -- Write Bank 1
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next_cycle(clk);
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precharge("00", 0, 21, "00", '1'); -- Precharge Bank 0
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next_cycle(clk);
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active(0, "10", 22, "00", '1'); -- Activate Bank 2
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next_cycle(clk);
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nop(23, "00", '1');
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next_cycle(clk);
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nop(24, "00", '1');
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next_cycle(clk);
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nop(25, "00", '1');
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next_cycle(clk);
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nop(26, "00", '1');
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next_cycle(clk);
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nop(27, "00", '1');
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next_cycle(clk);
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write(0, "10", 30, "00", '1'); -- Write Bank 2
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next_cycle(clk);
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precharge("01", 0, 31, "00", '1'); -- Precharge Bank 1
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next_cycle(clk);
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active(0, "11", 32, "00", '1'); -- Activate Bank 3
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next_cycle(clk);
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nop(33, "00", '1');
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next_cycle(clk);
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nop(34, "00", '1');
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next_cycle(clk);
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nop(35, "00", '1');
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next_cycle(clk);
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nop(36, "00", '1');
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next_cycle(clk);
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nop(37, "00", '1');
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next_cycle(clk);
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write(0, "11", 40, "00", '1'); -- Write Bank 3
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next_cycle(clk);
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precharge("10", 0, 41, "00", '1'); -- Precharge Bank 2
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next_cycle(clk);
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active(0, "00", 42, "00", '1'); -- Activate Bank 0
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next_cycle(clk);
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nop(43, "00", '1');
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next_cycle(clk);
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nop(44, "00", '1');
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next_cycle(clk);
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nop(45, "00", '1');
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next_cycle(clk);
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nop(46, "00", '1');
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next_cycle(clk);
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nop(47, "00", '1');
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-- Read Section
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next_cycle(clk);
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read(0, "00", "00", '1'); -- Read Bank 0
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next_cycle(clk);
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precharge("11", 0, Z, "00", '1'); -- Precharge Bank 3
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next_cycle(clk);
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active(0, "01", Z, "00", '1'); -- Activate Bank 1
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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read(0, "01", "00", '1'); -- Read Bank 1
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next_cycle(clk);
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precharge("00", 0, Z, "00", '1'); -- Precharge Bank 0
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next_cycle(clk);
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active(0, "10", Z, "00", '1'); -- Activate Bank 2
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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read(0, "10", "00", '1'); -- Read Bank 2
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next_cycle(clk);
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precharge("01", 0, Z, "00", '1'); -- Precharge Bank 1
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next_cycle(clk);
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active(0, "11", Z, "00", '1'); -- Activate Bank 3
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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read(0, "11", "00", '1'); -- Read Bank 3
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next_cycle(clk);
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precharge("10", 0, Z, "00", '1'); -- Precharge Bank 2
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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precharge("11", 0, Z, "00", '1'); -- Precharge Bank 3
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next_cycle(clk);
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nop(Z, "00", '1');
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next_cycle(clk);
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nop(Z, "00", '1');
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--next_cycle(clk); -- Unload Bank 0 Memory Array
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--unload_array(0, 3, "00");
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--next_cycle(clk); -- Unload Bank 1 Memory Array
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--unload_array(0, 3, "01");
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--next_cycle(clk); -- Unload Bank 2 Memory Array
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--unload_array(0, 3, "10");
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--next_cycle(clk); -- Unload Bank 3 Memory Array
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--unload_array(0, 3, "11");
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next_cycle(clk);
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nop(Z, "00", '1');
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stim_done <= TRUE; --always include this line at the end of your stimulus
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-------------------------------------------------------------------------------
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--*************************************************************************----
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END PROCESS;
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clock:
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PROCESS
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VARIABLE done_time : time;
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VARIABLE cycle_var : integer := 0;
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BEGIN
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cycle <= 0;
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clk <= '0';
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WAIT for clk_start;
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WHILE not stim_done loop
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clk <= '1';
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cycle <= cycle_var;
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WAIT for clk_period/2;
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cycle_var := cycle_var + 1;
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clk <= '0';
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WAIT for clk_period/2;
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END LOOP;
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ASSERT (FALSE)
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REPORT "Test Vectors Generated"
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SEVERITY note;
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WAIT;
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END PROCESS;
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END;
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