jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
1,039 Commits 7 Branches 23 Tags
f6e00c3922174cfaa150a5e2ed9d48dc79f0cd2d
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
S
Description
No description provided
23 MiB
Languages
VHDL 90.1%
Verilog 4.2%
Tcl 2.5%
SystemVerilog 0.8%
IGOR Pro 0.5%
Other 1.5%