jens
c02d1c0bbb
git-svn-id: http://moon:8086/svn/vhdl/trunk@1065 cc03376c-175c-47c8-b038-4cd826a8556b
484 lines
13 KiB
VHDL
484 lines
13 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:16:42 13.05.2007
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-- Design Name: tb_nco
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-- Module Name: tb_nco.vhd
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-- Project Name: nco
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library ieee_proposed;
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use ieee_proposed.math_utility_pkg.all;
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use ieee_proposed.fixed_pkg.all;
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library work;
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use work.fixed_util_pkg.all;
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use work.cordic_pkg.all;
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--use work.PCK_FIO.all;
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ENTITY tb_syn_ddc IS
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Generic
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(
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nbits_in : integer := 16;
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nbits_in_frac : integer := 14;
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nbits_out : integer := 32;
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nbits_out_frac : integer := 30;
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lo_nbits_phase : integer := 24;
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lo_nbits_freq : integer := 24;
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cic_nstages : integer := 5;
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cic_ratio : integer := 25;
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cic_scale_nbits : integer := 22;
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rfgen_nbits_phase : integer := 32;
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rfgen_nbits_freq : integer := 32
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);
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END tb_syn_ddc;
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ARCHITECTURE behavior OF tb_syn_ddc IS
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--Constants
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constant fa : REAL := 2.0**27;
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constant frf1 : REAL := 33.99E6;
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constant frf2 : REAL := 2.1E6;
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constant frf3 : REAL := 19.01E6;
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constant flo : REAL := 2.00E6;
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constant PERIOD_ADCCLK : time := 10 ns;
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constant PERIOD_USBCLK : time := 20 ns;
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constant PERIOD_IFCLK : time := 20 ns;
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SIGNAL rfgen1_freq_word : integer := integer(frf1/fa*2.0**rfgen_nbits_freq);
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SIGNAL rfgen2_freq_word : integer := integer(frf2/fa*2.0**rfgen_nbits_freq);
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SIGNAL rfgen3_freq_word : integer := integer(frf3/fa*2.0**rfgen_nbits_freq);
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SIGNAL lo_freq_word : integer := integer(flo/fa*2.0**lo_nbits_freq);
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SIGNAL ddc_freq_in : unsigned(lo_nbits_freq-1 downto 0) := (others => '0');
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SIGNAL ddc_phase_in : unsigned(lo_nbits_phase-1 downto 0) := (others => '0');
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--Inputs
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SIGNAL rst : std_logic := '1';
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SIGNAL adc_clk : std_logic := '0';
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SIGNAL adc_ofa : std_logic := '0';
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SIGNAL adc_rand : std_logic;
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SIGNAL adc_pga : std_logic;
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SIGNAL adc_dith : std_logic;
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SIGNAL adc_shdn : std_logic;
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SIGNAL adc_da : signed (15 downto 0);
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SIGNAL adc_da_vld : std_logic;
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SIGNAL usb_usbclk : std_logic := '0';
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SIGNAL usb_ifclk : std_logic := '0';
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SIGNAL usb_fd : signed (15 downto 0);
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SIGNAL usb_fifoadr : unsigned (1 downto 0);
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SIGNAL usb_pktend : std_logic;
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SIGNAL usb_slcs_n : std_logic;
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SIGNAL usb_slwr_n : std_logic;
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SIGNAL usb_slrd_n : std_logic;
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SIGNAL usb_sloe : std_logic;
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SIGNAL usb_flaga : std_logic := '0';
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SIGNAL usb_flagb : std_logic := '0';
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SIGNAL usb_flagc : std_logic := '0';
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SIGNAL cl_dout : unsigned (20 downto 0);
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SIGNAL cl_clk_out : std_logic;
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SIGNAL cl_pd_n : std_logic;
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SIGNAL reg_dio : unsigned (7 downto 0) := (others => 'Z');
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SIGNAL reg_aen : std_logic := '1';
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SIGNAL reg_oe : std_logic := '0';
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SIGNAL reg_we : std_logic := '0';
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SIGNAL rfgen_nco_rst : std_logic := '0';
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SIGNAL rfgen_nco_en : std_logic := '0';
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SIGNAL rfgen1_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
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SIGNAL rfgen1_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
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SIGNAL rfgen2_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
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SIGNAL rfgen2_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
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SIGNAL rfgen3_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
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SIGNAL rfgen3_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
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--Outputs
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signal rfgen_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
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signal rfgen_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(1.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen1_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen1_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen1_dout_vld : std_logic;
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SIGNAL rfgen2_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen2_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen2_dout_vld : std_logic;
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SIGNAL rfgen3_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen3_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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SIGNAL rfgen3_dout_vld : std_logic;
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SIGNAL fileout_enable : std_logic := '0';
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BEGIN
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inst_syn_ddc : entity work.syn_ddc
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GENERIC MAP
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(
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nbits_in => nbits_in,
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nbits_in_frac => nbits_in_frac,
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nbits_out => nbits_out,
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nbits_out_frac => nbits_out_frac,
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lo_nbits_phase => lo_nbits_phase,
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lo_nbits_freq => lo_nbits_freq,
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cic_nstages => cic_nstages,
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cic_ratio => cic_ratio,
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cic_scale_nbits => cic_scale_nbits
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)
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PORT MAP
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(
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rst => rst,
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adc_clk => adc_clk,
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adc_da => adc_da,
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adc_ofa => adc_ofa,
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adc_rand => adc_rand,
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adc_pga => adc_pga,
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adc_dith => adc_dith,
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adc_shdn => adc_shdn,
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usb_usbclk => usb_usbclk,
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usb_ifclk => usb_ifclk,
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usb_fd => usb_fd,
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usb_pktend => usb_pktend,
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usb_fifoadr => usb_fifoadr,
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usb_slcs_n => usb_slcs_n,
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usb_slwr_n => usb_slwr_n,
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usb_slrd_n => usb_slrd_n,
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usb_sloe => usb_sloe,
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usb_flaga => usb_flaga,
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usb_flagb => usb_flagb,
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usb_flagc => usb_flagc,
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cl_clk_out => cl_clk_out,
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cl_dout => cl_dout,
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cl_pd_n => cl_pd_n,
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reg_aen => reg_aen,
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reg_dio => reg_dio,
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reg_oe => reg_oe,
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reg_we => reg_we
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);
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rfgen1: entity work.mix
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GENERIC MAP
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(
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nbits_din => nbits_in,
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nbits_din_frac => nbits_in_frac,
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nbits_dout => nbits_in,
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nbits_dout_frac => nbits_in_frac,
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nbits_phase => rfgen_nbits_phase,
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nbits_freq => rfgen_nbits_freq
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)
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PORT MAP
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(
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rst => rst,
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clk => adc_clk,
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nco_rst => rfgen_nco_rst,
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nco_en => rfgen_nco_en,
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freq_in => rfgen1_freq_in,
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phase_in => rfgen1_phase_in,
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din_i => rfgen_din_i,
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din_q => rfgen_din_q,
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dout_i => rfgen1_dout_i,
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dout_q => rfgen1_dout_q,
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din_vld => '1',
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dout_vld => rfgen1_dout_vld
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);
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rfgen2: entity work.mix
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GENERIC MAP
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(
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nbits_din => nbits_in,
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nbits_din_frac => nbits_in_frac,
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nbits_dout => nbits_in,
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nbits_dout_frac => nbits_in_frac,
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nbits_phase => rfgen_nbits_phase,
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nbits_freq => rfgen_nbits_freq
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)
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PORT MAP
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(
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rst => rst,
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clk => adc_clk,
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nco_rst => rfgen_nco_rst,
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nco_en => rfgen_nco_en,
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freq_in => rfgen2_freq_in,
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phase_in => rfgen2_phase_in,
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din_i => rfgen_din_i,
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din_q => rfgen_din_q,
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dout_i => rfgen2_dout_i,
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dout_q => rfgen2_dout_q,
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din_vld => '1',
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dout_vld => rfgen2_dout_vld
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);
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rfgen3: entity work.mix
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GENERIC MAP
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(
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nbits_din => nbits_in,
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nbits_din_frac => nbits_in_frac,
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nbits_dout => nbits_in,
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nbits_dout_frac => nbits_in_frac,
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nbits_phase => rfgen_nbits_phase,
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nbits_freq => rfgen_nbits_freq
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)
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PORT MAP
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(
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rst => rst,
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clk => adc_clk,
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nco_rst => rfgen_nco_rst,
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nco_en => rfgen_nco_en,
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freq_in => rfgen3_freq_in,
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phase_in => rfgen3_phase_in,
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din_i => rfgen_din_i,
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din_q => rfgen_din_q,
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dout_i => rfgen3_dout_i,
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dout_q => rfgen3_dout_q,
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din_vld => '1',
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dout_vld => rfgen3_dout_vld
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);
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tb_adcclk : PROCESS
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BEGIN
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adc_clk <= not adc_clk;
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wait for PERIOD_ADCCLK/2;
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END PROCESS;
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tb_usbclk : PROCESS
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BEGIN
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usb_usbclk <= not usb_usbclk;
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wait for PERIOD_USBCLK/2;
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END PROCESS;
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tb_ifclk : PROCESS
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BEGIN
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usb_ifclk <= not usb_ifclk;
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wait for PERIOD_IFCLK/2;
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END PROCESS;
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rfgen_dout_i <= resize(0.333*rfgen1_dout_i + 0.333*rfgen2_dout_i + 0.333*rfgen3_dout_i, rfgen_dout_i);
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rfgen_dout_q <= resize(0.333*rfgen1_dout_q + 0.333*rfgen2_dout_q + 0.333*rfgen3_dout_q, rfgen_dout_q);
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adc_da <= to_signed(rfgen_dout_i);
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adc_da_vld <= rfgen1_dout_vld and rfgen2_dout_vld and rfgen3_dout_vld;
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tb : PROCESS
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BEGIN
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-- Wait 100 ns for global reset to finish
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wait for 400*PERIOD_USBCLK;
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rst <= '0';
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wait for 200*PERIOD_USBCLK;
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-------------------------------------------
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-- Program gains
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wait for 2*PERIOD_USBCLK;
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ddc_phase_in <= to_unsigned(0,lo_nbits_phase);
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ddc_freq_in <= to_unsigned(lo_freq_word,lo_nbits_freq);
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"10";
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reg_aen <= '1';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= ddc_freq_in(7 downto 0);
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reg_aen <= '0';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"11";
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reg_aen <= '1';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= ddc_freq_in(15 downto 8);
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reg_aen <= '0';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"12";
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reg_aen <= '1';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= ddc_freq_in(23 downto 16);
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reg_aen <= '0';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"13";
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reg_aen <= '1';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"00";
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reg_aen <= '0';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"20";
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reg_aen <= '1';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= ddc_phase_in(7 downto 0);
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reg_aen <= '0';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"21";
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reg_aen <= '1';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= ddc_phase_in(15 downto 8);
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reg_aen <= '0';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"22";
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reg_aen <= '1';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= ddc_phase_in(23 downto 16);
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reg_aen <= '0';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"23";
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reg_aen <= '1';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"00";
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reg_aen <= '0';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait for 200*PERIOD_USBCLK;
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fileout_enable <= '1';
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"00";
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reg_aen <= '1';
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reg_we <= '1';
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wait until rising_edge(usb_usbclk);
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reg_aen <= '0';
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reg_we <= '0';
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wait until rising_edge(usb_usbclk);
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reg_dio <= X"02";
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reg_aen <= '0';
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reg_we <= '1';
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wait;
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END PROCESS;
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rfgen_ctrl : PROCESS
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BEGIN
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wait until rising_edge(adc_clk) and rst = '0';
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rfgen1_freq_in <= to_unsigned(rfgen1_freq_word,rfgen_nbits_freq);
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rfgen1_phase_in <= to_unsigned(0,rfgen_nbits_phase);
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rfgen2_freq_in <= to_unsigned(rfgen2_freq_word,rfgen_nbits_freq);
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rfgen2_phase_in <= to_unsigned(0,rfgen_nbits_phase);
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rfgen3_freq_in <= to_unsigned(rfgen3_freq_word,rfgen_nbits_freq);
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rfgen3_phase_in <= to_unsigned(0,rfgen_nbits_phase);
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wait until rising_edge(adc_clk);
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rfgen_nco_en <= '1';
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wait;
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END PROCESS;
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END;
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