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git-svn-id: http://moon:8086/svn/vhdl/trunk@1065 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2014-07-24 06:33:46 +00:00
parent 714cf9990b
commit c02d1c0bbb
8 changed files with 2269 additions and 0 deletions
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lib/radio/ddc/sim/tb_syn_ddc.fdo
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vmap ieee_proposed ../../../../Common/sim/ieee_proposed
vlib work
vcom -explicit -93 "../../../fixed/fixed_util_pkg.vhd"
vcom -explicit -93 "../../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../../misc/dpram_1w1r.vhd"
vcom -explicit -93 "../../../filter/src/filter_pkg.vhd"
vcom -explicit -93 "../../../filter/src/fir_pkg.vhd"
vcom -explicit -93 "../../../filter/src/fir_stage_sys.vhd"
vcom -explicit -93 "../../../filter/src/delay_line.vhd"
vcom -explicit -93 "../../../filter/src/fir_semi_parallel.vhd"
vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pkg.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_stage.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd"
vcom -explicit -93 "../../nco/src/mix_cordic.vhd"
vcom -explicit -93 "../../decimator/CIC/src/cic_i_pipe.vhd"
vcom -explicit -93 "../../decimator/CIC/src/cic_c_pipe.vhd"
vcom -explicit -93 "../../decimator/CIC/src/cic_decim_pipe.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd"
vcom -explicit -93 "../../../FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
vcom -explicit -93 "../../../FIFO/src/fifo_async.vhd"
vcom -explicit -93 "../src/ddc.vhd"
vcom -explicit -93 "../src/syn_ddc.vhd"
vcom -explicit -93 "../src/tb_syn_ddc.vhd"
vsim -t 1ps -lib work tb_syn_ddc
do {tb_syn_ddc.wdo}
view wave
view structure
view signals
run 500us
lib/radio/ddc/sim/tb_syn_ddc.wdo
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_syn_ddc/rst
add wave -noupdate -format Logic /tb_syn_ddc/rst
add wave -noupdate -format Logic /tb_syn_ddc/adc_clk
add wave -noupdate -format Logic /tb_syn_ddc/adc_ofa
add wave -noupdate -format Logic /tb_syn_ddc/adc_rand
add wave -noupdate -format Logic /tb_syn_ddc/adc_pga
add wave -noupdate -format Logic /tb_syn_ddc/adc_dith
add wave -noupdate -format Logic /tb_syn_ddc/adc_shdn
add wave -noupdate -format Literal -radix decimal /tb_syn_ddc/adc_da
add wave -noupdate -format Logic /tb_syn_ddc/adc_da_vld
add wave -noupdate -format Logic /tb_syn_ddc/usb_usbclk
add wave -noupdate -format Logic /tb_syn_ddc/usb_ifclk
add wave -noupdate -format Literal /tb_syn_ddc/usb_fd
add wave -noupdate -format Literal /tb_syn_ddc/usb_fifoadr
add wave -noupdate -format Logic /tb_syn_ddc/usb_pktend
add wave -noupdate -format Logic /tb_syn_ddc/usb_slcs_n
add wave -noupdate -format Logic /tb_syn_ddc/usb_slwr_n
add wave -noupdate -format Logic /tb_syn_ddc/usb_slrd_n
add wave -noupdate -format Logic /tb_syn_ddc/usb_sloe
add wave -noupdate -format Logic /tb_syn_ddc/usb_flaga
add wave -noupdate -format Logic /tb_syn_ddc/usb_flagb
add wave -noupdate -format Logic /tb_syn_ddc/usb_flagc
add wave -noupdate -format Literal -radix hexadecimal /tb_syn_ddc/cl_dout
add wave -noupdate -format Logic /tb_syn_ddc/cl_clk_out
add wave -noupdate -format Logic /tb_syn_ddc/cl_pd_n
add wave -noupdate -format Literal /tb_syn_ddc/reg_dio
add wave -noupdate -format Logic /tb_syn_ddc/reg_aen
add wave -noupdate -format Logic /tb_syn_ddc/reg_oe
add wave -noupdate -format Logic /tb_syn_ddc/reg_we
add wave -noupdate -format Logic /tb_syn_ddc/rfgen_nco_rst
add wave -noupdate -format Logic /tb_syn_ddc/rfgen_nco_en
add wave -noupdate -format Literal /tb_syn_ddc/rfgen1_freq_in
add wave -noupdate -format Literal /tb_syn_ddc/rfgen1_phase_in
add wave -noupdate -format Literal /tb_syn_ddc/rfgen2_freq_in
add wave -noupdate -format Literal /tb_syn_ddc/rfgen2_phase_in
add wave -noupdate -format Literal /tb_syn_ddc/rfgen3_freq_in
add wave -noupdate -format Literal /tb_syn_ddc/rfgen3_phase_in
add wave -noupdate -format Literal /tb_syn_ddc/rfgen_din_i
add wave -noupdate -format Literal /tb_syn_ddc/rfgen_din_q
add wave -noupdate -format Literal /tb_syn_ddc/rfgen_dout_i
add wave -noupdate -format Literal /tb_syn_ddc/rfgen_dout_q
add wave -noupdate -format Literal /tb_syn_ddc/rfgen1_dout_i
add wave -noupdate -format Literal /tb_syn_ddc/rfgen1_dout_q
add wave -noupdate -format Logic /tb_syn_ddc/rfgen1_dout_vld
add wave -noupdate -format Literal /tb_syn_ddc/rfgen2_dout_i
add wave -noupdate -format Literal /tb_syn_ddc/rfgen2_dout_q
add wave -noupdate -format Logic /tb_syn_ddc/rfgen2_dout_vld
add wave -noupdate -format Literal /tb_syn_ddc/rfgen3_dout_i
add wave -noupdate -format Literal /tb_syn_ddc/rfgen3_dout_q
add wave -noupdate -format Logic /tb_syn_ddc/rfgen3_dout_vld
add wave -noupdate -format Logic /tb_syn_ddc/fileout_enable
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {287711864 ps} 0} {{Cursor 2} {4988927 ps} 0}
configure wave -namecolwidth 97
configure wave -valuecolwidth 55
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 100
configure wave -griddelta 40
configure wave -timeline 1
update
WaveRestoreZoom {0 ps} {525 us}
lib/radio/ddc/src/ddc.vhd.bak
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.utils_pkg.all;
use work.fixed_util_pkg.all;
use work.filter_pkg.all;
use work.fir_pkg.all;
ENTITY ddc IS
Generic
(
nbits_in : integer := 18;
nbits_in_frac : integer := 16;
nbits_out : integer := 18;
nbits_out_frac : integer := 16;
lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20;
cic_nstages : integer := 3;
cic_ratio : integer := 64;
cic_scale_nbits : integer := 18
);
PORT
(
rst : in std_logic;
clk : in std_logic;
lo_nco_rst : in std_logic;
lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
din_i : in sfixed;
din_q : in sfixed;
din_vld : in std_logic;
dec_i : out sfixed;
dec_q : out sfixed;
dec_vld : out std_logic;
dout_i : out sfixed;
dout_q : out sfixed;
dout_vld : out std_logic
);
END ddc;
ARCHITECTURE behavior OF ddc IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mix
GENERIC
(
nbits_din : integer;
nbits_din_frac : integer;
nbits_dout : integer;
nbits_dout_frac : integer;
nbits_phase : integer;
nbits_freq : integer
);
PORT
(
rst : in std_logic;
clk : in std_logic;
nco_rst : in std_logic;
nco_en : in std_logic;
freq_in : in unsigned(nbits_freq-1 downto 0);
phase_in : in unsigned(nbits_phase-1 downto 0);
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
dout_q : out sfixed;
din_vld : in std_logic;
dout_vld : out std_logic
);
END COMPONENT;
COMPONENT cic_decim_pipe
GENERIC
(
nstages : integer;
ratio : integer;
scale_nbits : integer;
in_width : integer;
in_width_frac : integer;
out_width : integer;
out_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
COMPONENT fifo_sync
GENERIC
(
addr_width : natural;
data_width : natural;
almost_full_thresh : integer;
almost_empty_thresh : integer
);
PORT
(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
we : in STD_LOGIC;
re : in STD_LOGIC;
fifo_full : out STD_LOGIC;
fifo_empty : out STD_LOGIC;
fifo_afull : out STD_LOGIC;
fifo_aempty : out STD_LOGIC;
data_w : in unsigned (data_width-1 downto 0);
data_r : out unsigned (data_width-1 downto 0)
);
END COMPONENT;
COMPONENT fir_semi_parallel
GENERIC
(
ntaps_per_stage : integer;
nstages : integer;
mul_latency : integer;
nbits_in : integer;
nbits_in_frac : integer;
nbits_stages : integer;
nbits_stages_frac : integer;
nbits_out : integer;
nbits_out_frac : integer
);
PORT
(
rst : in std_logic;
clk : in std_logic;
h_addr : in natural range 0 to nstages*ntaps_per_stage-1;
h_we : in std_logic;
h_in : in sfixed;
din_vld : in std_logic;
din : in sfixed;
dout_vld : out std_logic;
rdy : out std_logic;
dout : out sfixed
);
END COMPONENT;
constant lo_nbits_in : integer := nbits_in;
constant lo_nbits_in_frac : integer := nbits_in_frac;
constant lo_nbits_out : integer := nbits_in;
constant lo_nbits_out_frac : integer := nbits_in_frac;
constant cic_nbits_in : integer := lo_nbits_out;
constant cic_nbits_in_frac : integer := lo_nbits_out_frac;
constant cic_nbits_out : integer := nbits_out+1;
constant cic_nbits_out_frac : integer := nbits_out_frac+1;
constant cfir_mul_latency : integer := 5;
constant cfir_ntaps : integer := 63;
constant cfir_nstages : integer := 2;
constant cfir_nbits_in : integer := cic_nbits_out;
constant cfir_nbits_in_frac : integer := cic_nbits_out_frac;
constant cfir_nbits_out : integer := nbits_out;
constant cfir_nbits_out_frac : integer := nbits_out_frac;
constant cfir_nbits_stages : integer := cfir_nbits_in;
constant cfir_nbits_stages_frac : integer := cfir_nbits_in_frac;
constant cfir_ntaps_per_stage : integer := NextPowerOfTwo(cfir_ntaps)/cfir_nstages;
SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
SIGNAL mix_dout_vld : std_logic;
SIGNAL dec_dout_i : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
SIGNAL dec_dout_q : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
SIGNAL dec_dout_vld_i : std_logic;
SIGNAL dec_dout_vld_q : std_logic;
SIGNAL cfir_h_data : sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
SIGNAL cfir_h_addr : natural range 0 to NextPowerOfTwo(cfir_ntaps)-1;
SIGNAL cfir_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL cfir_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL cfir_h_we : std_logic;
SIGNAL cfir_vld_i : std_logic;
SIGNAL cfir_vld_q : std_logic;
SIGNAL cfir_ready_i : std_logic;
SIGNAL cfir_ready_q : std_logic;
SIGNAL cfir_start_i : std_logic;
SIGNAL cfir_start_q : std_logic;
SIGNAL cfir_din_vld_i : std_logic;
SIGNAL cfir_din_vld_q : std_logic;
SIGNAL cfir_din_i : sfixed(shi(cfir_nbits_in, cfir_nbits_in_frac) downto slo(cfir_nbits_in, cfir_nbits_in_frac));
SIGNAL cfir_din_q : sfixed(shi(cfir_nbits_in, cfir_nbits_in_frac) downto slo(cfir_nbits_in, cfir_nbits_in_frac));
SIGNAL cfir_write_i : std_logic;
SIGNAL cfir_write_q : std_logic;
SIGNAL fifo_empty_i : std_logic;
SIGNAL fifo_empty_q : std_logic;
SIGNAL fifo_full_i : std_logic;
SIGNAL fifo_full_q : std_logic;
SIGNAL fifo_din_i : unsigned(cfir_nbits_in-1 downto 0);
SIGNAL fifo_din_q : unsigned(cfir_nbits_in-1 downto 0);
SIGNAL fifo_dout_i : unsigned(cfir_nbits_in-1 downto 0);
SIGNAL fifo_dout_q : unsigned(cfir_nbits_in-1 downto 0);
constant cfir_coef : real_array_t(0 to cfir_ntaps-1) := FilterCoef_Lowpass(cfir_ntaps, 0.40, 1.0);
type h_mem_t is array (0 to cfir_ntaps-1) of sfixed(shi(cfir_nbits_stages, cfir_nbits_stages_frac) downto slo(cfir_nbits_stages, cfir_nbits_stages_frac));
function to_h_mem(coef_real : real_array_t; ntaps : integer; proto : sfixed) return h_mem_t is
variable res : h_mem_t;
begin
for i in 0 to ntaps-1 loop
res(i) := to_sfixed(coef_real(i), proto, fixed_wrap, fixed_round);
end loop;
return res;
end to_h_mem;
SIGNAL hclr_mode : std_logic;
CONSTANT h_mem : h_mem_t := to_h_mem(cfir_coef, cfir_ntaps, cfir_h_data);
BEGIN
-- assert false report "cfir_h_addr_i'length = " & natural'image(cfir_h_addr_i'length) & "." severity note;
dec_vld <= dec_dout_vld_i and dec_dout_vld_q;
dec_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dec_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dout_vld <= cfir_vld_i and cfir_vld_q;
dout_i <= resize(cfir_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dout_q <= resize(cfir_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-- cfir_start <= dec_dout_vld_i and dec_dout_vld_q;
-- Instantiate the Unit Under Test (UUT)
inst_mixer: mix
GENERIC MAP
(
nbits_din => lo_nbits_in,
nbits_din_frac => lo_nbits_in_frac,
nbits_dout => lo_nbits_out,
nbits_dout_frac => lo_nbits_out_frac,
nbits_phase => lo_nbits_phase,
nbits_freq => lo_nbits_freq
)
PORT MAP
(
rst => rst,
clk => clk,
nco_rst => lo_nco_rst,
nco_en => lo_nco_en,
freq_in => lo_freq_in,
phase_in => lo_phase_in,
din_i => din_i,
din_q => din_q,
dout_i => mix_dout_i,
dout_q => mix_dout_q,
din_vld => din_vld,
dout_vld => mix_dout_vld
);
inst_cic_decim_pipe_I : cic_decim_pipe
GENERIC MAP
(
nstages => cic_nstages,
ratio => cic_ratio,
scale_nbits => cic_scale_nbits,
in_width => cic_nbits_in,
in_width_frac => cic_nbits_in_frac,
out_width => cic_nbits_out,
out_width_frac => cic_nbits_out_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => mix_dout_vld,
din => mix_dout_i,
dout => dec_dout_i,
vld_out => dec_dout_vld_i
);
inst_cic_decim_pipe_Q : cic_decim_pipe
GENERIC MAP
(
nstages => cic_nstages,
ratio => cic_ratio,
scale_nbits => cic_scale_nbits,
in_width => cic_nbits_in,
in_width_frac => cic_nbits_in_frac,
out_width => cic_nbits_out,
out_width_frac => cic_nbits_out_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => mix_dout_vld,
din => mix_dout_q,
dout => dec_dout_q,
vld_out => dec_dout_vld_q
);
cfir_I : entity work.fir_semi_parallel
GENERIC MAP
(
ntaps_per_stage => cfir_ntaps_per_stage,
nstages => cfir_nstages,
mul_latency => cfir_mul_latency,
nbits_in => cfir_nbits_in,
nbits_in_frac => cfir_nbits_in_frac,
nbits_stages => cfir_nbits_stages,
nbits_stages_frac => cfir_nbits_stages_frac,
nbits_out => cfir_nbits_out,
nbits_out_frac => cfir_nbits_out_frac
)
PORT MAP
(
rst => rst,
clk => clk,
h_addr => cfir_h_addr,
h_we => cfir_h_we,
h_in => cfir_h_data,
din_vld => cfir_din_vld_i,
din => cfir_din_i,
dout_vld => cfir_vld_i,
start => cfir_start_i,
rdy => cfir_ready_i,
dout => cfir_dout_i
);
cfir_Q : entity work.fir_semi_parallel
GENERIC MAP
(
ntaps_per_stage => cfir_ntaps_per_stage,
nstages => cfir_nstages,
mul_latency => cfir_mul_latency,
nbits_in => cfir_nbits_in,
nbits_in_frac => cfir_nbits_in_frac,
nbits_stages => cfir_nbits_stages,
nbits_stages_frac => cfir_nbits_stages_frac,
nbits_out => cfir_nbits_out,
nbits_out_frac => cfir_nbits_out_frac
)
PORT MAP
(
rst => rst,
clk => clk,
h_addr => cfir_h_addr,
h_we => cfir_h_we,
h_in => cfir_h_data,
din_vld => cfir_din_vld_q,
din => cfir_din_q,
dout_vld => cfir_vld_q,
start => cfir_start_q,
rdy => cfir_ready_q,
dout => cfir_dout_q
);
cfir_din_vld_i <= not fifo_empty_i and cfir_ready_i and cfir_write_i;
cfir_start_i <= fifo_empty_i and cfir_write_i;
fifo_din_i <= to_unsigned(ufixed(dec_dout_i));
cfir_din_i <= sfixed(fifo_dout_i);
-- cfir_din_vld_i <= dec_dout_vld_i;
-- cfir_start_i <= dec_dout_vld_i;
--
-- cfir_din_i <= dec_dout_i;
inst_fifo_sync_i : fifo_sync
GENERIC MAP
(
addr_width => 1,
data_width => cfir_nbits_in,
almost_full_thresh => 1,
almost_empty_thresh => 1
)
PORT MAP
(
rst => rst,
clk => clk,
we => dec_dout_vld_i,
re => cfir_write_i,
fifo_full => fifo_full_i,
fifo_empty => fifo_empty_i,
fifo_afull => open,
fifo_aempty => open,
data_w => fifo_din_i,
data_r => fifo_dout_i
);
cfir_din_vld_q <= not fifo_empty_q and cfir_ready_q and cfir_write_q;
cfir_start_q <= fifo_empty_q and cfir_write_q;
fifo_din_q <= to_unsigned(ufixed(dec_dout_q));
cfir_din_q <= sfixed(fifo_dout_q);
-- cfir_din_vld_q <= dec_dout_vld_q;
-- cfir_start_q <= dec_dout_vld_q;
--
-- cfir_din_q <= dec_dout_q;
inst_fifo_sync_q : fifo_sync
GENERIC MAP
(
addr_width => 1,
data_width => cfir_nbits_in,
almost_full_thresh => 1,
almost_empty_thresh => 1
)
PORT MAP
(
rst => rst,
clk => clk,
we => dec_dout_vld_q,
re => cfir_write_q,
fifo_full => fifo_full_q,
fifo_empty => fifo_empty_q,
fifo_afull => open,
fifo_aempty => open,
data_w => fifo_din_q,
data_r => fifo_dout_q
);
cfir_write_logic_i:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
cfir_write_i <= '0';
elsif fifo_full_i = '1' then
cfir_write_i <= '1';
elsif fifo_empty_i = '1' then
cfir_write_i <= '0';
end if;
end if;
end process;
cfir_write_logic_q:
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
cfir_write_q <= '0';
elsif fifo_full_q = '1' then
cfir_write_q <= '1';
elsif fifo_empty_q = '1' then
cfir_write_q <= '0';
end if;
end if;
end process;
coef_load_counter:
process(clk)
variable count : natural range 0 to NextPowerOfTwo(cfir_ntaps)-1;
variable we : std_logic;
begin
if rising_edge(clk) then
cfir_h_addr <= count;
cfir_h_we <= we;
if rst = '1' then
we := '1';
hclr_mode <= '1';
count := 0;
else
if hclr_mode = '1' then
cfir_h_data <= to_sfixed(0.0, cfir_h_data);
if count /= NextPowerOfTwo(cfir_ntaps)-1 then
we := '1';
count := count + 1;
else
count := 0;
hclr_mode <= '0';
end if;
else
cfir_h_data <= h_mem(count);
if count /= cfir_ntaps-1 then
we := '1';
count := count + 1;
else
we := '0';
end if;
end if;
end if;
end if;
end process;
END;
lib/radio/ddc/src/ddc_var.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
ENTITY ddc IS
Generic
(
nbits_in : integer := 18;
nbits_in_frac : integer := 16;
nbits_out : integer := 18;
nbits_out_frac : integer := 16;
lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20;
cic_nstages : integer := 3;
cic_max_ratio : integer := 4096;
cic_max_diff_delay : integer := 2;
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 32
);
PORT
(
rst : in std_logic;
clk : in std_logic;
lo_nco_rst : in std_logic;
lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
dout_q : out sfixed;
din_vld : in std_logic;
dout_vld : out std_logic
);
END ddc;
ARCHITECTURE behavior OF ddc IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mix
GENERIC
(
nbits_din : integer;
nbits_din_frac : integer;
nbits_dout : integer;
nbits_dout_frac : integer;
nbits_phase : integer;
nbits_freq : integer
);
PORT
(
rst : in std_logic;
clk : in std_logic;
nco_rst : in std_logic;
nco_en : in std_logic;
freq_in : in unsigned(nbits_freq-1 downto 0);
phase_in : in unsigned(nbits_phase-1 downto 0);
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
dout_q : out sfixed;
din_vld : in std_logic;
dout_vld : out std_logic
);
END COMPONENT;
COMPONENT cic_decim_pipe
GENERIC
(
nstages : integer;
ratio_max : integer;
scale_nbits_min : integer;
scale_nbits_max : integer;
max_diff_delay : integer;
in_width : integer;
in_width_frac : integer;
out_width : integer;
out_width_frac : integer
);
PORT
(
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
ratio : in natural range 1 to ratio_max;
diff_delay : in natural range 1 to max_diff_delay;
shift_in : in natural range 0 to scale_nbits_max;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
constant lo_nbits_in : integer := nbits_in;
constant lo_nbits_in_frac : integer := nbits_in_frac;
constant lo_nbits_out : integer := nbits_in;
constant lo_nbits_out_frac : integer := nbits_in_frac;
constant cic_nbits_in : integer := lo_nbits_out;
constant cic_nbits_in_frac : integer := lo_nbits_out_frac;
constant cic_nbits_out : integer := nbits_out;
constant cic_nbits_out_frac : integer := nbits_out_frac;
SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
SIGNAL mix_dout_vld : std_logic;
SIGNAL dec_dout_i : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
SIGNAL dec_dout_q : sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
SIGNAL dec_dout_vld_i : std_logic;
SIGNAL dec_dout_vld_q : std_logic;
BEGIN
dout_vld <= dec_dout_vld_i and dec_dout_vld_q;
dout_i <= dec_dout_i;
dout_q <= dec_dout_q;
-- Instantiate the Unit Under Test (UUT)
inst_mixer: mix
GENERIC MAP
(
nbits_din => lo_nbits_in,
nbits_din_frac => lo_nbits_in_frac,
nbits_dout => lo_nbits_out,
nbits_dout_frac => lo_nbits_out_frac,
nbits_phase => lo_nbits_phase,
nbits_freq => lo_nbits_freq
)
PORT MAP
(
rst => rst,
clk => clk,
nco_rst => lo_nco_rst,
nco_en => lo_nco_en,
freq_in => lo_freq_in,
phase_in => lo_phase_in,
din_i => din_i,
din_q => din_q,
dout_i => mix_dout_i,
dout_q => mix_dout_q,
din_vld => din_vld,
dout_vld => mix_dout_vld
);
inst_cic_decim_pipe_I : cic_decim_pipe
GENERIC MAP
(
nstages => cic_nstages,
ratio_max => cic_max_ratio,
scale_nbits_min => cic_scale_nbits_min,
scale_nbits_max => cic_scale_nbits_max,
max_diff_delay => cic_max_diff_delay,
in_width => cic_nbits_in,
in_width_frac => cic_nbits_in_frac,
out_width => cic_nbits_out,
out_width_frac => cic_nbits_out_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => mix_dout_vld,
ratio => cic_ratio,
diff_delay => cic_diff_delay,
shift_in => cic_shift_in,
din => mix_dout_i,
dout => dec_dout_i,
vld_out => dec_dout_vld_i
);
inst_cic_decim_pipe_Q : cic_decim_pipe
GENERIC MAP
(
nstages => cic_nstages,
ratio_max => cic_max_ratio,
scale_nbits_min => cic_scale_nbits_min,
scale_nbits_max => cic_scale_nbits_max,
max_diff_delay => cic_max_diff_delay,
in_width => cic_nbits_in,
in_width_frac => cic_nbits_in_frac,
out_width => cic_nbits_out,
out_width_frac => cic_nbits_out_frac
)
PORT MAP
(
clk => clk,
rst => rst,
vld_in => mix_dout_vld,
ratio => cic_ratio,
diff_delay => cic_diff_delay,
shift_in => cic_shift_in,
din => mix_dout_q,
dout => dec_dout_q,
vld_out => dec_dout_vld_q
);
END;
lib/radio/ddc/src/syn_ddc.vhd.bak
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library altera;
use altera.altera_syn_attributes.all;
library work;
use work.fixed_util_pkg.all;
ENTITY syn_ddc IS
Generic
(
nbits_in : integer := 16;
nbits_in_frac : integer := 14;
nbits_out : integer := 32;
nbits_out_frac : integer := 30;
lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20;
cic_nstages : integer := 5;
cic_ratio : integer := 25;
cic_scale_nbits : integer := 22
);
PORT
(
rst : in std_logic;
adc_clk : in std_logic;
adc_da : in signed(15 downto 0);
adc_ofa : in std_logic;
adc_rand : out std_logic;
adc_pga : out std_logic;
adc_dith : out std_logic;
adc_shdn : out std_logic;
usb_usbclk : in std_logic;
usb_ifclk : in std_logic;
usb_fd : out signed(15 downto 0);
usb_pktend : out std_logic;
usb_fifoadr : out unsigned(1 downto 0);
usb_slcs_n : out std_logic;
usb_slwr_n : out std_logic;
usb_slrd_n : out std_logic;
usb_sloe : out std_logic;
usb_flaga : in std_logic;
usb_flagb : in std_logic;
usb_flagc : in std_logic;
cl_clk_out : out std_logic;
cl_dout : out unsigned(23 downto 0);
cl_pat_sel : out std_logic;
cl_prbs_en : out std_logic;
cl_ds_opt : out std_logic;
cl_bal : out std_logic;
cl_pd_n : out std_logic;
cl_tsen : in std_logic;
reg_aen : in std_logic;
reg_dio : inout unsigned(7 downto 0);
reg_oe : in std_logic;
reg_we : in std_logic
);
END syn_ddc;
ARCHITECTURE behavior OF syn_ddc IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ddc
GENERIC
(
nbits_in : integer;
nbits_in_frac : integer;
nbits_out : integer;
nbits_out_frac : integer;
lo_nbits_phase : integer;
lo_nbits_freq : integer;
cic_nstages : integer;
cic_ratio : integer;
cic_scale_nbits : integer
);
PORT
(
rst : in std_logic;
clk : in std_logic;
lo_nco_rst : in std_logic;
lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
din_vld : in std_logic;
din_i : in sfixed;
din_q : in sfixed;
dec_vld : out std_logic;
dec_i : out sfixed;
dec_q : out sfixed;
dout_vld : out std_logic;
dout_i : out sfixed;
dout_q : out sfixed
);
END COMPONENT;
--Outputs
SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL ddc_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL dec_vld : std_logic;
SIGNAL ddc_dec_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL ddc_dec_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL reg_lo_nco_rst : std_logic;
SIGNAL reg_lo_nco_en : std_logic;
SIGNAL reg_lo_freq_in : unsigned(31 downto 0);
SIGNAL reg_lo_phase_in : unsigned(31 downto 0);
SIGNAL reg_en_addr : std_logic;
SIGNAL reg_en_data : std_logic;
SIGNAL reg_addr_last : std_logic;
SIGNAL reg_data_last : std_logic;
SIGNAL reg_addr_async : unsigned (7 downto 0);
SIGNAL reg_data_async : unsigned (7 downto 0);
SIGNAL reg_addr : unsigned (7 downto 0);
SIGNAL reg_data : unsigned (7 downto 0);
SIGNAL fifo_usb_we : std_logic;
SIGNAL fifo_usb_re : std_logic;
SIGNAL fifo_usb_ff : std_logic;
SIGNAL fifo_usb_ef : std_logic;
SIGNAL fifo_usb_aff : std_logic;
SIGNAL fifo_usb_aef : std_logic;
type fifo_usb_array_t is array (0 to 3) of unsigned (15 downto 0);
SIGNAL fifo_usb_in : fifo_usb_array_t;
SIGNAL fifo_usb_out : unsigned (15 downto 0);
SIGNAL fifo_usb_we_pipe : unsigned(3 downto 0);
SIGNAL enable : std_logic;
SIGNAL ddc_din_vld : std_logic;
SIGNAL ddc_dout_vld : std_logic;
SIGNAL cl_we_pipe : unsigned(1 downto 0);
type cl_data_array_t is array (0 to 1) of unsigned (31 downto 0);
SIGNAL cl_sd_data : cl_data_array_t;
SIGNAL cl_dout_L : std_logic_vector(24 downto 0);
SIGNAL cl_dout_H : std_logic_vector(24 downto 0);
SIGNAL cl_dout_clk : std_logic_vector(24 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
inst_ddc : ddc
GENERIC MAP
(
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac,
lo_nbits_phase => lo_nbits_phase,
lo_nbits_freq => lo_nbits_freq,
cic_nstages => cic_nstages,
cic_ratio => cic_ratio,
cic_scale_nbits => cic_scale_nbits
)
PORT MAP
(
rst => rst,
clk => adc_clk,
lo_nco_rst => reg_lo_nco_rst,
lo_nco_en => reg_lo_nco_en,
lo_freq_in => reg_lo_freq_in(lo_nbits_freq-1 downto 0),
lo_phase_in => reg_lo_phase_in(lo_nbits_phase-1 downto 0),
din_vld => ddc_din_vld,
din_i => ddc_din_i,
din_q => ddc_din_q,
dec_vld => dec_vld,
dec_i => ddc_dec_i,
dec_q => ddc_dec_q,
dout_vld => ddc_dout_vld,
dout_i => ddc_dout_i,
dout_q => ddc_dout_q
);
reg_dio <= reg_addr when reg_oe = '1' else (others => 'Z');
----------------------------------------------------------
-- Register control
----------------------------------------------------------
proc_reg_da_async:
process(reg_we)
begin
if rising_edge(reg_we) then
if reg_aen = '1' then
reg_addr_async <= reg_dio;
else
reg_data_async <= reg_dio;
end if;
end if;
end process;
proc_reg_da_sync:
process(adc_clk)
-- process(usb_usbclk)
begin
if rising_edge(adc_clk) then
-- if rising_edge(usb_usbclk) then
if rst = '1' then
reg_en_addr <= '0';
reg_en_data <= '0';
reg_addr_last <= '0';
reg_data_last <= '0';
elsif reg_we = '1' then
reg_en_addr <= reg_aen and not reg_addr_last;
reg_en_data <= not (reg_aen or reg_data_last);
reg_addr_last <= reg_aen;
reg_data_last <= not reg_aen;
else
reg_addr_last <= '0';
reg_data_last <= '0';
end if;
reg_data <= reg_data_async;
reg_addr <= reg_addr_async;
end if;
end process;
-- Registers
proc_register_write:
process(adc_clk)
-- process(usb_usbclk)
begin
if rising_edge(adc_clk) then
-- if rising_edge(usb_usbclk) then
if rst = '1' then
reg_lo_nco_rst <= '0';
reg_lo_nco_en <= '0';
elsif reg_en_data = '1' then
case reg_addr is
when X"00" => -- Control
reg_lo_nco_rst <= reg_data(0);
reg_lo_nco_en <= reg_data(1);
when X"10" => -- freqency
reg_lo_freq_in(7 downto 0) <= reg_data;
when X"11" => -- freqency
reg_lo_freq_in(15 downto 8) <= reg_data;
when X"12" => -- freqency
reg_lo_freq_in(23 downto 16) <= reg_data;
when X"13" => -- freqency
reg_lo_freq_in(31 downto 24) <= reg_data;
when X"20" => -- phase
reg_lo_phase_in(7 downto 0) <= reg_data;
when X"21" => -- phase
reg_lo_phase_in(15 downto 8) <= reg_data;
when X"22" => -- phase
reg_lo_phase_in(23 downto 16) <= reg_data;
when X"23" => -- phase
reg_lo_phase_in(31 downto 24) <= reg_data;
when others => null;
end case;
end if;
end if;
end process;
----------------------------------------------------------
-- DDC input
----------------------------------------------------------
proc_adc_input_register:
process(adc_clk)
begin
if rising_edge(adc_clk) then
ddc_din_vld <= enable;
if enable = '1' then
ddc_din_i <= sfixed(resize(adc_da, nbits_in));
end if;
end if;
end process;
ddc_din_q <= to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
enable <= '1';
adc_rand <= '0';
adc_pga <= '0';
adc_dith <= '0';
adc_shdn <= not enable;
----------------------------------------------------------
-- USB FIFO output
----------------------------------------------------------
proc_usb_interleave_iq:
process(adc_clk)
variable i, q : unsigned(31 downto 0);
begin
if rising_edge(adc_clk) then
if rst = '1' then
fifo_usb_we_pipe <= (others => '0');
elsif ddc_dout_vld = '1' then
fifo_usb_we_pipe <= (others => '1');
i := unsigned(ddc_dout_i);
q := unsigned(ddc_dout_q);
fifo_usb_in(0) <= i(15 downto 0);
fifo_usb_in(1) <= i(31 downto 16);
fifo_usb_in(2) <= q(15 downto 0);
fifo_usb_in(3) <= q(31 downto 16);
elsif fifo_usb_ff = '0' then
fifo_usb_we_pipe <= fifo_usb_we_pipe(fifo_usb_we_pipe'left-1 downto 0) & '0';
fifo_usb_in(0) <= fifo_usb_in(1);
fifo_usb_in(1) <= fifo_usb_in(2);
fifo_usb_in(2) <= fifo_usb_in(3);
end if;
end if;
end process;
inst_usbfifo: entity work.fifo_async
GENERIC MAP
(
addr_width => 7,
data_width => 16,
almost_full_thresh => 96,
almost_empty_thresh => 32
)
PORT MAP
(
rst => rst,
clk_w => adc_clk,
clk_r => usb_ifclk,
we => fifo_usb_we,
re => fifo_usb_re,
data_w => fifo_usb_in(0),
data_r => fifo_usb_out,
fifo_full => fifo_usb_ff,
fifo_empty => fifo_usb_ef,
fifo_afull => fifo_usb_aff,
fifo_aempty => fifo_usb_aef
);
fifo_usb_we <= fifo_usb_we_pipe(fifo_usb_we_pipe'left);
usb_fd <= signed(fifo_usb_out);
fifo_usb_re <= usb_flaga;
usb_slcs_n <= '0';
usb_slwr_n <= not usb_flaga;
usb_slrd_n <= '1';
usb_sloe <= '0';
----------------------------------------------------------
-- Channel-Link DDR output
----------------------------------------------------------
proc_cl_interleave_iq:
process(adc_clk)
variable i, q : unsigned(31 downto 0);
begin
if rising_edge(adc_clk) then
if rst = '1' then
cl_we_pipe <= (others => '0');
elsif ddc_dout_vld = '1' then
cl_we_pipe <= (others => '1');
i := unsigned(ddc_dout_i);
q := unsigned(ddc_dout_q);
cl_sd_data(0) <= i;
cl_sd_data(1) <= q;
else
cl_we_pipe <= cl_we_pipe(cl_we_pipe'left-1 downto 0) & '0';
cl_sd_data(0) <= cl_sd_data(1);
end if;
end if;
end process;
inst_cl_ddr_out: entity work.cl_ddr_out
PORT MAP
(
aclr => rst,
datain_h => cl_dout_H,
datain_l => cl_dout_L,
outclock => adc_clk,
outclocken => '1',
dataout => cl_dout_clk
);
cl_dout_H <= '0' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(31 downto 16));
cl_dout_L <= '1' & cl_we_pipe(cl_we_pipe'left) & "0000000" & std_logic_vector(cl_sd_data(0)(15 downto 0));
cl_dout <= unsigned(cl_dout_clk(23 downto 0));
cl_clk_out <= cl_dout_clk(24);
cl_pat_sel <= '0';
cl_prbs_en <= '0';
cl_ds_opt <= '0';
cl_bal <= '0';
cl_pd_n <= '1';
----------------------------------------------------------
END;
lib/radio/ddc/src/syn_ddc_var.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
use work.cordic_pkg.all;
ENTITY syn_ddc IS
Generic
(
nbits_in : integer := 18;
nbits_in_frac : integer := 16;
nbits_out : integer := 18;
nbits_out_frac : integer := 16;
lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20;
cic_nstages : integer := 3;
cic_max_ratio : integer := 1024;
cic_max_diff_delay : integer := 2;
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 24
);
PORT
(
rst : in std_logic;
clk : in std_logic;
lo_nco_rst : in std_logic;
lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in signed(nbits_in-1 downto 0);
din_q : in signed(nbits_in-1 downto 0);
dout_i : out signed(nbits_out-1 downto 0);
dout_q : out signed(nbits_out-1 downto 0);
din_vld : in std_logic;
dout_vld : out std_logic
);
END syn_ddc;
ARCHITECTURE behavior OF syn_ddc IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ddc
GENERIC
(
nbits_in : integer;
nbits_in_frac : integer;
nbits_out : integer;
nbits_out_frac : integer;
lo_nbits_phase : integer;
lo_nbits_freq : integer;
cic_nstages : integer;
cic_max_ratio : integer;
cic_max_diff_delay : integer;
cic_scale_nbits_min : integer;
cic_scale_nbits_max : integer
);
PORT
(
rst : in std_logic;
clk : in std_logic;
lo_nco_rst : in std_logic;
lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
dout_q : out sfixed;
din_vld : in std_logic;
dout_vld : out std_logic
);
END COMPONENT;
--Outputs
SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL ddc_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
BEGIN
-- Instantiate the Unit Under Test (UUT)
inst_ddc : ddc
GENERIC MAP
(
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac,
lo_nbits_phase => lo_nbits_phase,
lo_nbits_freq => lo_nbits_freq,
cic_nstages => cic_nstages,
cic_max_ratio => cic_max_ratio,
cic_max_diff_delay => cic_max_diff_delay,
cic_scale_nbits_min => cic_scale_nbits_min,
cic_scale_nbits_max => cic_scale_nbits_max
)
PORT MAP
(
rst => rst,
clk => clk,
lo_nco_rst => lo_nco_rst,
lo_nco_en => lo_nco_en,
lo_freq_in => lo_freq_in,
lo_phase_in => lo_phase_in,
cic_ratio => cic_ratio,
cic_diff_delay => cic_diff_delay,
cic_shift_in => cic_shift_in,
din_i => ddc_din_i,
din_q => ddc_din_q,
dout_i => ddc_dout_i,
dout_q => ddc_dout_q,
din_vld => din_vld,
dout_vld => dout_vld
);
ddc_din_i <= to_sfixed(din_i, ddc_din_i);
ddc_din_q <= to_sfixed(din_q, ddc_din_q);
dout_i <= signed(ddc_dout_i);
dout_q <= signed(ddc_dout_q);
END;
lib/radio/ddc/src/tb_ddc_var.vhd
+381
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
use work.cordic_pkg.all;
use work.PCK_FIO.all;
ENTITY tb_ddc IS
Generic
(
nbits_in : integer := 16;
nbits_in_frac : integer := 14;
nbits_out : integer := 18;
nbits_out_frac : integer := 16;
lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20;
cic_nstages : integer := 3;
cic_max_ratio : integer := 4096;
cic_max_diff_delay : integer := 1;
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 32;
rfgen_nbits_phase : integer := 20;
rfgen_nbits_freq : integer := 20
);
END tb_ddc;
ARCHITECTURE behavior OF tb_ddc IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ddc
GENERIC
(
nbits_in : integer;
nbits_in_frac : integer;
nbits_out : integer;
nbits_out_frac : integer;
lo_nbits_phase : integer;
lo_nbits_freq : integer;
cic_nstages : integer;
cic_max_ratio : integer;
cic_max_diff_delay : integer;
cic_scale_nbits_min : integer;
cic_scale_nbits_max : integer
);
PORT
(
rst : in std_logic;
clk : in std_logic;
lo_nco_rst : in std_logic;
lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
dout_q : out sfixed;
din_vld : in std_logic;
dout_vld : out std_logic
);
END COMPONENT;
-- Rf-Generator
COMPONENT mix
GENERIC
(
nbits_din : integer;
nbits_din_frac : integer;
nbits_dout : integer;
nbits_dout_frac : integer;
nbits_phase : integer;
nbits_freq : integer
);
PORT
(
rst : in std_logic;
clk : in std_logic;
nco_rst : in std_logic;
nco_en : in std_logic;
freq_in : in unsigned(nbits_freq-1 downto 0);
phase_in : in unsigned(nbits_phase-1 downto 0);
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
dout_q : out sfixed;
din_vld : in std_logic;
dout_vld : out std_logic
);
END COMPONENT;
--Constants
constant fa : REAL := 100.0E6;
constant frf1 : REAL := 29.9E6;
constant frf2 : REAL := 30.0E6;
constant frf3 : REAL := 30.1E6;
constant flo : REAL := 30.0E6;
constant PERIOD : time := 10 ns;
SIGNAL rfgen1_freq_word : integer := integer(frf1/fa*2.0**rfgen_nbits_freq);
SIGNAL rfgen2_freq_word : integer := integer(frf2/fa*2.0**rfgen_nbits_freq);
SIGNAL rfgen3_freq_word : integer := integer(frf3/fa*2.0**rfgen_nbits_freq);
SIGNAL lo_freq_word : integer := integer(flo/fa*2.0**lo_nbits_freq);
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '1';
SIGNAL ddc_nco_rst : std_logic := '0';
SIGNAL ddc_nco_en : std_logic := '0';
SIGNAL ddc_freq_in : unsigned(lo_nbits_freq-1 downto 0) := (others => '0');
SIGNAL ddc_phase_in : unsigned(lo_nbits_phase-1 downto 0) := (others => '0');
SIGNAL ddc_diff_delay : natural := 1;
SIGNAL ddc_ratio : natural := 64;
SIGNAL ddc_shift_in : natural := 18-cic_scale_nbits_min;
--Outputs
SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL ddc_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL ddc_dout_i : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL ddc_dout_q : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
SIGNAL ddc_dout_vld : std_logic;
SIGNAL ddc_din_vld : std_logic := '0';
SIGNAL rfgen_nco_rst : std_logic := '0';
SIGNAL rfgen_nco_en : std_logic := '0';
SIGNAL rfgen1_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
SIGNAL rfgen1_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
SIGNAL rfgen2_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
SIGNAL rfgen2_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
SIGNAL rfgen3_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
SIGNAL rfgen3_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
--Outputs
signal rfgen_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
signal rfgen_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(1.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
SIGNAL rfgen_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen1_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen1_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen1_dout_vld : std_logic;
SIGNAL rfgen2_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen2_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen2_dout_vld : std_logic;
SIGNAL rfgen3_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen3_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen3_dout_vld : std_logic;
SIGNAL fileout_enable : std_logic := '0';
-- Debug
signal ddc_i_out_f : real;
signal ddc_q_out_f : real;
signal rfgen_i_out_f : real;
signal rfgen_q_out_f : real;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : ddc
GENERIC MAP
(
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac,
lo_nbits_phase => lo_nbits_phase,
lo_nbits_freq => lo_nbits_freq,
cic_nstages => cic_nstages,
cic_max_ratio => cic_max_ratio,
cic_max_diff_delay => cic_max_diff_delay,
cic_scale_nbits_min => cic_scale_nbits_min,
cic_scale_nbits_max => cic_scale_nbits_max
)
PORT MAP
(
rst => rst,
clk => clk,
lo_nco_rst => ddc_nco_rst,
lo_nco_en => ddc_nco_en,
lo_freq_in => ddc_freq_in,
lo_phase_in => ddc_phase_in,
cic_ratio => ddc_ratio,
cic_diff_delay => ddc_diff_delay,
cic_shift_in => ddc_shift_in,
din_i => ddc_din_i,
din_q => ddc_din_q,
dout_i => ddc_dout_i,
dout_q => ddc_dout_q,
din_vld => ddc_din_vld,
dout_vld => ddc_dout_vld
);
rfgen1: mix
GENERIC MAP
(
nbits_din => nbits_in,
nbits_din_frac => nbits_in_frac,
nbits_dout => nbits_in,
nbits_dout_frac => nbits_in_frac,
nbits_phase => rfgen_nbits_phase,
nbits_freq => rfgen_nbits_freq
)
PORT MAP
(
rst => rst,
clk => clk,
nco_rst => rfgen_nco_rst,
nco_en => rfgen_nco_en,
freq_in => rfgen1_freq_in,
phase_in => rfgen1_phase_in,
din_i => rfgen_din_i,
din_q => rfgen_din_q,
dout_i => rfgen1_dout_i,
dout_q => rfgen1_dout_q,
din_vld => '1',
dout_vld => rfgen1_dout_vld
);
rfgen2: mix
GENERIC MAP
(
nbits_din => nbits_in,
nbits_din_frac => nbits_in_frac,
nbits_dout => nbits_in,
nbits_dout_frac => nbits_in_frac,
nbits_phase => rfgen_nbits_phase,
nbits_freq => rfgen_nbits_freq
)
PORT MAP
(
rst => rst,
clk => clk,
nco_rst => rfgen_nco_rst,
nco_en => rfgen_nco_en,
freq_in => rfgen2_freq_in,
phase_in => rfgen2_phase_in,
din_i => rfgen_din_i,
din_q => rfgen_din_q,
dout_i => rfgen2_dout_i,
dout_q => rfgen2_dout_q,
din_vld => '1',
dout_vld => rfgen2_dout_vld
);
rfgen3: mix
GENERIC MAP
(
nbits_din => nbits_in,
nbits_din_frac => nbits_in_frac,
nbits_dout => nbits_in,
nbits_dout_frac => nbits_in_frac,
nbits_phase => rfgen_nbits_phase,
nbits_freq => rfgen_nbits_freq
)
PORT MAP
(
rst => rst,
clk => clk,
nco_rst => rfgen_nco_rst,
nco_en => rfgen_nco_en,
freq_in => rfgen3_freq_in,
phase_in => rfgen3_phase_in,
din_i => rfgen_din_i,
din_q => rfgen_din_q,
dout_i => rfgen3_dout_i,
dout_q => rfgen3_dout_q,
din_vld => '1',
dout_vld => rfgen3_dout_vld
);
tb_clk : PROCESS
BEGIN
clk <= not clk;
wait for PERIOD/2;
END PROCESS;
rfgen_dout_i <= resize(0.333*rfgen1_dout_i + 0.333*rfgen2_dout_i + 0.333*rfgen3_dout_i, rfgen_dout_i);
rfgen_dout_q <= resize(0.333*rfgen1_dout_q + 0.333*rfgen2_dout_q + 0.333*rfgen3_dout_q, rfgen_dout_q);
ddc_din_i <= rfgen_dout_i;
ddc_din_q <= to_sfixed(0.0, ddc_din_q);
ddc_din_vld <= rfgen1_dout_vld and rfgen2_dout_vld and rfgen3_dout_vld;
ddc_i_out_f <= to_real(ddc_dout_i);
ddc_q_out_f <= to_real(ddc_dout_q);
rfgen_i_out_f <= to_real(rfgen_dout_i);
rfgen_q_out_f <= to_real(rfgen_dout_q);
tb : PROCESS
file RESULT_FREQ: text open write_mode is "freq.txt";
variable L: line;
BEGIN
-- Wait 100 ns for global reset to finish
wait for 4*PERIOD;
rst <= '0';
fprint(RESULT_FREQ, L,"%s\n", REAL'image(flo));
wait for 2*PERIOD;
-------------------------------------------
-- Program gains
wait for 2*PERIOD;
wait until rising_edge(clk);
-- start DDC
ddc_phase_in <= to_unsigned(0,lo_nbits_phase);
ddc_freq_in <= to_unsigned(lo_freq_word,lo_nbits_freq);
wait until rising_edge(clk);
ddc_nco_en <= '1';
wait for 20*PERIOD;
fileout_enable <= '1';
wait;
END PROCESS;
rfgen_ctrl : PROCESS
BEGIN
wait until rising_edge(clk) and rst = '0';
rfgen1_freq_in <= to_unsigned(rfgen1_freq_word,rfgen_nbits_freq);
rfgen1_phase_in <= to_unsigned(0,rfgen_nbits_phase);
rfgen2_freq_in <= to_unsigned(rfgen2_freq_word,rfgen_nbits_freq);
rfgen2_phase_in <= to_unsigned(0,rfgen_nbits_phase);
rfgen3_freq_in <= to_unsigned(rfgen3_freq_word,rfgen_nbits_freq);
rfgen3_phase_in <= to_unsigned(0,rfgen_nbits_phase);
wait until rising_edge(clk);
rfgen_nco_en <= '1';
wait;
END PROCESS;
tb_fo : PROCESS(clk)
file RESULT_Ii: text open write_mode is "i_in.txt";
file RESULT_Qi: text open write_mode is "q_in.txt";
file RESULT_Io: text open write_mode is "i_dec.txt";
file RESULT_Qo: text open write_mode is "q_dec.txt";
variable L: line;
BEGIN
if rising_edge(clk) and fileout_enable = '1' then
if ddc_din_vld = '1' then
fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_dout_i)));
fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_dout_q)));
end if;
if ddc_dout_vld = '1' then
fprint(RESULT_Io, L,"%s\n", REAL'image(to_real(ddc_dout_i)));
fprint(RESULT_Qo, L,"%s\n", REAL'image(to_real(ddc_dout_q)));
end if;
end if;
END PROCESS;
END;
lib/radio/ddc/src/tb_syn_ddc.vhd
+483
View File
@@ -0,0 +1,483 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:16:42 13.05.2007
-- Design Name: tb_nco
-- Module Name: tb_nco.vhd
-- Project Name: nco
-- Target Device:
-- Tool versions:
-- Description:
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use std.textio.all; -- Imports the standard textio package.
library ieee_proposed;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
library work;
use work.fixed_util_pkg.all;
use work.cordic_pkg.all;
--use work.PCK_FIO.all;
ENTITY tb_syn_ddc IS
Generic
(
nbits_in : integer := 16;
nbits_in_frac : integer := 14;
nbits_out : integer := 32;
nbits_out_frac : integer := 30;
lo_nbits_phase : integer := 24;
lo_nbits_freq : integer := 24;
cic_nstages : integer := 5;
cic_ratio : integer := 25;
cic_scale_nbits : integer := 22;
rfgen_nbits_phase : integer := 32;
rfgen_nbits_freq : integer := 32
);
END tb_syn_ddc;
ARCHITECTURE behavior OF tb_syn_ddc IS
--Constants
constant fa : REAL := 2.0**27;
constant frf1 : REAL := 33.99E6;
constant frf2 : REAL := 2.1E6;
constant frf3 : REAL := 19.01E6;
constant flo : REAL := 2.00E6;
constant PERIOD_ADCCLK : time := 10 ns;
constant PERIOD_USBCLK : time := 20 ns;
constant PERIOD_IFCLK : time := 20 ns;
SIGNAL rfgen1_freq_word : integer := integer(frf1/fa*2.0**rfgen_nbits_freq);
SIGNAL rfgen2_freq_word : integer := integer(frf2/fa*2.0**rfgen_nbits_freq);
SIGNAL rfgen3_freq_word : integer := integer(frf3/fa*2.0**rfgen_nbits_freq);
SIGNAL lo_freq_word : integer := integer(flo/fa*2.0**lo_nbits_freq);
SIGNAL ddc_freq_in : unsigned(lo_nbits_freq-1 downto 0) := (others => '0');
SIGNAL ddc_phase_in : unsigned(lo_nbits_phase-1 downto 0) := (others => '0');
--Inputs
SIGNAL rst : std_logic := '1';
SIGNAL adc_clk : std_logic := '0';
SIGNAL adc_ofa : std_logic := '0';
SIGNAL adc_rand : std_logic;
SIGNAL adc_pga : std_logic;
SIGNAL adc_dith : std_logic;
SIGNAL adc_shdn : std_logic;
SIGNAL adc_da : signed (15 downto 0);
SIGNAL adc_da_vld : std_logic;
SIGNAL usb_usbclk : std_logic := '0';
SIGNAL usb_ifclk : std_logic := '0';
SIGNAL usb_fd : signed (15 downto 0);
SIGNAL usb_fifoadr : unsigned (1 downto 0);
SIGNAL usb_pktend : std_logic;
SIGNAL usb_slcs_n : std_logic;
SIGNAL usb_slwr_n : std_logic;
SIGNAL usb_slrd_n : std_logic;
SIGNAL usb_sloe : std_logic;
SIGNAL usb_flaga : std_logic := '0';
SIGNAL usb_flagb : std_logic := '0';
SIGNAL usb_flagc : std_logic := '0';
SIGNAL cl_dout : unsigned (20 downto 0);
SIGNAL cl_clk_out : std_logic;
SIGNAL cl_pd_n : std_logic;
SIGNAL reg_dio : unsigned (7 downto 0) := (others => 'Z');
SIGNAL reg_aen : std_logic := '1';
SIGNAL reg_oe : std_logic := '0';
SIGNAL reg_we : std_logic := '0';
SIGNAL rfgen_nco_rst : std_logic := '0';
SIGNAL rfgen_nco_en : std_logic := '0';
SIGNAL rfgen1_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
SIGNAL rfgen1_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
SIGNAL rfgen2_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
SIGNAL rfgen2_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
SIGNAL rfgen3_freq_in : unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
SIGNAL rfgen3_phase_in : unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
--Outputs
signal rfgen_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
signal rfgen_din_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(1.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
SIGNAL rfgen_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen1_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen1_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen1_dout_vld : std_logic;
SIGNAL rfgen2_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen2_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen2_dout_vld : std_logic;
SIGNAL rfgen3_dout_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen3_dout_q : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
SIGNAL rfgen3_dout_vld : std_logic;
SIGNAL fileout_enable : std_logic := '0';
BEGIN
inst_syn_ddc : entity work.syn_ddc
GENERIC MAP
(
nbits_in => nbits_in,
nbits_in_frac => nbits_in_frac,
nbits_out => nbits_out,
nbits_out_frac => nbits_out_frac,
lo_nbits_phase => lo_nbits_phase,
lo_nbits_freq => lo_nbits_freq,
cic_nstages => cic_nstages,
cic_ratio => cic_ratio,
cic_scale_nbits => cic_scale_nbits
)
PORT MAP
(
rst => rst,
adc_clk => adc_clk,
adc_da => adc_da,
adc_ofa => adc_ofa,
adc_rand => adc_rand,
adc_pga => adc_pga,
adc_dith => adc_dith,
adc_shdn => adc_shdn,
usb_usbclk => usb_usbclk,
usb_ifclk => usb_ifclk,
usb_fd => usb_fd,
usb_pktend => usb_pktend,
usb_fifoadr => usb_fifoadr,
usb_slcs_n => usb_slcs_n,
usb_slwr_n => usb_slwr_n,
usb_slrd_n => usb_slrd_n,
usb_sloe => usb_sloe,
usb_flaga => usb_flaga,
usb_flagb => usb_flagb,
usb_flagc => usb_flagc,
cl_clk_out => cl_clk_out,
cl_dout => cl_dout,
cl_pd_n => cl_pd_n,
reg_aen => reg_aen,
reg_dio => reg_dio,
reg_oe => reg_oe,
reg_we => reg_we
);
rfgen1: entity work.mix
GENERIC MAP
(
nbits_din => nbits_in,
nbits_din_frac => nbits_in_frac,
nbits_dout => nbits_in,
nbits_dout_frac => nbits_in_frac,
nbits_phase => rfgen_nbits_phase,
nbits_freq => rfgen_nbits_freq
)
PORT MAP
(
rst => rst,
clk => adc_clk,
nco_rst => rfgen_nco_rst,
nco_en => rfgen_nco_en,
freq_in => rfgen1_freq_in,
phase_in => rfgen1_phase_in,
din_i => rfgen_din_i,
din_q => rfgen_din_q,
dout_i => rfgen1_dout_i,
dout_q => rfgen1_dout_q,
din_vld => '1',
dout_vld => rfgen1_dout_vld
);
rfgen2: entity work.mix
GENERIC MAP
(
nbits_din => nbits_in,
nbits_din_frac => nbits_in_frac,
nbits_dout => nbits_in,
nbits_dout_frac => nbits_in_frac,
nbits_phase => rfgen_nbits_phase,
nbits_freq => rfgen_nbits_freq
)
PORT MAP
(
rst => rst,
clk => adc_clk,
nco_rst => rfgen_nco_rst,
nco_en => rfgen_nco_en,
freq_in => rfgen2_freq_in,
phase_in => rfgen2_phase_in,
din_i => rfgen_din_i,
din_q => rfgen_din_q,
dout_i => rfgen2_dout_i,
dout_q => rfgen2_dout_q,
din_vld => '1',
dout_vld => rfgen2_dout_vld
);
rfgen3: entity work.mix
GENERIC MAP
(
nbits_din => nbits_in,
nbits_din_frac => nbits_in_frac,
nbits_dout => nbits_in,
nbits_dout_frac => nbits_in_frac,
nbits_phase => rfgen_nbits_phase,
nbits_freq => rfgen_nbits_freq
)
PORT MAP
(
rst => rst,
clk => adc_clk,
nco_rst => rfgen_nco_rst,
nco_en => rfgen_nco_en,
freq_in => rfgen3_freq_in,
phase_in => rfgen3_phase_in,
din_i => rfgen_din_i,
din_q => rfgen_din_q,
dout_i => rfgen3_dout_i,
dout_q => rfgen3_dout_q,
din_vld => '1',
dout_vld => rfgen3_dout_vld
);
tb_adcclk : PROCESS
BEGIN
adc_clk <= not adc_clk;
wait for PERIOD_ADCCLK/2;
END PROCESS;
tb_usbclk : PROCESS
BEGIN
usb_usbclk <= not usb_usbclk;
wait for PERIOD_USBCLK/2;
END PROCESS;
tb_ifclk : PROCESS
BEGIN
usb_ifclk <= not usb_ifclk;
wait for PERIOD_IFCLK/2;
END PROCESS;
rfgen_dout_i <= resize(0.333*rfgen1_dout_i + 0.333*rfgen2_dout_i + 0.333*rfgen3_dout_i, rfgen_dout_i);
rfgen_dout_q <= resize(0.333*rfgen1_dout_q + 0.333*rfgen2_dout_q + 0.333*rfgen3_dout_q, rfgen_dout_q);
adc_da <= to_signed(rfgen_dout_i);
adc_da_vld <= rfgen1_dout_vld and rfgen2_dout_vld and rfgen3_dout_vld;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 400*PERIOD_USBCLK;
rst <= '0';
wait for 200*PERIOD_USBCLK;
-------------------------------------------
-- Program gains
wait for 2*PERIOD_USBCLK;
ddc_phase_in <= to_unsigned(0,lo_nbits_phase);
ddc_freq_in <= to_unsigned(lo_freq_word,lo_nbits_freq);
wait until rising_edge(usb_usbclk);
reg_dio <= X"10";
reg_aen <= '1';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= ddc_freq_in(7 downto 0);
reg_aen <= '0';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= X"11";
reg_aen <= '1';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= ddc_freq_in(15 downto 8);
reg_aen <= '0';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= X"12";
reg_aen <= '1';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= ddc_freq_in(23 downto 16);
reg_aen <= '0';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= X"13";
reg_aen <= '1';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= X"00";
reg_aen <= '0';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= X"20";
reg_aen <= '1';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= ddc_phase_in(7 downto 0);
reg_aen <= '0';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= X"21";
reg_aen <= '1';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= ddc_phase_in(15 downto 8);
reg_aen <= '0';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= X"22";
reg_aen <= '1';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= ddc_phase_in(23 downto 16);
reg_aen <= '0';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= X"23";
reg_aen <= '1';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= X"00";
reg_aen <= '0';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait for 200*PERIOD_USBCLK;
fileout_enable <= '1';
wait until rising_edge(usb_usbclk);
reg_dio <= X"00";
reg_aen <= '1';
reg_we <= '1';
wait until rising_edge(usb_usbclk);
reg_aen <= '0';
reg_we <= '0';
wait until rising_edge(usb_usbclk);
reg_dio <= X"02";
reg_aen <= '0';
reg_we <= '1';
wait;
END PROCESS;
rfgen_ctrl : PROCESS
BEGIN
wait until rising_edge(adc_clk) and rst = '0';
rfgen1_freq_in <= to_unsigned(rfgen1_freq_word,rfgen_nbits_freq);
rfgen1_phase_in <= to_unsigned(0,rfgen_nbits_phase);
rfgen2_freq_in <= to_unsigned(rfgen2_freq_word,rfgen_nbits_freq);
rfgen2_phase_in <= to_unsigned(0,rfgen_nbits_phase);
rfgen3_freq_in <= to_unsigned(rfgen3_freq_word,rfgen_nbits_freq);
rfgen3_phase_in <= to_unsigned(0,rfgen_nbits_phase);
wait until rising_edge(adc_clk);
rfgen_nco_en <= '1';
wait;
END PROCESS;
END;