jens d3e486b6d5 Reworked exception FSM: ...

- Pipeline is now flushed and finished and all dependencies are solved before entering exception handler
  - User mode writes on status register are now correctly finished before status is altered by exception
  - Processor stalls for 2 cycles after RFE to ensure that status register is correct in user mode
- Added int-port


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git-svn-id: http://moon:8086/svn/vhdl/trunk@426 cc03376c-175c-47c8-b038-4cd826a8556b

2009-04-11 08:34:50 +00:00

..

JCpu

- removed interrupt polarity capabilty

2009-02-28 13:17:32 +00:00

MIPS

Reworked exception FSM:

2009-04-11 08:34:50 +00:00