jens d3e486b6d5 Reworked exception FSM: ...

- Pipeline is now flushed and finished and all dependencies are solved before entering exception handler
  - User mode writes on status register are now correctly finished before status is altered by exception
  - Processor stalls for 2 cycles after RFE to ensure that status register is correct in user mode
- Added int-port


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git-svn-id: http://moon:8086/svn/vhdl/trunk@426 cc03376c-175c-47c8-b038-4cd826a8556b

2009-04-11 08:34:50 +00:00

..

ac97_ctrl

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

CPUs

Reworked exception FSM:

2009-04-11 08:34:50 +00:00

FIFO

- renamed

2009-01-30 21:22:25 +00:00

filter

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

fix_std

Initial import

2008-08-23 08:20:30 +00:00

fixed

deleted

2009-01-11 15:31:42 +00:00

fixed_ja

Initial import

2008-08-23 08:20:30 +00:00

jasm

Initial import

2008-08-23 08:20:30 +00:00

misc

- added timer inrterrupt

2009-03-27 11:16:54 +00:00

PCK_FIO-1.16

Initial import

2008-08-23 08:20:30 +00:00

PCK_FIO-2002.7

Initial import

2008-08-23 08:20:30 +00:00

radio

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

SDRAM

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

SSRAM

- Using MODELSIM_HOME environment variable

2008-10-23 21:21:24 +00:00

uart

Intital revision

2008-10-10 21:31:24 +00:00

VGA_ctrl

- vga_frontend* used wrong raster coords (y was swapped) - fixed

2009-02-13 08:51:41 +00:00