jens
2edaa4d7cb
git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
314 lines
12 KiB
VHDL
314 lines
12 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY tb IS
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END tb;
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ARCHITECTURE test OF tb IS
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COMPONENT mt48lc16m8a2
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GENERIC (
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tCK : TIME := 10 ns;
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addr_bits : INTEGER := 12;
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data_bits : INTEGER := 8
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);
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PORT (
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Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
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Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
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Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00";
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Clk : IN STD_LOGIC := '0';
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Cke : IN STD_LOGIC := '0';
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Cs_n : IN STD_LOGIC := '1';
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Cas_n : IN STD_LOGIC := '0';
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Ras_n : IN STD_LOGIC := '0';
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We_n : IN STD_LOGIC := '0';
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Dqm : IN STD_LOGIC := '0'
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);
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END COMPONENT;
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FOR ALL : mt48lc16m8a2 USE ENTITY work.mt48lc16m8a2 (behave);
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CONSTANT tCK : TIME := 10 ns;
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CONSTANT addr_bits : INTEGER := 12;
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CONSTANT data_bits : INTEGER := 8;
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SIGNAL pDq : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
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SIGNAL pAddr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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SIGNAL pBa : STD_LOGIC_VECTOR (1 DOWNTO 0);
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SIGNAL pClk : STD_LOGIC;
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SIGNAL pCke : STD_LOGIC;
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SIGNAL pCs_n : STD_LOGIC;
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SIGNAL pCas_n : STD_LOGIC;
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SIGNAL pRas_n : STD_LOGIC;
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SIGNAL pWe_n : STD_LOGIC;
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SIGNAL pDqm : STD_LOGIC;
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SIGNAL stim_done : boolean := false;
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SIGNAL clk_done : boolean := false;
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BEGIN
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u1: mt48lc16m8a2
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PORT MAP(
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Dq => pDq,
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Addr => pAddr,
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Ba => pBa,
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Clk => pClk,
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Cke => pCke,
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Cs_n => pCs_n,
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Ras_n => pRas_n,
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Cas_n => pCas_n,
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We_n => pWe_n,
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Dqm => pDqm
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);
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stimulator : PROCESS
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PROCEDURE ACTIVE (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
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Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
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BEGIN
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pCke <= '1';
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pCs_n <= '0';
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pRas_n <= '0';
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pCas_n <= '1';
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pWe_n <= '1';
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pDqm <= '0';
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pBa <= Ba_in;
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pAddr <= Addr_in;
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pDq <= Dq_in;
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WAIT FOR tCK;
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END;
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PROCEDURE AUTO_REFRESH IS
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BEGIN
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pCke <= '1';
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pCs_n <= '0';
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pRas_n <= '0';
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pCas_n <= '0';
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pWe_n <= '1';
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pDqm <= '0';
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--pBa <= "00";
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--pAddr <= (OTHERS => '0');
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pDq <= (OTHERS => 'Z');
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WAIT FOR tCK;
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END;
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PROCEDURE BURST_TERM IS
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BEGIN
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pCke <= '1';
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pCs_n <= '0';
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pRas_n <= '1';
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pCas_n <= '1';
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pWe_n <= '0';
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pDqm <= '0';
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--pBa <= "00";
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--pAddr <= (OTHERS => '0');
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pDq <= (OTHERS => 'Z');
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WAIT FOR tCK;
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END;
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PROCEDURE LOAD_MODE_REG (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
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Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0)) IS
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BEGIN
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pCke <= '1';
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pCs_n <= '0';
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pRas_n <= '0';
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pCas_n <= '0';
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pWe_n <= '0';
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pDqm <= '0';
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pBa <= Ba_in;
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pAddr <= Addr_in;
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pDq <= (OTHERS => 'Z');
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WAIT FOR tCK;
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END;
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PROCEDURE NOP (Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
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BEGIN
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pCke <= '1';
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pCs_n <= '0';
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pRas_n <= '1';
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pCas_n <= '1';
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pWe_n <= '1';
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pDqm <= '0';
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--pBa <= "00";
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--pAddr <= (OTHERS => '0');
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pDq <= Dq_in;
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WAIT FOR tCK;
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END;
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PROCEDURE PRECHARGE (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
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Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
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BEGIN
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pCke <= '1';
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pCs_n <= '0';
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pRas_n <= '0';
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pCas_n <= '1';
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pWe_n <= '0';
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pDqm <= '0';
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pBa <= Ba_in;
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pAddr <= Addr_in;
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pDq <= Dq_in;
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WAIT FOR tCK;
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END;
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PROCEDURE READ (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
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Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
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BEGIN
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pCke <= '1';
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pCs_n <= '0';
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pRas_n <= '1';
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pCas_n <= '0';
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pWe_n <= '1';
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pDqm <= '0';
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pBa <= Ba_in;
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pAddr <= Addr_in;
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pDq <= Dq_in;
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WAIT FOR tCK;
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END;
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-- Write
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PROCEDURE WRITE (Ba_in : STD_LOGIC_VECTOR (1 DOWNTO 0);
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Addr_in : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
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Dq_in : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
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BEGIN
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pCke <= '1';
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pCs_n <= '0';
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pRas_n <= '1';
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pCas_n <= '0';
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pWe_n <= '0';
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pDqm <= '0';
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pBa <= Ba_in;
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pAddr <= Addr_in;
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pDq <= Dq_in;
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WAIT FOR tCK;
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END;
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BEGIN
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-- COMMAND BA ADDR DQ
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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-- We need 100 us power up sequence. I use 10 NOPs here as a required example.
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PRECHARGE ("00", "010000000000", "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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AUTO_REFRESH;
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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AUTO_REFRESH;
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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LOAD_MODE_REG ("00", "000000100010");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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ACTIVE ("00", "000000000000", "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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ACTIVE ("01", "000000000000", "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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ACTIVE ("10", "000000000000", "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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ACTIVE ("11", "000000000000", "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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WRITE ("00", "000000000000", "00000000");
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NOP ( "00000001");
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NOP ( "00000010");
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NOP ( "00000011");
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WRITE ("01", "000000000000", "00000100");
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NOP ( "00000101");
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NOP ( "00000110");
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NOP ( "00000111");
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WRITE ("10", "000000000000", "00001000");
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NOP ( "00001001");
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NOP ( "00001010");
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NOP ( "00001011");
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WRITE ("11", "000000000000", "00001100");
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NOP ( "00001101");
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NOP ( "00001110");
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NOP ( "00001111");
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READ ("00", "000000000000", "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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READ ("01", "000000000000", "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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READ ("10", "000000000000", "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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READ ("11", "000000000000", "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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NOP ( "ZZZZZZZZ");
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ASSERT false
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REPORT "End of Stimulation Detected!"
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SEVERITY note;
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stim_done <= true;
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WAIT;
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END PROCESS;
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clock : PROCESS
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VARIABLE done_time : time;
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BEGIN
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pclk <= '0';
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WAIT for tCK/2;
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WHILE not stim_done loop
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pclk <= '1';
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WAIT for tCK/2;
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pclk <= '0';
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WAIT for tCK/2;
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END LOOP;
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done_time := now + tCK;
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WHILE now < done_time LOOP -- one last clock to finish last command
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pclk <= '1';
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WAIT for tCK/2;
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pclk <= '0';
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WAIT for tCK/2;
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END LOOP;
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ASSERT false
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REPORT "Suspending clock activity"
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SEVERITY note;
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clk_done <= true;
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WAIT;
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END PROCESS;
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END test;
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