jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
107 lines
2.2 KiB
VHDL
107 lines
2.2 KiB
VHDL
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13:42:54 10/08/2005
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-- Design Name: eval_synch_top
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-- Module Name: tb_eval_synch.vhd
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-- Project Name: eval_sync
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: eval_synch_top
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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ENTITY tb_eval_synch_vhd IS
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END tb_eval_synch_vhd;
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ARCHITECTURE behavior OF tb_eval_synch_vhd IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT eval_synch_top
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PORT(
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rst : IN std_logic;
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clk : IN std_logic;
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din : IN std_logic;
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dout : OUT std_logic_vector(0 to 7)
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);
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END COMPONENT;
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--Constants
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constant PERIOD : time := 10 ns;
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--Inputs
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SIGNAL rst : std_logic := '1';
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SIGNAL clk : std_logic := '0';
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SIGNAL din : std_logic := '0';
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--Outputs
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SIGNAL dout : std_logic_vector(0 to 7);
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: eval_synch_top PORT MAP(
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rst => rst,
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clk => clk,
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din => din,
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dout => dout
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);
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tb_clk : PROCESS
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BEGIN
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clk <= not clk;
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wait for PERIOD/2;
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END PROCESS;
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tb : PROCESS
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BEGIN
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-- Wait 100 ns for global reset to finish
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wait for 2*PERIOD;
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rst <= '0';
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wait for 1.0*PERIOD + 0 ns;
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din <= '1';
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wait for PERIOD;
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din <= '0';
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wait for PERIOD;
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din <= '1';
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wait for PERIOD;
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din <= '1';
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wait for PERIOD;
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din <= '0';
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-- Wait 100 ns for global reset to finish
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wait for 100 ns;
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-- Place stimulus here
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wait; -- will wait forever
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END PROCESS;
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END;
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