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-- Company: 
-- Engineer:
--
-- Create Date:   13:42:54 10/08/2005
-- Design Name:   eval_synch_top
-- Module Name:   tb_eval_synch.vhd
-- Project Name:  eval_sync
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: eval_synch_top
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_eval_synch_vhd IS
END tb_eval_synch_vhd;

ARCHITECTURE behavior OF tb_eval_synch_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT eval_synch_top
	PORT(
		rst : IN std_logic;
		clk : IN std_logic;
		din : IN std_logic;          
		dout : OUT std_logic_vector(0 to 7)
		);
	END COMPONENT;

	--Constants
	constant PERIOD : time := 10 ns;

	--Inputs
	SIGNAL rst :  std_logic := '1';
	SIGNAL clk :  std_logic := '0';
	SIGNAL din :  std_logic := '0';

	--Outputs
	SIGNAL dout :  std_logic_vector(0 to 7);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: eval_synch_top PORT MAP(
		rst => rst,
		clk => clk,
		din => din,
		dout => dout
	);

 	tb_clk : PROCESS
	BEGIN
		clk <= not clk;
		wait for PERIOD/2;
	END PROCESS;

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 2*PERIOD;
		rst <= '0';

		wait for 1.0*PERIOD + 0 ns;
		din <= '1';

		wait for PERIOD;
		din <= '0';

		wait for PERIOD;
		din <= '1';

		wait for PERIOD;
		din <= '1';

		wait for PERIOD;
		din <= '0';

		-- Wait 100 ns for global reset to finish
		wait for 100 ns;

		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;