jens
35c1a4e010
- derive sys_clk from PLL git-svn-id: http://moon:8086/svn/vhdl/trunk@1384 cc03376c-175c-47c8-b038-4cd826a8556b
111 lines
3.4 KiB
Tcl
111 lines
3.4 KiB
Tcl
## Generated SDC file "JMips.out.sdc"
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## Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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## Your use of Altera Corporation's design tools, logic functions
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## and other software and tools, and its AMPP partner logic
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## functions, and any output files from any of the foregoing
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## (including device programming or simulation files), and any
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## associated documentation or information are expressly subject
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## to the terms and conditions of the Altera Program License
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## Subscription Agreement, the Altera Quartus II License Agreement,
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## the Altera MegaCore Function License Agreement, or other
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## applicable license agreement, including, without limitation,
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## that your use is for the sole purpose of programming logic
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## devices manufactured by Altera and sold by Altera or its
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## authorized distributors. Please refer to the applicable
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## agreement for further details.
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## VENDOR "Altera"
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## PROGRAM "Quartus II"
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## VERSION "Version 15.0.0 Build 145 04/22/2015 SJ Web Edition"
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## DATE "Sat May 30 18:14:14 2015"
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##
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## DEVICE "EP4CE22F17C6"
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##
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {sys_clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports { clk_brd }]
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create_clock -name {SDRAM_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {sys_sdram_clk}]
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create_clock -name {spi_clk} -period 15.000 -waveform { 0.000 7.500 } [get_ports {spi_clk}]
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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derive_pll_clocks
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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