jens c1e96aecba - fixed rst ...

- use main_sim for test bench

git-svn-id: http://moon:8086/svn/vhdl/trunk@1576 cc03376c-175c-47c8-b038-4cd826a8556b

2021-03-29 14:14:22 +00:00

Common

- removed old wave select

2021-03-28 17:38:25 +00:00

lib

- fixed opc.list not found

2021-03-29 13:37:02 +00:00

make

- refactored ISE makefiles

2021-03-29 12:49:42 +00:00

projects

- fixed rst

2021-03-29 14:14:22 +00:00

Makefile

- refactored ISE makefiles

2021-03-29 12:49:42 +00:00

S

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23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%