jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
118 lines
2.8 KiB
VHDL
118 lines
2.8 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:07:37 11/13/05
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-- Design Name:
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-- Module Name: hpi_reg_top - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity hpi_reg_top is
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Port ( sys_rst_n : in std_logic;
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sys_clk : in std_logic;
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sys_hpi_a : in std_logic_vector(1 downto 0);
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sys_hpi_d : inout std_logic_vector(15 downto 0);
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sys_hpi_rd_n : in std_logic;
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sys_hpi_wr_n : in std_logic;
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sys_hpi_cs_n : in std_logic;
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sys_hpi_rst_n : in std_logic;
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sys_hpi_int : in std_logic;
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sys_led : out std_logic_vector(3 downto 0);
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sys_sace_mpce_n : out std_logic);
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end hpi_reg_top;
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architecture Behavioral of hpi_reg_top is
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COMPONENT oneshot
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Generic ( mode : integer range 0 to 2);
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PORT(
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rst : IN std_logic;
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clk : IN std_logic;
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input : IN std_logic;
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output : OUT std_logic
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);
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END COMPONENT;
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signal reg : std_logic_vector(15 downto 0);
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signal wr_n : std_logic;
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begin
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sys_sace_mpce_n <= '1';
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sys_led(0) <= sys_hpi_cs_n;
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sys_led(1) <= sys_hpi_rd_n;
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sys_led(2) <= sys_hpi_wr_n;
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sys_led(3) <= sys_hpi_int;
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Inst_oneshot_wr: oneshot
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GENERIC MAP (mode => 1)
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PORT MAP(
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rst => sys_rst_n,
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clk => sys_clk,
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input => sys_hpi_wr_n,
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output => wr_n
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);
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reg_in: process(sys_clk, sys_hpi_rst_n, wr_n, sys_hpi_cs_n, sys_hpi_a, sys_hpi_d)
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begin
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if (sys_hpi_rst_n = '0') then
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reg <= (others => '0');
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else
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if (sys_hpi_cs_n = '0') then
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if (wr_n = '0' and rising_edge(sys_clk)) then
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case (sys_hpi_a) is
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when "00" =>
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reg <= sys_hpi_d;
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when others => null;
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end case;
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end if;
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end if;
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end if;
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end process;
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reg_out: process(sys_hpi_rst_n, sys_hpi_rd_n, sys_hpi_cs_n, sys_hpi_a, reg)
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begin
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if (sys_hpi_rst_n = '0') then
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sys_hpi_d <= (others => 'Z');
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else
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if (sys_hpi_cs_n = '0' and sys_hpi_rd_n = '0') then
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case (sys_hpi_a) is
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when "00" =>
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sys_hpi_d <= reg;
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when "01" =>
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sys_hpi_d <= X"AAAA";
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when "10" =>
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sys_hpi_d <= X"5555";
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when "11" =>
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sys_hpi_d <= X"1234";
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when others => null;
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end case;
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else
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sys_hpi_d <= (others => 'Z');
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end if;
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end if;
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end process;
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end Behavioral;
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