jens
5af1242330
git-svn-id: http://moon:8086/svn/vhdl/trunk@1415 cc03376c-175c-47c8-b038-4cd826a8556b
108 lines
3.1 KiB
VHDL
108 lines
3.1 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:52:30 10/02/05
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-- Design Name:
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-- Module Name: cordic_top - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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use work.fixed_ja.all;
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use std.textio.all; -- Imports the standard textio package.
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use work.PCK_FIO.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity mac_top is
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Generic
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(
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nbits_in : integer := 8;
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nbits_in_int : integer := 2;
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nbits_out : integer := 8;
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nbits_out_int : integer := 2
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);
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Port (
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rst : in std_logic;
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clk : in std_logic;
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ce : in std_logic;
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xin : in sfixed_t;
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yin : in sfixed_t;
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dout : out sfixed_t;
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ready : out std_logic;
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valid_din : in std_logic;
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valid_dout : out std_logic
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);
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end mac_top;
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architecture Behavioral of mac_top is
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signal xin_r, yin_r : sfixed_t(sproto(nbits_in, nbits_in_int)'range);
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signal mul_xy : sfixed_t(sproto(xin, '*', yin)'range);
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signal accu : sfixed_t(sproto(mul_xy, '+', mul_xy)'range);
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signal res : sfixed_t(sproto(nbits_out, nbits_out_int)'range);
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begin
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mac_pipelined: process (rst, clk, ce, valid_din, xin, yin)
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variable valid_dout_pipe : unsigned(2 downto 0);
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file RESULT : text open write_mode is "STD_OUTPUT";
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variable L: line;
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begin
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if rst = '1' then
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dout <= (sproto(nbits_out, nbits_out_int)'range => '0');
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ready <= '0';
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valid_dout <= '0';
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accu <= to_sfixed(0, accu);
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res <= to_sfixed(0, res);
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mul_xy <= to_sfixed(0, mul_xy);
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valid_dout_pipe := (others => '0');
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elsif rising_edge(clk) then
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valid_dout <= valid_dout_pipe(valid_dout_pipe'length-1);
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valid_dout_pipe := valid_dout_pipe(valid_dout_pipe'length-2 downto 0) & valid_din;
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xin_r <= to_sfixed(0, xin_r);
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yin_r <= to_sfixed(0, yin_r);
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-- Assign dout
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if ce = '1' then
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fprint(RESULT, L,"-----------------------------------------\n");
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fprint(RESULT, L,"time = %s\n", time'image(now));
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fprint(RESULT, L,"0: xin = %s, yin = %s\n", REAL'image(to_real(xin)), REAL'image(to_real(yin)));
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fprint(RESULT, L,"1: xin_r = %s, yin_r = %s\n", REAL'image(to_real(xin_r)), REAL'image(to_real(yin_r)));
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fprint(RESULT, L,"2: mul_xy = %s\n", REAL'image(to_real(mul_xy)));
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fprint(RESULT, L,"3: accu = %s\n", REAL'image(to_real(accu)));
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fprint(RESULT, L,"4: res = %s\n\n", REAL'image(to_real(res)));
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dout <= res;
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res <= to_sfixed(accu, res, none, saturate);
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accu <= to_sfixed(accu + mul_xy, accu);
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mul_xy <= xin_r * yin_r;
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if valid_din = '1' then
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xin_r <= xin;
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yin_r <= yin;
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end if;
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end if;
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end if;
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end process;
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--------------------------------------------------------------------
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end Behavioral;
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