--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:    11:52:30 10/02/05
-- Design Name:    
-- Module Name:    cordic_top - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_ja.all;
use std.textio.all; --  Imports the standard textio package.
use work.PCK_FIO.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mac_top is
Generic
(
	nbits_in		: integer := 8;
	nbits_in_int	: integer := 2;
	nbits_out		: integer := 8;
	nbits_out_int	: integer := 2
);
Port (
	rst			: in std_logic;
	clk			: in std_logic;
	ce			: in std_logic;
	xin			: in sfixed_t;
	yin			: in sfixed_t;
	dout		: out sfixed_t;
	ready		: out std_logic;
	valid_din	: in std_logic;
	valid_dout	: out std_logic
);
end mac_top;

architecture Behavioral of mac_top is

signal xin_r, yin_r : sfixed_t(sproto(nbits_in, nbits_in_int)'range);
signal mul_xy : sfixed_t(sproto(xin, '*', yin)'range);
signal accu : sfixed_t(sproto(mul_xy, '+', mul_xy)'range);
signal res : sfixed_t(sproto(nbits_out, nbits_out_int)'range);

begin

mac_pipelined: process (rst, clk, ce, valid_din, xin, yin)
variable valid_dout_pipe : unsigned(2 downto 0);

file RESULT : text open write_mode is "STD_OUTPUT"; 
variable L:         line;
begin
	if rst = '1' then
		dout <= (sproto(nbits_out, nbits_out_int)'range => '0');
		ready <= '0';
		valid_dout <= '0';
		accu <= to_sfixed(0, accu);
		res <= to_sfixed(0, res);
		mul_xy <= to_sfixed(0, mul_xy);
		valid_dout_pipe := (others => '0');
	elsif rising_edge(clk) then
	

		valid_dout <= valid_dout_pipe(valid_dout_pipe'length-1);
		valid_dout_pipe := valid_dout_pipe(valid_dout_pipe'length-2 downto 0) & valid_din;
		xin_r <= to_sfixed(0, xin_r);
		yin_r <= to_sfixed(0, yin_r);
		
		-- Assign dout
		if ce = '1' then
			fprint(RESULT, L,"-----------------------------------------\n");
			fprint(RESULT, L,"time   = %s\n", time'image(now));
			fprint(RESULT, L,"0: xin    = %s, yin    = %s\n", REAL'image(to_real(xin)), REAL'image(to_real(yin)));
			fprint(RESULT, L,"1: xin_r  = %s, yin_r  = %s\n", REAL'image(to_real(xin_r)), REAL'image(to_real(yin_r)));
			fprint(RESULT, L,"2: mul_xy = %s\n", REAL'image(to_real(mul_xy)));
			fprint(RESULT, L,"3: accu   = %s\n", REAL'image(to_real(accu)));
			fprint(RESULT, L,"4: res    = %s\n\n", REAL'image(to_real(res)));
			dout <= res;
			res <= to_sfixed(accu, res, none, saturate);
			accu <= to_sfixed(accu + mul_xy, accu);
			mul_xy <= xin_r * yin_r;
			if valid_din = '1' then
				xin_r <= xin;
				yin_r <= yin;
			end if;	
		end if;	

	end if;
end process;

--------------------------------------------------------------------
end Behavioral;