- added mac

git-svn-id: http://moon:8086/svn/vhdl/trunk@1415 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 10:51:05 +00:00
parent ea60299d26
commit 5af1242330
3 changed files with 391 additions and 0 deletions
@@ -0,0 +1,74 @@
+# -------------------------------------------------
+# Global options
+# -------------------------------------------------
+LANG_STD := 93c
+IEEE_STD := standard
+WORK_PATH := work
+SOURCE_PATH := src
+LIB_PATH := ../lib
+
+# -------------------------------------------------
+# Target options
+# -------------------------------------------------
+TARGET := tb_mac_top
+
+SOURCES :=	src/mac_top.vhd \
+			src/tb_mac_top.vhd 
+			
+
+# -------------------------------------------------
+GHDL_SRC := /usr/local/lib/gcc/i686-pc-linux-gnu/4.1.1/vhdl/src
+GHDL_OPT := --workdir=$(WORK_PATH) --std=$(LANG_STD) --ieee=$(IEEE_STD)
+
+# -------------------------------------------------
+	
+all: elaborate
+
+.PHONY : skel
+skel : 
+	@mkdir -p ./$(WORK_PATH)
+
+.PHONY: xref
+xref: 
+	ghdl --xref-html $(LIB_PATH)/*.vhd $(SOURCES)
+
+.PHONY: syntax
+syntax: skel xref
+	ghdl -s $(GHDL_OPT) $(SOURCES)
+
+.PHONY: import
+import: skel xref
+	ghdl -i $(GHDL_OPT) $(LIB_PATH)/*.vhd
+
+.PHONY: analyze
+analyze: skel import
+	ghdl -a $(GHDL_OPT) $(LIB_PATH)/*.vhd $(SOURCES)
+
+.PHONY: anaborate
+anaborate: skel import
+	ghdl -c $(GHDL_OPT) $(LIB_PATH)/*.vhd $(SOURCES) -e $(TARGET)
+
+.PHONY: makeunit
+makeunit: skel import
+	ghdl -m $(GHDL_OPT) $(TARGET)
+
+.PHONY: elaborate
+elaborate: skel analyze
+	ghdl -e $(GHDL_OPT) $(TARGET)
+
+.PHONY: run
+run: skel elaborate
+	ghdl -r $(GHDL_OPT) $(TARGET) --vcd=$(TARGET).vcd --assert-level=error 
+
+.PHONY: show
+show:  $(TARGET).vcd 
+	@gtkwave $(TARGET).vcd $(TARGET).sav 2>/dev/null
+
+# -------------------------------------------------
+.PHONY: clean
+clean:
+	rm -rf $(TARGET)
+	rm -rf ./html
+	cd $(WORK_PATH); rm -rf *.o *.cf
+	
+# -------------------------------------------------
@@ -0,0 +1,107 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    11:52:30 10/02/05
+-- Design Name:    
+-- Module Name:    cordic_top - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use work.fixed_ja.all;
+use std.textio.all; --  Imports the standard textio package.
+use work.PCK_FIO.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+entity mac_top is
+Generic
+(
+	nbits_in		: integer := 8;
+	nbits_in_int	: integer := 2;
+	nbits_out		: integer := 8;
+	nbits_out_int	: integer := 2
+);
+Port (
+	rst			: in std_logic;
+	clk			: in std_logic;
+	ce			: in std_logic;
+	xin			: in sfixed_t;
+	yin			: in sfixed_t;
+	dout		: out sfixed_t;
+	ready		: out std_logic;
+	valid_din	: in std_logic;
+	valid_dout	: out std_logic
+);
+end mac_top;
+
+architecture Behavioral of mac_top is
+
+signal xin_r, yin_r : sfixed_t(sproto(nbits_in, nbits_in_int)'range);
+signal mul_xy : sfixed_t(sproto(xin, '*', yin)'range);
+signal accu : sfixed_t(sproto(mul_xy, '+', mul_xy)'range);
+signal res : sfixed_t(sproto(nbits_out, nbits_out_int)'range);
+
+begin
+
+mac_pipelined: process (rst, clk, ce, valid_din, xin, yin)
+variable valid_dout_pipe : unsigned(2 downto 0);
+
+file RESULT : text open write_mode is "STD_OUTPUT"; 
+variable L:         line;
+begin
+	if rst = '1' then
+		dout <= (sproto(nbits_out, nbits_out_int)'range => '0');
+		ready <= '0';
+		valid_dout <= '0';
+		accu <= to_sfixed(0, accu);
+		res <= to_sfixed(0, res);
+		mul_xy <= to_sfixed(0, mul_xy);
+		valid_dout_pipe := (others => '0');
+	elsif rising_edge(clk) then
+	
+
+		valid_dout <= valid_dout_pipe(valid_dout_pipe'length-1);
+		valid_dout_pipe := valid_dout_pipe(valid_dout_pipe'length-2 downto 0) & valid_din;
+		xin_r <= to_sfixed(0, xin_r);
+		yin_r <= to_sfixed(0, yin_r);
+		
+		-- Assign dout
+		if ce = '1' then
+			fprint(RESULT, L,"-----------------------------------------\n");
+			fprint(RESULT, L,"time   = %s\n", time'image(now));
+			fprint(RESULT, L,"0: xin    = %s, yin    = %s\n", REAL'image(to_real(xin)), REAL'image(to_real(yin)));
+			fprint(RESULT, L,"1: xin_r  = %s, yin_r  = %s\n", REAL'image(to_real(xin_r)), REAL'image(to_real(yin_r)));
+			fprint(RESULT, L,"2: mul_xy = %s\n", REAL'image(to_real(mul_xy)));
+			fprint(RESULT, L,"3: accu   = %s\n", REAL'image(to_real(accu)));
+			fprint(RESULT, L,"4: res    = %s\n\n", REAL'image(to_real(res)));
+			dout <= res;
+			res <= to_sfixed(accu, res, none, saturate);
+			accu <= to_sfixed(accu + mul_xy, accu);
+			mul_xy <= xin_r * yin_r;
+			if valid_din = '1' then
+				xin_r <= xin;
+				yin_r <= yin;
+			end if;	
+		end if;	
+
+	end if;
+end process;
+
+--------------------------------------------------------------------
+end Behavioral;
@@ -0,0 +1,210 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 10/02/2005
+-- Design Name:   mac_top
+-- Module Name:   tb_mac_top.vhd
+-- Project Name:  mac
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: cordic_top
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.fixed_ja.all;
+use work.PCK_FIO.all;
+
+ENTITY tb_mac_top IS
+	Generic (
+	        nbits_in		: integer := 8;
+	        nbits_in_int	: integer := 1;
+	        nbits_out		: integer := 16;
+	        nbits_out_int	: integer := 1
+	        );
+END tb_mac_top;
+
+ARCHITECTURE behavior OF tb_mac_top IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT mac_top
+	GENERIC (
+		nbits_in		: integer;
+		nbits_in_int	: integer;
+		nbits_out		: integer;
+		nbits_out_int	: integer
+		);
+	PORT(
+		rst			: in std_logic;
+		clk			: in std_logic;
+		ce			: in std_logic;
+		xin			: in sfixed_t;
+		yin			: in sfixed_t;
+		dout		: out sfixed_t;
+		ready		: out std_logic;
+		valid_din	: in std_logic;
+		valid_dout	: out std_logic
+	);
+	END COMPONENT;
+
+	--Constants
+	constant PERIOD : time := 10 ns;
+
+	--Inputs
+	SIGNAL clk			: std_logic := '0';
+	SIGNAL rst			: std_logic := '1';
+	SIGNAL ce			: std_logic := '0';
+	SIGNAL valid_din	: std_logic := '0';
+	SIGNAL xin, yin		: sfixed_t(sproto(nbits_in, nbits_in_int)'range) := to_sfixed(0, nbits_in, nbits_in_int);
+
+	--Outputs
+	SIGNAL dout			: sfixed_t(sproto(nbits_out, nbits_out_int)'range);
+	SIGNAL valid_dout, ready : std_logic;
+	
+
+		
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: mac_top 
+	GENERIC MAP (
+		nbits_in		=> nbits_in,
+		nbits_in_int	=> nbits_in_int,
+		nbits_out		=> nbits_out,
+		nbits_out_int	=> nbits_out_int
+		)
+	PORT MAP(
+		clk  => clk,
+		rst  => rst,
+		ce   => ce,
+		xin  => xin,
+		yin  => yin,
+		dout => dout,
+		ready => ready,
+		valid_din => valid_din,
+		valid_dout => valid_dout
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+	tb : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 1*PERIOD;
+		rst <= '0';
+
+		wait for 1*PERIOD;
+		
+		wait until rising_edge(clk);
+		ce <= '0';
+		valid_din <= '0';
+		xin <= (others => '-');
+		yin <= (others => '-');
+
+		wait until rising_edge(clk);
+		ce <= '1';
+		valid_din <= '1';
+		xin <= to_sfixed(0.5, nbits_in, nbits_in_int);
+		yin <= to_sfixed(0.5, nbits_in, nbits_in_int);
+		
+		wait until rising_edge(clk);
+		ce <= '1';
+		valid_din <= '1';
+		xin <= to_sfixed(-0.25, nbits_in, nbits_in_int);
+		yin <= to_sfixed(0.25, nbits_in, nbits_in_int);
+
+		wait until rising_edge(clk);
+		ce <= '1';
+		valid_din <= '1';
+		xin <= to_sfixed(0.125, nbits_in, nbits_in_int);
+		yin <= to_sfixed(-0.125, nbits_in, nbits_in_int);
+		
+		wait until rising_edge(clk);
+		ce <= '1';
+		valid_din <= '1';
+		xin <= to_sfixed(1.0, nbits_in, nbits_in_int);
+		yin <= to_sfixed(0.5, nbits_in, nbits_in_int);
+		
+		wait until rising_edge(clk);
+		ce <= '1';
+		valid_din <= '1';
+		xin <= to_sfixed(0.333, nbits_in, nbits_in_int);
+		yin <= to_sfixed(0.75, nbits_in, nbits_in_int);
+
+		wait until rising_edge(clk);
+		ce <= '1';
+		valid_din <= '1';
+		xin <= to_sfixed(0.7071, nbits_in, nbits_in_int);
+		yin <= to_sfixed(-0.7071, nbits_in, nbits_in_int);
+
+		wait until rising_edge(clk);
+		ce <= '1';
+		valid_din <= '0';
+		xin <= (others => '-');
+		yin <= (others => '-');
+
+		wait for 2*PERIOD;
+
+		wait until rising_edge(clk);
+		ce <= '0';
+		valid_din <= '0';
+		xin <= (others => '-');
+		yin <= (others => '-');
+
+		wait until rising_edge(clk);
+		ce <= '1';
+		valid_din <= '1';
+		xin <= to_sfixed(0.9, nbits_in, nbits_in_int);
+		yin <= to_sfixed(0.333, nbits_in, nbits_in_int);
+
+		wait until rising_edge(clk);
+		ce <= '1';
+		valid_din <= '0';
+		xin <= (others => '-');
+		yin <= (others => '-');
+
+		wait for 2*PERIOD;
+
+		wait until rising_edge(clk);
+		ce <= '1';
+		valid_din <= '0';
+		xin <= (others => '-');
+		yin <= (others => '-');
+
+		wait until rising_edge(clk);
+		ce <= '0';
+		valid_din <= '0';
+		xin <= (others => '-');
+		yin <= (others => '-');
+		
+		wait for 20*PERIOD;
+		assert false report "Test finished" severity error;
+		wait; 
+	END PROCESS;
+
+END;