jens
ea60299d26
git-svn-id: http://moon:8086/svn/vhdl/trunk@1414 cc03376c-175c-47c8-b038-4cd826a8556b
19 lines
592 B
Plaintext
19 lines
592 B
Plaintext
## NOTE: Do not edit this file.
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## Auto generated by Project Navigator for Post-Translate Simulation
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##
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vlib work
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## Compile Post-Translate Model
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vcom -explicit -93 "../../../lib/CPUs/JCpu/src/core/cpu_pkg.vhd"
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vcom -explicit -93 "../src/systest/ddr_sdr_conf_pkg.vhd"
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vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_2/src/mt46v16m16.vhd"
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vcom -93 "../ise91/systest/netgen/translate/systest_translate.vhd"
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vcom -93 "../src/systest/tb_systest.vhd"
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vsim -t 1ps -lib work tb_systest
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#do {tb_systest.wdo}
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view wave
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add wave *
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view structure
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view signals
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run 5us
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## End
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