-------------------------------------------------------------------------
-- Project: FIFO, generic FIFOs written in VHDL
-- Release 1
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
-----------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

entity fifo_async is
	Generic 
	(
		addr_width					: natural := 3;
		data_width					: natural := 8;
		almost_full_thresh			: integer := 6;
		almost_empty_thresh			: integer := 2;
		allow_full_writes			: boolean := false;
		allow_empty_reads			: boolean := false;
		do_last_read_update			: boolean := true;
		add_extra_read_register		: boolean := false
	);
	Port
	(
		rst			: in  STD_LOGIC;
		clk_w		: in  STD_LOGIC;
		clk_r		: in  STD_LOGIC;
		we			: in  STD_LOGIC;
		re			: in  STD_LOGIC;
		fifo_full	: out STD_LOGIC;
		fifo_empty	: out STD_LOGIC;
		fifo_afull	: out STD_LOGIC;
		fifo_aempty	: out STD_LOGIC;
		data_w		: in  unsigned (data_width-1 downto 0);
		data_r		: out unsigned (data_width-1 downto 0)
	);
end fifo_async;

architecture Behavioral of fifo_async is
	
	signal reg_we		: STD_LOGIC;
	signal reg_vld		: STD_LOGIC;
	signal reg_full		: STD_LOGIC;
	signal fifo_dout	: unsigned (data_width-1 downto 0);
	signal fifo_rd		: STD_LOGIC;
	signal fifo_empty_s	: STD_LOGIC;
	
begin

gen_extra_regs:
if add_extra_read_register generate

	inst_reg_stage: entity work.reg_stage
	GENERIC MAP
	(
		data_width	=> data_width
	)
	PORT MAP
	(
		rst			=>	rst,
		clk			=>	clk_r,
		we			=>	reg_we,
		re			=>	re,
		din			=>	fifo_dout,
		dout		=>	data_r,
		full		=>	reg_full,
		vld_dout	=>	reg_vld
	);

	fifo_rd			<= not reg_full;
	fifo_empty		<= not reg_vld;
	reg_we			<= not fifo_empty_s;
end generate;

	inst_fifo_async_stage: entity work.fifo_async_stage
	GENERIC MAP
	(
		data_width					=> data_width,
		addr_width					=> addr_width,
		almost_full_thresh			=> almost_full_thresh,
		almost_empty_thresh			=> almost_empty_thresh,
		allow_full_writes			=> allow_full_writes,
		allow_empty_reads			=> allow_empty_reads,
		do_last_read_update			=> do_last_read_update
	)
	PORT MAP
	(
		rst			=>	rst,
		clk_w		=>	clk_w,
		clk_r		=>	clk_r,
		we			=>	we,
		re			=>	fifo_rd,
		data_w		=>	data_w,
		data_r		=>	fifo_dout,
		fifo_full	=>	fifo_full,
		fifo_empty	=>	fifo_empty_s,
		fifo_afull	=>	fifo_afull,
		fifo_aempty	=>	fifo_aempty

	);

gen_no_extra_regs:
if not add_extra_read_register generate

	fifo_rd			<= re;
	fifo_empty		<= fifo_empty_s;
	data_r			<= fifo_dout;
end generate;

end Behavioral;