jens 8af5e1a8a5 - added extra register for bus master fifos ...

git-svn-id: http://moon:8086/svn/vhdl/trunk@1615 cc03376c-175c-47c8-b038-4cd826a8556b

2021-03-31 12:07:35 +00:00

Common

- removed old wave select

2021-03-28 17:38:25 +00:00

lib

- added extra register for bus master fifos

2021-03-31 12:07:35 +00:00

make

- remove unrelated path

2021-03-30 15:42:52 +00:00

projects

- fixed synth project after fifo refactoring

2021-03-31 09:55:49 +00:00

Makefile

- refactored ISE makefiles

2021-03-29 12:49:42 +00:00

S

Description

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23 MiB

Languages

VHDL 90.1%

Verilog 4.2%

Tcl 2.5%

SystemVerilog 0.8%

IGOR Pro 0.5%

Other 1.5%