jens
deb2fdbb90
git-svn-id: http://moon:8086/svn/vhdl/trunk@1323 cc03376c-175c-47c8-b038-4cd826a8556b
174 lines
8.4 KiB
Plaintext
174 lines
8.4 KiB
Plaintext
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This is the "ieee_proposed" library. This is a compatability library,
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which is designed to provide all of the functionality of the VHDL-200X-FT
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packages in VHDL-93. The "_c" after the package name is used to denote
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that this is a 1993 compliant version of this package. Otherwise, the
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name of the file and the name of the package are the same.
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Please compile the following files into a library named "ieee_proposed":
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standard_additions_c.vhdl
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env_c.vhdl
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standard_textio_additions_c.vhdl
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std_logic_1164_additions.vhdl
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numeric_std_additions.vhdl
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numeric_std_unsigned_c.vhdl
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fixed_pkg_c.vhdl
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float_pkg_c.vhdl
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New/Updated functions
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A) standard_additions -- Additions to the package "std.standard"
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Use model:
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use ieee_proposed.standard_additions.all;
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Dependancies: None.
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Notes: The functions "rising_edge" and "falling_edge" are defined in
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this package. If you use "numeric_bit" they are ALSO defined in that
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package, causing a conflict. The VHDL-200X-FT version of numeric_bit
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has these functions commented out, as well as the "sll", "srl", "ror"
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and "rol" functions which are implicit.
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New types defined in this package:
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REAL_VECTOR
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TIME_VECTOR
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INTEGER_VECTOR
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BOOLEAN_VECTOR
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New constants defined in this package:
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SIM_RESOLUTION : TIME - returns the simulator's resolution (1 ns default)
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1) "maximum" and "minimum" are defined for all default datatypes
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2) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
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These functions reduce a bit_vector to a single bit. Example:
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or_reduce ("0101") = '1'. In VHDL-2006 syntax these will be "or".
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3) "vector" and "bit" operations are defined. These will perform a
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boolean operation of a vector. Example:
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"1" xor "1010" = "0101";
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5) /??/ function is defined for "bit" ("??" operator is release)
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if (/??/('1')) then -- will return a "true".
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6) rising_edge and falling_edge functions are defined (see Notes).
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7) to_string function - Converts any of the base types into a string.
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Example:
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assert (bv = "101") report "result was " & to_string(bv) severity note;
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8) to_hstring and to_ostring function (bit_vector to hex or octal string)
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B) standard_textio_additions - Additions to the package "std.textio"
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Use model:
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use ieee_proposed.standard_textio_additions.all;
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Dependencies: std.textio, ieee_proposed.standard_additions
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1) tee - Echos the string to BOTH the file and the screen
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2) SREAD and SWRITE - String read and write routines (so you no longer
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need to do write (L, string'("ABCEDFG"));
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3) HREAD and HWRITE (Hex read and write) for bit_vector
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4) OREAD and OWRITE (octal read and write) for bit_vector
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5) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
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bit_vector
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6) justify - Justify a string left or right with a width. Example:
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justify ("ABCD", left, 6); will result in "ABCD "
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C) std_logic_1164_additions - Additions to the package "ieee.std_logic_1164"
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Usage model:
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use ieee.std_logic_1164.all;
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-- use ieee.std_logic_textio.all; -- Comment out, included in "_additions".
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use ieee_proposed.std_logic_1164_additions.all;
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Dependencies: ieee.std_logic_1164
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Note: The contents of the "std_logic_textio" package have now been
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included in the "std_logic_1164" package, and an EMPTY "std_logic_textio"
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package is provided in the new release.
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1) Short had aliases:
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a) to_bv - calls "to_BitVector"
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b) to_slv - calls "to_StdLogicVector"
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c) to_sulv - calls "to_stdULogicVector"
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2) Long hand aliases:
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a) to_bit_vector - calls "to_BitVector"
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b) to_std_logic_vector - calls "to_StdLogicVector"
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c) to_std_ulogic_vector - calls "to_StdULogicVector"
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3) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
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These functions reduce a std_logic_vector (or ulogic) to a single bit.
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In vhdl-2006 these will be unary "or", example "or "11011" = '1'"
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4) "vector" and "std_ulogic" operations are defined. These will perform a
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boolean operation of a vector. Example:
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"1" xor "1010" = "0101";
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5) "std_ulogic" and "boolean" operations are defined. Thus:
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if '1' and true then -- returns a "true".
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6) "\??\" function is defined for "std_ulogic" ("??" operator is release)
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if (bool('1')) then -- will return a "true".
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7) READ and WRITE procedures for "std_logic_vector", "std_ulogic_vector"
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and "std_ulogic" are defined.
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8) HREAD and HWRITE (Hex read and write) for std_logic_vector
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and std_ulogic_vector. These are more "forgiving" than the ones
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originally from "std_logic_textio"
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9) OREAD and OWRITE (octal read and write) for std_logic_vector
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and std_ulogic_vector. These are more "forgiving" than the ones
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originally from "std_logic_textio"
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10) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
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std_logic_vector and std_ulogic_vector.
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11) to_string function - Converts a "std_ulogic", "std_logic_vector" or
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"std_ulogic_vector" types into a string.
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Example:
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assert (slv = "101") report "result was " & to_string(slv) severity note;
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12) to_hstring and to_ostring function (std_(u)logic_vector to hex or octal
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string)
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D) numeric_std_additions - additions the the package "ieee.numeric_std"
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Usage Model:
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee_proposed.numeric_std_additions.all;
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Dependencies: ieee.std_logic_1164, ieee.numeric_std
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1) SIGNED or UNSIGNED + std_ulogic operators
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2) SIGNED or UNSIGNED - std_ulogic operators
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3) type UNRESOLVED_UNSIGNED (aliased to U_UNSIGNED) is an unresolved
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verion of UNSIGNED. It is aliased to "UNSIGNED" for compatability.
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4) type UNRESOLVED_SIGNED (aliased to U_SIGNED) is an unresolved
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verion of SIGNED. It is aliased to "SIGNED" for compatability.
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5) \?=\, \?/=\ - similar to "std_match", but return std_ulogic values.
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\?<\, \?<=\, \?>\, \?>=\ - compare functions which retrun std_ulogic.
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(these will be "?="... operators in the release)
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7) To_X01, To_X01Z, To_U01X, Is_X - same as std_logic_1164 functions,
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but overloaded for SIGNED and UNSIGNED.
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8) "sla" and "sra" - Mathmetically correct versions of these functions.
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9) minimum and maximum - smaller or larger of two SIGNED or UNSIGNED values.
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10) find_rightmost and find_leftmost - finds the first bit in a string.
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Example:
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find_leftmost (c12, '1'); -- returns the Log2 of "c12".
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returns -1 if not found.
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11) _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
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These functions reduce a SIGNED or an UNSIGNED to a single bit.
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(will overload the "or" and "and", ... operators in the release)
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12) SIGNED or UNSIGNED and "std_ulogic" operations are defined.
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These will perform a boolean operation of a vector. Example:
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"1" xor "1010" = "0101";
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13) READ and WRITE procedures for "SIGNED", and "UNSIGNED" are defined.
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14) HREAD and HWRITE (Hex read and write) for SIGNED and UNSIGNED.
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These are more "forgiving" than the ones
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originally from "std_logic_textio"
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15) OREAD and OWRITE (octal read and write) for "SIGNED" and "UNSIGNED.
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These are more "forgiving" than the ones
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originally from "std_logic_textio"
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16) BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
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SIGNED and UNSIGNED.
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17) to_string function - Converts a "SIGNED" or "UNSIGNED" types into a
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string. Example:
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assert (UNS = "101") report "result was " & to_string(UNS) severity note;
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18) to_hstring and to_ostring function (SIGNED or UNSIGNED to hex or octal
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string)
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E) numeric_std_unsigned - Simular to the "std_logic_unsigned" packages, but
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with all of the functionality of the "numeric_std" package.
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use model:
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use ieee.std_logic_1164.all;
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use ieee_proposed.numeric_std_unsigned.all;
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dependencies: ieee.numeric_std, ieee_proposed.numeric_std_additions
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F) For fixed point package:
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use model:
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee_proposed.fixed_float_types.all;
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use ieee_proposed.fixed_pkg.all;
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See fixed point package documentation
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http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Fixed_ug.pdf
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G) For floating point package:
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use model:
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee_proposed.fixed_float_types.all;
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use ieee_proposed.fixed_pkg.all;
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use ieee_proposed.float_pkg.all;
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See floating point package documentation
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http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/Float_ug.pdf
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