jens dabea0e2ab - fixed write latency, which shall be zero ...

git-svn-id: http://moon:8086/svn/vhdl/trunk@1266 cc03376c-175c-47c8-b038-4cd826a8556b

2015-05-30 13:59:21 +00:00

..

tb_ctrl_ddr_wb32.fdo

- removed constants from sdram_types.vhd and put them to sdram_const.vhd

2015-05-25 07:25:49 +00:00

tb_ctrl_ddr_wb32.wdo

- update wave

2015-05-24 18:27:52 +00:00

tb_ctrl_ddr_wb64.fdo

- removed constants from sdram_types.vhd and put them to sdram_const.vhd

2015-05-25 07:25:49 +00:00

tb_ctrl_ddr_wb64.wdo

- simplified PHY control signals

2015-05-30 08:31:08 +00:00

tb_ctrl_sdr_wb32_de0nano.fdo

- adde SIPO and PISO

2015-05-30 12:27:20 +00:00

tb_ctrl_sdr_wb32_de0nano.wdo

- fixed write latency, which shall be zero

2015-05-30 13:59:21 +00:00

tb_ctrl_sdr_wb32.fdo

[SDRAM CMD FSM]

2015-05-25 09:32:10 +00:00

tb_ctrl_sdr_wb32.wdo

- added Altera/De0-NAno implementation

2015-05-29 13:15:30 +00:00