jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
72 lines
2.6 KiB
VHDL
72 lines
2.6 KiB
VHDL
--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: controller.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:19:52 $
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--
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--------------------------------------------------------------------------
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--
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-- Entity declaration for DLX control section.
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--
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use work.dlx_types.all,
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work.dlx_instr.all,
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work.alu_types.all,
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work.mem_types.all;
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entity controller is
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generic (Tpd_clk_ctrl, Tpd_clk_const : Time;
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debug : boolean := false;
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tag : string := "";
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origin_x, origin_y : real := 0.0);
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port (phi1, phi2 : in bit;
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reset : in bit;
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halt : out bit;
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width : out mem_width;
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write_enable : out bit;
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mem_enable : out bit;
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ifetch : out bit;
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ready : in bit;
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alu_latch_en : out bit;
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alu_function : out alu_func;
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alu_zero, alu_negative, alu_overflow : in bit;
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reg_s1_addr, reg_s2_addr, reg_dest_addr : out dlx_reg_addr;
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reg_write : out bit;
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c_latch_en : out bit;
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a_latch_en, a_out_en : out bit;
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b_latch_en, b_out_en : out bit;
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temp_latch_en, temp_out_en1, temp_out_en2 : out bit;
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iar_latch_en, iar_out_en1, iar_out_en2 : out bit;
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pc_latch_en, pc_out_en1, pc_out_en2 : out bit;
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mar_latch_en, mar_out_en1, mar_out_en2 : out bit;
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mem_addr_mux_sel : out bit;
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mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out bit;
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mdr_mux_sel : out bit;
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ir_latch_en : out bit;
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ir_immed_sel1, ir_immed_sel2 : out immed_size;
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ir_immed_unsigned1, ir_immed_unsigned2 : out bit;
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ir_immed_en1, ir_immed_en2 : out bit;
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current_instruction : in dlx_word;
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const1, const2 : out dlx_word_bus bus);
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end controller;
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