jens
d61b3c2e0c
git-svn-id: http://moon:8086/svn/vhdl/trunk@1416 cc03376c-175c-47c8-b038-4cd826a8556b
353 lines
12 KiB
VHDL
353 lines
12 KiB
VHDL
--
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-- KCPSM3 reference design - Real Time Clock with UART communications
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--
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-- Ken Chapman - Xilinx Ltd - October 2003
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--
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-- The design demonstrates the following:-
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-- Connection of KCPSM3 to Program ROM
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-- Connection of UART macros supplied with PicoBlaze with
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-- Baud rate generation
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-- Definition of input and output ports with
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-- Minimum decoding
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-- Pipelining where appropriate
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-- Interrupt circuit with
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-- Simple fixed period timer
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-- Automatic clearing using interrupt acknowledge from KCPSM3
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--
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-- The design is set up for a 55MHz system clock and UART communications rate of 38400 baud.
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-- Please read design documentation to modify to your own requirements.
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--
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------------------------------------------------------------------------------------
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--
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-- NOTICE:
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--
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-- Copyright Xilinx, Inc. 2003. This code may be contain portions patented by other
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-- third parties. By providing this core as one possible implementation of a standard,
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-- Xilinx is making no representation that the provided implementation of this standard
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-- is free from any claims of infringement by any third party. Xilinx expressly
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-- disclaims any warranty with respect to the adequacy of the implementation, including
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-- but not limited to any warranty or representation that the implementation is free
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-- from claims of any third party. Furthermore, Xilinx is providing this core as a
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-- courtesy to you and suggests that you contact all third parties to obtain the
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-- necessary rights to use this implementation.
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--
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------------------------------------------------------------------------------------
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--
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-- Library declarations
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--
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-- Standard IEEE libraries
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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------------------------------------------------------------------------------------
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--
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--
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entity uart_clock is
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Port ( tx : out std_logic;
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rx : in std_logic;
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alarm : out std_logic;
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clk : in std_logic);
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end uart_clock;
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--
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------------------------------------------------------------------------------------
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--
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-- Start of test architecture
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--
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architecture Behavioral of uart_clock is
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--
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------------------------------------------------------------------------------------
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--
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-- declaration of KCPSM3
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--
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component kcpsm3
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Port ( address : out std_logic_vector(9 downto 0);
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instruction : in std_logic_vector(17 downto 0);
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port_id : out std_logic_vector(7 downto 0);
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write_strobe : out std_logic;
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out_port : out std_logic_vector(7 downto 0);
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read_strobe : out std_logic;
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in_port : in std_logic_vector(7 downto 0);
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interrupt : in std_logic;
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interrupt_ack : out std_logic;
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reset : in std_logic;
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clk : in std_logic);
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end component;
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--
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-- declaration of program ROM
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--
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component uclock
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Port ( address : in std_logic_vector(9 downto 0);
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instruction : out std_logic_vector(17 downto 0);
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clk : in std_logic);
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end component;
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--
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-- declaration of UART transmitter with integral 16 byte FIFO buffer
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--
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component uart_tx
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Port ( data_in : in std_logic_vector(7 downto 0);
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write_buffer : in std_logic;
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reset_buffer : in std_logic;
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en_16_x_baud : in std_logic;
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serial_out : out std_logic;
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buffer_full : out std_logic;
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buffer_half_full : out std_logic;
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clk : in std_logic);
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end component;
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--
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-- declaration of UART Receiver with integral 16 byte FIFO buffer
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--
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component uart_rx
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Port ( serial_in : in std_logic;
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data_out : out std_logic_vector(7 downto 0);
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read_buffer : in std_logic;
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reset_buffer : in std_logic;
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en_16_x_baud : in std_logic;
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buffer_data_present : out std_logic;
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buffer_full : out std_logic;
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buffer_half_full : out std_logic;
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clk : in std_logic);
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end component;
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--
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------------------------------------------------------------------------------------
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--
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-- Signals used to connect KCPSM3 to program ROM and I/O logic
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--
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signal address : std_logic_vector(9 downto 0);
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signal instruction : std_logic_vector(17 downto 0);
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signal port_id : std_logic_vector(7 downto 0);
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signal out_port : std_logic_vector(7 downto 0);
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signal in_port : std_logic_vector(7 downto 0);
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signal write_strobe : std_logic;
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signal read_strobe : std_logic;
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signal interrupt : std_logic;
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signal interrupt_ack : std_logic;
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--
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-- Signals for connection of peripherals
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--
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signal uart_status_port : std_logic_vector(7 downto 0);
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--
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-- Signals to form an timer generating an interrupt every microsecond
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--
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signal timer_count : integer range 0 to 63 :=0;
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signal timer_pulse : std_logic;
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--
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-- Signals for UART connections
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--
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signal baud_count : integer range 0 to 255 :=0;
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signal en_16_x_baud : std_logic;
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signal write_to_uart : std_logic;
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signal tx_full : std_logic;
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signal tx_half_full : std_logic;
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signal read_from_uart : std_logic;
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signal rx_data : std_logic_vector(7 downto 0);
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signal rx_data_present : std_logic;
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signal rx_full : std_logic;
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signal rx_half_full : std_logic;
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--
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------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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--
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-- Start of circuit description
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--
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begin
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--
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----------------------------------------------------------------------------------------------------------------------------------
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-- KCPSM3 and the program memory
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----------------------------------------------------------------------------------------------------------------------------------
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--
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processor: kcpsm3
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port map( address => address,
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instruction => instruction,
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port_id => port_id,
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write_strobe => write_strobe,
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out_port => out_port,
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read_strobe => read_strobe,
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in_port => in_port,
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interrupt => interrupt,
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interrupt_ack => interrupt_ack,
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reset => '0',
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clk => clk);
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program_rom: uclock
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port map( address => address,
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instruction => instruction,
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clk => clk);
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--
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----------------------------------------------------------------------------------------------------------------------------------
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-- Interrupt
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----------------------------------------------------------------------------------------------------------------------------------
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--
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--
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-- Interrupt is a generated once every 55 clock cycles to provide a 1us reference.
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-- Interrupt is automatically cleared by interrupt acknowledgment from KCPSM3.
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--
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Timer: process(clk)
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begin
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if clk'event and clk='1' then
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if timer_count=54 then
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timer_count <= 0;
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timer_pulse <= '1';
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else
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timer_count <= timer_count + 1;
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timer_pulse <= '0';
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end if;
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if interrupt_ack = '1' then
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interrupt <= '0';
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elsif timer_pulse = '1' then
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interrupt <= '1';
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else
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interrupt <= interrupt;
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end if;
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end if;
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end process Timer;
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--
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----------------------------------------------------------------------------------------------------------------------------------
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-- KCPSM3 input ports
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----------------------------------------------------------------------------------------------------------------------------------
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--
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--
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-- UART FIFO status signals to form a bus
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--
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uart_status_port <= "000" & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
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--
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-- The inputs connect via a pipelined multiplexer
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--
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input_ports: process(clk)
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begin
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if clk'event and clk='1' then
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case port_id(0) is
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-- read UART status at address 00 hex
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when '0' => in_port <= uart_status_port;
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-- read UART receive data at address 01 hex
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when '1' => in_port <= rx_data;
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-- Don't care used for all other addresses to ensure minimum logic implementation
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when others => in_port <= "XXXXXXXX";
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end case;
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-- Form read strobe for UART receiver FIFO buffer.
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-- The fact that the read strobe will occur after the actual data is read by
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-- the KCPSM3 is acceptable because it is really means 'I have read you'!
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read_from_uart <= read_strobe and port_id(0);
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end if;
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end process input_ports;
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--
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----------------------------------------------------------------------------------------------------------------------------------
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-- KCPSM3 output ports
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----------------------------------------------------------------------------------------------------------------------------------
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--
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-- adding the output registers to the clock processor
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output_ports: process(clk)
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begin
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if clk'event and clk='1' then
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if write_strobe='1' then
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-- Alarm register at address 00 hex with data bit0 providing control
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if port_id(0)='0' then
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alarm <= out_port(0);
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end if;
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end if;
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end if;
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end process output_ports;
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--
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-- write to UART transmitter FIFO buffer at address 01 hex.
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-- This is a combinatorial decode because the FIFO is the 'port register'.
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--
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write_to_uart <= write_strobe and port_id(0);
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--
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----------------------------------------------------------------------------------------------------------------------------------
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-- UART
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----------------------------------------------------------------------------------------------------------------------------------
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--
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-- Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
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-- Each contains an embedded 16-byte FIFO buffer.
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--
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transmit: uart_tx
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port map ( data_in => out_port,
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write_buffer => write_to_uart,
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reset_buffer => '0',
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en_16_x_baud => en_16_x_baud,
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serial_out => tx,
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buffer_full => tx_full,
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buffer_half_full => tx_half_full,
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clk => clk );
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receive: uart_rx
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port map ( serial_in => rx,
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data_out => rx_data,
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read_buffer => read_from_uart,
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reset_buffer => '0',
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en_16_x_baud => en_16_x_baud,
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buffer_data_present => rx_data_present,
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buffer_full => rx_full,
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buffer_half_full => rx_half_full,
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clk => clk );
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--
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-- Set baud rate to 38400 for the UART communications
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-- Requires en_16_x_baud to be 614400Hz which is a single cycle pulse every 163 cycles at 100MHz
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--
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-- NOTE : If the highest value for baud_count exceeds 127 you will need to adjust
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-- the range of integers in the signal declaration for baud_count.
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--
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baud_timer: process(clk)
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begin
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if clk'event and clk='1' then
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if baud_count=162 then
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baud_count <= 0;
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en_16_x_baud <= '1';
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else
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baud_count <= baud_count + 1;
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en_16_x_baud <= '0';
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end if;
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end if;
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end process baud_timer;
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----------------------------------------------------------------------------------------------------------------------------------
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end Behavioral;
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------------------------------------------------------------------------------------------------------------------------------------
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--
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-- END OF FILE uart_clock.vhd
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--
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------------------------------------------------------------------------------------------------------------------------------------
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