- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1416 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,111 @@
|
||||
Table of constant values and their specified constant labels.
|
||||
|
||||
00 UART_status_port
|
||||
01 tx_half_full
|
||||
02 tx_full
|
||||
04 rx_half_full
|
||||
08 rx_full
|
||||
10 rx_data_present
|
||||
01 UART_read_port
|
||||
01 UART_write_port
|
||||
00 alarm_port
|
||||
01 alarm_control
|
||||
00 us_time_stamp_lsb
|
||||
01 us_time_stamp_msb
|
||||
02 us_time_lsb
|
||||
03 us_time_msb
|
||||
04 ms_time_lsb
|
||||
05 ms_time_msb
|
||||
06 real_time_hours
|
||||
07 real_time_minutes
|
||||
08 real_time_seconds
|
||||
09 alarm_time_hours
|
||||
0A alarm_time_minutes
|
||||
0B alarm_time_seconds
|
||||
0C alarm_status
|
||||
01 alarm_active
|
||||
02 alarm_armed
|
||||
10 time_preserve0
|
||||
11 time_preserve1
|
||||
12 time_preserve2
|
||||
13 time_preserve3
|
||||
14 time_preserve4
|
||||
15 time_preserve5
|
||||
20 string_start
|
||||
E8 count_1000_lsb
|
||||
03 count_1000_msb
|
||||
18 hours_in_a_day
|
||||
3C minutes_in_an_hour
|
||||
3C seconds_in_a_minute
|
||||
61 character_a
|
||||
62 character_b
|
||||
63 character_c
|
||||
64 character_d
|
||||
65 character_e
|
||||
66 character_f
|
||||
67 character_g
|
||||
68 character_h
|
||||
69 character_i
|
||||
6A character_j
|
||||
6B character_k
|
||||
6C character_l
|
||||
6D character_m
|
||||
6E character_n
|
||||
6F character_o
|
||||
70 character_p
|
||||
71 character_q
|
||||
72 character_r
|
||||
73 character_s
|
||||
74 character_t
|
||||
75 character_u
|
||||
76 character_v
|
||||
77 character_w
|
||||
78 character_x
|
||||
79 character_y
|
||||
7A character_z
|
||||
41 character_A
|
||||
42 character_B
|
||||
43 character_C
|
||||
44 character_D
|
||||
45 character_E
|
||||
46 character_F
|
||||
47 character_G
|
||||
48 character_H
|
||||
49 character_I
|
||||
4A character_J
|
||||
4B character_K
|
||||
4C character_L
|
||||
4D character_M
|
||||
4E character_N
|
||||
4F character_O
|
||||
50 character_P
|
||||
51 character_Q
|
||||
52 character_R
|
||||
53 character_S
|
||||
54 character_T
|
||||
55 character_U
|
||||
56 character_V
|
||||
57 character_W
|
||||
58 character_X
|
||||
59 character_Y
|
||||
5A character_Z
|
||||
30 character_0
|
||||
31 character_1
|
||||
32 character_2
|
||||
33 character_3
|
||||
34 character_4
|
||||
35 character_5
|
||||
36 character_6
|
||||
37 character_7
|
||||
38 character_8
|
||||
39 character_9
|
||||
3A character_colon
|
||||
3B character_semi_colon
|
||||
3C character_less_than
|
||||
3E character_greater_than
|
||||
3D character_equals
|
||||
20 character_space
|
||||
0D character_CR
|
||||
3F character_question
|
||||
24 character_dollar
|
||||
08 character_BS
|
||||
@@ -0,0 +1,92 @@
|
||||
component_name=int_test;
|
||||
width_a=18;
|
||||
depth_a=1024;
|
||||
configuration_port_a=read_only;
|
||||
port_a_enable_pin=false;
|
||||
port_a_handshaking_pins=false;
|
||||
port_a_register_inputs=false;
|
||||
port_a_init_pin=false;
|
||||
port_a_init_value=00000;
|
||||
port_a_additional_output_pipe_stages = 0;
|
||||
port_a_register_inputs = false;
|
||||
port_a_active_clock_edge = Rising_Edge_Triggered;
|
||||
width_b=18;
|
||||
depth_b=1024;
|
||||
configuration_port_b=read_and_write;
|
||||
write_mode_port_b=read_after_write;
|
||||
port_b_enable_pin=false;
|
||||
port_b_handshaking_pins=false;
|
||||
port_b_register_inputs=false;
|
||||
port_b_init_pin=false;
|
||||
port_b_init_value=00000;
|
||||
port_b_additional_output_pipe_stages = 0;
|
||||
port_b_register_inputs = false;
|
||||
port_b_active_clock_edge = Rising_Edge_Triggered;
|
||||
port_b_write_enable_polarity = Active_High;
|
||||
memory_initialization_radix=16;
|
||||
global_init_value=00000;
|
||||
memory_initialization_vector=
|
||||
00A00, 002AA, 3C001, 2C202, 00007, 1C001, 35405, 0E2FF, 34003, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
18A01, 2CA04, 38001, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 342B0;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,25 @@
|
||||
;Interrupt example
|
||||
;
|
||||
CONSTANT waveform_port, 02 ;bit0 will be data
|
||||
CONSTANT counter_port, 04
|
||||
CONSTANT pattern_10101010, AA
|
||||
NAMEREG sA, interrupt_counter
|
||||
;
|
||||
start: LOAD interrupt_counter, 00 ;reset interrupt counter
|
||||
LOAD s2, pattern_10101010 ;initial output condition
|
||||
ENABLE INTERRUPT
|
||||
;
|
||||
drive_wave: OUTPUT s2, waveform_port
|
||||
LOAD s0, 07 ;delay size
|
||||
loop: SUB s0, 01 ;delay loop
|
||||
JUMP NZ, loop
|
||||
XOR s2, FF ;toggle waveform
|
||||
JUMP drive_wave
|
||||
;
|
||||
ADDRESS 2B0
|
||||
int_routine: ADD interrupt_counter, 01 ;increment counter
|
||||
OUTPUT interrupt_counter, counter_port
|
||||
RETURNI ENABLE
|
||||
;
|
||||
ADDRESS 3FF ;set interrupt vector
|
||||
JUMP int_routine
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,32 @@
|
||||
KCPSM3 Assembler log file for program 'int_test.psm'.
|
||||
Generated by KCPSM3 version 1.30
|
||||
Ken Chapman (Xilinx Ltd) 2005.
|
||||
25Sep2005-14:54:47
|
||||
|
||||
Addr Code
|
||||
|
||||
000 ;Interrupt example
|
||||
000 ;
|
||||
000 CONSTANT waveform_port, 02 ;bit0 will be data
|
||||
000 CONSTANT counter_port, 04
|
||||
000 CONSTANT pattern_10101010, AA
|
||||
000 NAMEREG sA, interrupt_counter
|
||||
000 ;
|
||||
000 00A00 start: LOAD interrupt_counter[sA], 00 ;reset interrupt counter
|
||||
001 002AA LOAD s2, pattern_10101010[AA] ;initial output condition
|
||||
002 3C001 ENABLE INTERRUPT
|
||||
003 ;
|
||||
003 2C202 drive_wave: OUTPUT s2, waveform_port[02]
|
||||
004 00007 LOAD s0, 07 ;delay size
|
||||
005 1C001 loop: SUB s0, 01 ;delay loop
|
||||
006 35405 JUMP NZ, loop[005]
|
||||
007 0E2FF XOR s2, FF ;toggle waveform
|
||||
008 34003 JUMP drive_wave[003]
|
||||
009 ;
|
||||
2B0 ADDRESS 2B0
|
||||
2B0 18A01 int_routine: ADD interrupt_counter[sA], 01 ;increment counter
|
||||
2B1 2CA04 OUTPUT interrupt_counter[sA], counter_port[04]
|
||||
2B2 38001 RETURNI ENABLE
|
||||
2B3 ;
|
||||
3FF ADDRESS 3FF ;set interrupt vector
|
||||
3FF 342B0 JUMP int_routine[2B0]
|
||||
@@ -0,0 +1,69 @@
|
||||
function bits = fill_int_test_program_store()
|
||||
bits = [ ...
|
||||
2560, 682, 245761, 180738, 7, 114689, 218117, 58111, 212995, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
100865, 182788, 229377, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 213680, ...
|
||||
];
|
||||
|
||||
return;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,262 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2004 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: v1.30
|
||||
// \ \ Application : KCPSM3
|
||||
// / / Filename: int_test.v
|
||||
// /___/ /\
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Command: kcpsm3 int_test.psm
|
||||
//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs
|
||||
//Design Name: int_test
|
||||
//Generated 25Sep2005-14:54:47.
|
||||
//Purpose:
|
||||
// int_test verilog program definition.
|
||||
//
|
||||
//Reference:
|
||||
// PicoBlaze 8-bit Embedded Microcontroller User Guide
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1 ps / 1ps
|
||||
module int_test (address, instruction, clk);
|
||||
input [9:0] address;
|
||||
input clk;
|
||||
output [17:0] instruction;
|
||||
RAMB16_S18 ram_1024_x_18(
|
||||
.DI (16'h0000),
|
||||
.DIP (2'b00),
|
||||
.EN (1'b1),
|
||||
.WE (1'b0),
|
||||
.SSR (1'b0),
|
||||
.CLK (clk),
|
||||
.ADDR (address),
|
||||
.DO (instruction[15:0]),
|
||||
.DOP (instruction[17:16]))
|
||||
/*synthesis
|
||||
init_00 = "00000000000000000000000000004003E2FF5405C0010007C202C00102AA0A00"
|
||||
init_01 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_02 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_03 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_04 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_05 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_06 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_07 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_08 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_09 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0B = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0F = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_10 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_11 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_12 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_13 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_14 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_15 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_16 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_17 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_18 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_19 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1B = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1F = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_20 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_21 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_22 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_23 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_24 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_25 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_26 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_27 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_28 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_29 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2B = "00000000000000000000000000000000000000000000000000008001CA048A01"
|
||||
init_2C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2F = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_30 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_31 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_32 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_33 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_34 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_35 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_36 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_37 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_38 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_39 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3B = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3F = "42B0000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_00 = "00000000000000000000000000000000000000000000000000000000000334B0"
|
||||
initp_01 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_02 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_03 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_04 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_05 = "0000000000000000000000000000000000000039000000000000000000000000"
|
||||
initp_06 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_07 = "C000000000000000000000000000000000000000000000000000000000000000" */;
|
||||
// synthesis translate_off
|
||||
// Attributes for Simulation
|
||||
defparam ram_1024_x_18.INIT_00 = 256'h00000000000000000000000000004003E2FF5405C0010007C202C00102AA0A00;
|
||||
defparam ram_1024_x_18.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2B = 256'h00000000000000000000000000000000000000000000000000008001CA048A01;
|
||||
defparam ram_1024_x_18.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3F = 256'h42B0000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_00 = 256'h00000000000000000000000000000000000000000000000000000000000334B0;
|
||||
defparam ram_1024_x_18.INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_05 = 256'h0000000000000000000000000000000000000039000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_07 = 256'hC000000000000000000000000000000000000000000000000000000000000000;
|
||||
// synthesis translate_on
|
||||
// Attributes for XST (Synplicity attributes are in-line)
|
||||
// synthesis attribute INIT_00 of ram_1024_x_18 is "00000000000000000000000000004003E2FF5405C0010007C202C00102AA0A00"
|
||||
// synthesis attribute INIT_01 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_02 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_03 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_04 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_05 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_06 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_07 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_08 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_09 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_10 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_11 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_12 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_13 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_14 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_15 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_16 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_17 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_18 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_19 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_20 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_21 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_22 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_23 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_24 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_25 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_26 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_27 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_28 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_29 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2B of ram_1024_x_18 is "00000000000000000000000000000000000000000000000000008001CA048A01"
|
||||
// synthesis attribute INIT_2C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_30 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_31 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_32 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_33 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_34 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_35 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_36 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_37 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_38 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_39 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3F of ram_1024_x_18 is "42B0000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_00 of ram_1024_x_18 is "00000000000000000000000000000000000000000000000000000000000334B0"
|
||||
// synthesis attribute INITP_01 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_02 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_03 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_04 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_05 of ram_1024_x_18 is "0000000000000000000000000000000000000039000000000000000000000000"
|
||||
// synthesis attribute INITP_06 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_07 of ram_1024_x_18 is "C000000000000000000000000000000000000000000000000000000000000000"
|
||||
endmodule
|
||||
// END OF FILE int_test.v
|
||||
@@ -0,0 +1,274 @@
|
||||
--
|
||||
-- Definition of a single port ROM for KCPSM3 program defined by int_test.psm
|
||||
--
|
||||
-- Generated by KCPSM3 Assembler 25Sep2005-14:54:47.
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
--
|
||||
entity int_test is
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end int_test;
|
||||
--
|
||||
architecture low_level_definition of int_test is
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
-- The information is repeated in the generic map for functional simulation
|
||||
--
|
||||
attribute INIT_00 : string;
|
||||
attribute INIT_01 : string;
|
||||
attribute INIT_02 : string;
|
||||
attribute INIT_03 : string;
|
||||
attribute INIT_04 : string;
|
||||
attribute INIT_05 : string;
|
||||
attribute INIT_06 : string;
|
||||
attribute INIT_07 : string;
|
||||
attribute INIT_08 : string;
|
||||
attribute INIT_09 : string;
|
||||
attribute INIT_0A : string;
|
||||
attribute INIT_0B : string;
|
||||
attribute INIT_0C : string;
|
||||
attribute INIT_0D : string;
|
||||
attribute INIT_0E : string;
|
||||
attribute INIT_0F : string;
|
||||
attribute INIT_10 : string;
|
||||
attribute INIT_11 : string;
|
||||
attribute INIT_12 : string;
|
||||
attribute INIT_13 : string;
|
||||
attribute INIT_14 : string;
|
||||
attribute INIT_15 : string;
|
||||
attribute INIT_16 : string;
|
||||
attribute INIT_17 : string;
|
||||
attribute INIT_18 : string;
|
||||
attribute INIT_19 : string;
|
||||
attribute INIT_1A : string;
|
||||
attribute INIT_1B : string;
|
||||
attribute INIT_1C : string;
|
||||
attribute INIT_1D : string;
|
||||
attribute INIT_1E : string;
|
||||
attribute INIT_1F : string;
|
||||
attribute INIT_20 : string;
|
||||
attribute INIT_21 : string;
|
||||
attribute INIT_22 : string;
|
||||
attribute INIT_23 : string;
|
||||
attribute INIT_24 : string;
|
||||
attribute INIT_25 : string;
|
||||
attribute INIT_26 : string;
|
||||
attribute INIT_27 : string;
|
||||
attribute INIT_28 : string;
|
||||
attribute INIT_29 : string;
|
||||
attribute INIT_2A : string;
|
||||
attribute INIT_2B : string;
|
||||
attribute INIT_2C : string;
|
||||
attribute INIT_2D : string;
|
||||
attribute INIT_2E : string;
|
||||
attribute INIT_2F : string;
|
||||
attribute INIT_30 : string;
|
||||
attribute INIT_31 : string;
|
||||
attribute INIT_32 : string;
|
||||
attribute INIT_33 : string;
|
||||
attribute INIT_34 : string;
|
||||
attribute INIT_35 : string;
|
||||
attribute INIT_36 : string;
|
||||
attribute INIT_37 : string;
|
||||
attribute INIT_38 : string;
|
||||
attribute INIT_39 : string;
|
||||
attribute INIT_3A : string;
|
||||
attribute INIT_3B : string;
|
||||
attribute INIT_3C : string;
|
||||
attribute INIT_3D : string;
|
||||
attribute INIT_3E : string;
|
||||
attribute INIT_3F : string;
|
||||
attribute INITP_00 : string;
|
||||
attribute INITP_01 : string;
|
||||
attribute INITP_02 : string;
|
||||
attribute INITP_03 : string;
|
||||
attribute INITP_04 : string;
|
||||
attribute INITP_05 : string;
|
||||
attribute INITP_06 : string;
|
||||
attribute INITP_07 : string;
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
--
|
||||
attribute INIT_00 of ram_1024_x_18 : label is "00000000000000000000000000004003E2FF5405C0010007C202C00102AA0A00";
|
||||
attribute INIT_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2B of ram_1024_x_18 : label is "00000000000000000000000000000000000000000000000000008001CA048A01";
|
||||
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3F of ram_1024_x_18 : label is "42B0000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_00 of ram_1024_x_18 : label is "00000000000000000000000000000000000000000000000000000000000334B0";
|
||||
attribute INITP_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000039000000000000000000000000";
|
||||
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_07 of ram_1024_x_18 : label is "C000000000000000000000000000000000000000000000000000000000000000";
|
||||
--
|
||||
begin
|
||||
--
|
||||
--Instantiate the Xilinx primitive for a block RAM
|
||||
ram_1024_x_18: RAMB16_S18
|
||||
--synthesis translate_off
|
||||
--INIT values repeated to define contents for functional simulation
|
||||
generic map ( INIT_00 => X"00000000000000000000000000004003E2FF5405C0010007C202C00102AA0A00",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"00000000000000000000000000000000000000000000000000008001CA048A01",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"42B0000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_00 => X"00000000000000000000000000000000000000000000000000000000000334B0",
|
||||
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_05 => X"0000000000000000000000000000000000000039000000000000000000000000",
|
||||
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_07 => X"C000000000000000000000000000000000000000000000000000000000000000")
|
||||
--synthesis translate_on
|
||||
port map( DI => "0000000000000000",
|
||||
DIP => "00",
|
||||
EN => '1',
|
||||
WE => '0',
|
||||
SSR => '0',
|
||||
CLK => clk,
|
||||
ADDR => address,
|
||||
DO => instruction(15 downto 0),
|
||||
DOP => instruction(17 downto 16));
|
||||
--
|
||||
end low_level_definition;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE int_test.vhd
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
Binary file not shown.
@@ -0,0 +1,63 @@
|
||||
Table of addresses and their specified labels.
|
||||
|
||||
000 cold_start
|
||||
012 prompt_input
|
||||
01C bad_input_command
|
||||
01E test_for_TIME
|
||||
02C set_time_command
|
||||
037 test_for_ALARM
|
||||
048 set_alarm_command
|
||||
055 set_alarm_on_off
|
||||
060 test_OFF
|
||||
06D test_time_string
|
||||
08B invalid_time
|
||||
091 fetch_char_from_memory
|
||||
095 read_from_UART
|
||||
09A read_character
|
||||
09D send_to_UART
|
||||
0A2 UART_write
|
||||
0A4 alarm_drive
|
||||
0A8 transmit_time
|
||||
0AC transmit_alarm_time
|
||||
0B6 test_armed
|
||||
0BA alarm_is_off
|
||||
0BC transmit_string
|
||||
0BD next_char_tx
|
||||
0C3 receive_string
|
||||
0C6 receive_full_test
|
||||
0D3 BS_edit
|
||||
0D9 string_start_again
|
||||
0DB read_error
|
||||
0DF clear_UART_Rx_loop
|
||||
0E4 send_CR
|
||||
0E7 send_space
|
||||
0EA send_backspace
|
||||
0ED send_Syntax_Error
|
||||
0FA send_Overflow_Error
|
||||
10A send_space_Error
|
||||
10B send_Error
|
||||
115 send_prompt
|
||||
122 send_greater_than
|
||||
125 send_Invalid
|
||||
134 send_Time
|
||||
13D send_Alarm
|
||||
148 send_OFF
|
||||
14E send_ON
|
||||
153 send_Active
|
||||
160 time_to_ASCII
|
||||
17E decimal_to_ASCII
|
||||
17F test_for_ten
|
||||
185 update_time
|
||||
19A test_1000us
|
||||
19F store_us_time
|
||||
1AD restore_ms_time
|
||||
1AF store_ms_time
|
||||
1B7 inc_minutes
|
||||
1BF inc_hours
|
||||
1C7 reset_hours
|
||||
1C9 time_update_complete
|
||||
1DB finish_update
|
||||
1E2 upper_case
|
||||
1E8 1char_to_value
|
||||
1EC 2char_to_value
|
||||
3FC ISR
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,29 @@
|
||||
component_name={name};
|
||||
width_a=18;
|
||||
depth_a=1024;
|
||||
configuration_port_a=read_only;
|
||||
port_a_enable_pin=false;
|
||||
port_a_handshaking_pins=false;
|
||||
port_a_register_inputs=false;
|
||||
port_a_init_pin=false;
|
||||
port_a_init_value=00000;
|
||||
port_a_additional_output_pipe_stages = 0;
|
||||
port_a_register_inputs = false;
|
||||
port_a_active_clock_edge = Rising_Edge_Triggered;
|
||||
width_b=18;
|
||||
depth_b=1024;
|
||||
configuration_port_b=read_and_write;
|
||||
write_mode_port_b=read_after_write;
|
||||
port_b_enable_pin=false;
|
||||
port_b_handshaking_pins=false;
|
||||
port_b_register_inputs=false;
|
||||
port_b_init_pin=false;
|
||||
port_b_init_value=00000;
|
||||
port_b_additional_output_pipe_stages = 0;
|
||||
port_b_register_inputs = false;
|
||||
port_b_active_clock_edge = Rising_Edge_Triggered;
|
||||
port_b_write_enable_polarity = Active_High;
|
||||
memory_initialization_radix=16;
|
||||
global_init_value=00000;
|
||||
memory_initialization_vector=
|
||||
|
||||
@@ -0,0 +1,350 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2004 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: 1.02
|
||||
// \ \ Filename: ROM_form.v
|
||||
// / / Date Last Modified: September 7 2004
|
||||
// /___/ /\ Date Created: July 2003
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Device: Xilinx
|
||||
//Purpose:
|
||||
// This is the Verilog template file for the KCPSM3 assembler.
|
||||
// It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block
|
||||
// RAM to act as a single port program ROM.
|
||||
//
|
||||
// This Verilog file is not valid as input directly into a synthesis or
|
||||
// simulation tool. The assembler will read this template and insert the
|
||||
// data required to complete the definition of program ROM and write it out
|
||||
// to a new '.v' file associated with the name of the original '.psm' file
|
||||
// being assembled.
|
||||
//
|
||||
// This template can be modified to define alternative memory definitions
|
||||
// such as dual port. However, you are responsible for ensuring the template
|
||||
// is correct as the assembler does not perform any checking of the Verilog.
|
||||
//
|
||||
// The assembler identifies all text enclosed by {} characters, and replaces
|
||||
// these character strings. All templates should include these {} character
|
||||
// strings for the assembler to work correctly.
|
||||
//
|
||||
// This template defines a block RAM configured in 1024 x 18-bit single port
|
||||
// mode and conneceted to act as a single port ROM.
|
||||
//
|
||||
//Reference:
|
||||
// None
|
||||
//Revision History:
|
||||
// Rev 1.00 - jc - Converted to verilog, July 2003.
|
||||
// Rev 1.01 - sus - Added text to confirm to Xilinx HDL std, August 4 2004.
|
||||
// Rev 1.02 - njs - Added attributes for Synplicity August 5 2004.
|
||||
// Rev 1.03 - sus - Added text to conform to Xilinx generated
|
||||
// HDL spec, September 7 2004
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Contact: e-mail picoblaze@xilinx.com
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Disclaimer:
|
||||
// LIMITED WARRANTY AND DISCLAIMER. These designs are
|
||||
// provided to you "as is". Xilinx and its licensors make and you
|
||||
// receive no warranties or conditions, express, implied,
|
||||
// statutory or otherwise, and Xilinx specifically disclaims any
|
||||
// implied warranties of merchantability, non-infringement, or
|
||||
// fitness for a particular purpose. Xilinx does not warrant that
|
||||
// the functions contained in these designs will meet your
|
||||
// requirements, or that the operation of these designs will be
|
||||
// uninterrupted or error free, or that defects in the Designs
|
||||
// will be corrected. Furthermore, Xilinx does not warrant or
|
||||
// make any representations regarding use or the results of the
|
||||
// use of the designs in terms of correctness, accuracy,
|
||||
// reliability, or otherwise.
|
||||
//
|
||||
// LIMITATION OF LIABILITY. In no event will Xilinx or its
|
||||
// licensors be liable for any loss of data, lost profits, cost
|
||||
// or procurement of substitute goods or services, or for any
|
||||
// special, incidental, consequential, or indirect damages
|
||||
// arising from the use or operation of the designs or
|
||||
// accompanying documentation, however caused and on any theory
|
||||
// of liability. This limitation will apply even if Xilinx
|
||||
// has been advised of the possibility of such damage. This
|
||||
// limitation shall apply not-withstanding the failure of the
|
||||
// essential purpose of any limited remedies herein.
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
The next line is used to determine where the template actually starts and must exist.
|
||||
{begin template}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2004 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: v1.30
|
||||
// \ \ Application : KCPSM3
|
||||
// / / Filename: {name}.v
|
||||
// /___/ /\
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Command: kcpsm3 {name}.psm
|
||||
//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs
|
||||
//Design Name: {name}
|
||||
//Generated {timestamp}.
|
||||
//Purpose:
|
||||
// {name} verilog program definition.
|
||||
//
|
||||
//Reference:
|
||||
// PicoBlaze 8-bit Embedded Microcontroller User Guide
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1 ps / 1ps
|
||||
|
||||
module {name} (address, instruction, clk);
|
||||
|
||||
input [9:0] address;
|
||||
input clk;
|
||||
|
||||
output [17:0] instruction;
|
||||
|
||||
RAMB16_S18 ram_1024_x_18(
|
||||
.DI (16'h0000),
|
||||
.DIP (2'b00),
|
||||
.EN (1'b1),
|
||||
.WE (1'b0),
|
||||
.SSR (1'b0),
|
||||
.CLK (clk),
|
||||
.ADDR (address),
|
||||
.DO (instruction[15:0]),
|
||||
.DOP (instruction[17:16]))
|
||||
/*synthesis
|
||||
init_00 = "{INIT_00}"
|
||||
init_01 = "{INIT_01}"
|
||||
init_02 = "{INIT_02}"
|
||||
init_03 = "{INIT_03}"
|
||||
init_04 = "{INIT_04}"
|
||||
init_05 = "{INIT_05}"
|
||||
init_06 = "{INIT_06}"
|
||||
init_07 = "{INIT_07}"
|
||||
init_08 = "{INIT_08}"
|
||||
init_09 = "{INIT_09}"
|
||||
init_0A = "{INIT_0A}"
|
||||
init_0B = "{INIT_0B}"
|
||||
init_0C = "{INIT_0C}"
|
||||
init_0D = "{INIT_0D}"
|
||||
init_0E = "{INIT_0E}"
|
||||
init_0F = "{INIT_0F}"
|
||||
init_10 = "{INIT_10}"
|
||||
init_11 = "{INIT_11}"
|
||||
init_12 = "{INIT_12}"
|
||||
init_13 = "{INIT_13}"
|
||||
init_14 = "{INIT_14}"
|
||||
init_15 = "{INIT_15}"
|
||||
init_16 = "{INIT_16}"
|
||||
init_17 = "{INIT_17}"
|
||||
init_18 = "{INIT_18}"
|
||||
init_19 = "{INIT_19}"
|
||||
init_1A = "{INIT_1A}"
|
||||
init_1B = "{INIT_1B}"
|
||||
init_1C = "{INIT_1C}"
|
||||
init_1D = "{INIT_1D}"
|
||||
init_1E = "{INIT_1E}"
|
||||
init_1F = "{INIT_1F}"
|
||||
init_20 = "{INIT_20}"
|
||||
init_21 = "{INIT_21}"
|
||||
init_22 = "{INIT_22}"
|
||||
init_23 = "{INIT_23}"
|
||||
init_24 = "{INIT_24}"
|
||||
init_25 = "{INIT_25}"
|
||||
init_26 = "{INIT_26}"
|
||||
init_27 = "{INIT_27}"
|
||||
init_28 = "{INIT_28}"
|
||||
init_29 = "{INIT_29}"
|
||||
init_2A = "{INIT_2A}"
|
||||
init_2B = "{INIT_2B}"
|
||||
init_2C = "{INIT_2C}"
|
||||
init_2D = "{INIT_2D}"
|
||||
init_2E = "{INIT_2E}"
|
||||
init_2F = "{INIT_2F}"
|
||||
init_30 = "{INIT_30}"
|
||||
init_31 = "{INIT_31}"
|
||||
init_32 = "{INIT_32}"
|
||||
init_33 = "{INIT_33}"
|
||||
init_34 = "{INIT_34}"
|
||||
init_35 = "{INIT_35}"
|
||||
init_36 = "{INIT_36}"
|
||||
init_37 = "{INIT_37}"
|
||||
init_38 = "{INIT_38}"
|
||||
init_39 = "{INIT_39}"
|
||||
init_3A = "{INIT_3A}"
|
||||
init_3B = "{INIT_3B}"
|
||||
init_3C = "{INIT_3C}"
|
||||
init_3D = "{INIT_3D}"
|
||||
init_3E = "{INIT_3E}"
|
||||
init_3F = "{INIT_3F}"
|
||||
initp_00 = "{INITP_00}"
|
||||
initp_01 = "{INITP_01}"
|
||||
initp_02 = "{INITP_02}"
|
||||
initp_03 = "{INITP_03}"
|
||||
initp_04 = "{INITP_04}"
|
||||
initp_05 = "{INITP_05}"
|
||||
initp_06 = "{INITP_06}"
|
||||
initp_07 = "{INITP_07}" */;
|
||||
|
||||
// synthesis translate_off
|
||||
// Attributes for Simulation
|
||||
defparam ram_1024_x_18.INIT_00 = 256'h{INIT_00};
|
||||
defparam ram_1024_x_18.INIT_01 = 256'h{INIT_01};
|
||||
defparam ram_1024_x_18.INIT_02 = 256'h{INIT_02};
|
||||
defparam ram_1024_x_18.INIT_03 = 256'h{INIT_03};
|
||||
defparam ram_1024_x_18.INIT_04 = 256'h{INIT_04};
|
||||
defparam ram_1024_x_18.INIT_05 = 256'h{INIT_05};
|
||||
defparam ram_1024_x_18.INIT_06 = 256'h{INIT_06};
|
||||
defparam ram_1024_x_18.INIT_07 = 256'h{INIT_07};
|
||||
defparam ram_1024_x_18.INIT_08 = 256'h{INIT_08};
|
||||
defparam ram_1024_x_18.INIT_09 = 256'h{INIT_09};
|
||||
defparam ram_1024_x_18.INIT_0A = 256'h{INIT_0A};
|
||||
defparam ram_1024_x_18.INIT_0B = 256'h{INIT_0B};
|
||||
defparam ram_1024_x_18.INIT_0C = 256'h{INIT_0C};
|
||||
defparam ram_1024_x_18.INIT_0D = 256'h{INIT_0D};
|
||||
defparam ram_1024_x_18.INIT_0E = 256'h{INIT_0E};
|
||||
defparam ram_1024_x_18.INIT_0F = 256'h{INIT_0F};
|
||||
defparam ram_1024_x_18.INIT_10 = 256'h{INIT_10};
|
||||
defparam ram_1024_x_18.INIT_11 = 256'h{INIT_11};
|
||||
defparam ram_1024_x_18.INIT_12 = 256'h{INIT_12};
|
||||
defparam ram_1024_x_18.INIT_13 = 256'h{INIT_13};
|
||||
defparam ram_1024_x_18.INIT_14 = 256'h{INIT_14};
|
||||
defparam ram_1024_x_18.INIT_15 = 256'h{INIT_15};
|
||||
defparam ram_1024_x_18.INIT_16 = 256'h{INIT_16};
|
||||
defparam ram_1024_x_18.INIT_17 = 256'h{INIT_17};
|
||||
defparam ram_1024_x_18.INIT_18 = 256'h{INIT_18};
|
||||
defparam ram_1024_x_18.INIT_19 = 256'h{INIT_19};
|
||||
defparam ram_1024_x_18.INIT_1A = 256'h{INIT_1A};
|
||||
defparam ram_1024_x_18.INIT_1B = 256'h{INIT_1B};
|
||||
defparam ram_1024_x_18.INIT_1C = 256'h{INIT_1C};
|
||||
defparam ram_1024_x_18.INIT_1D = 256'h{INIT_1D};
|
||||
defparam ram_1024_x_18.INIT_1E = 256'h{INIT_1E};
|
||||
defparam ram_1024_x_18.INIT_1F = 256'h{INIT_1F};
|
||||
defparam ram_1024_x_18.INIT_20 = 256'h{INIT_20};
|
||||
defparam ram_1024_x_18.INIT_21 = 256'h{INIT_21};
|
||||
defparam ram_1024_x_18.INIT_22 = 256'h{INIT_22};
|
||||
defparam ram_1024_x_18.INIT_23 = 256'h{INIT_23};
|
||||
defparam ram_1024_x_18.INIT_24 = 256'h{INIT_24};
|
||||
defparam ram_1024_x_18.INIT_25 = 256'h{INIT_25};
|
||||
defparam ram_1024_x_18.INIT_26 = 256'h{INIT_26};
|
||||
defparam ram_1024_x_18.INIT_27 = 256'h{INIT_27};
|
||||
defparam ram_1024_x_18.INIT_28 = 256'h{INIT_28};
|
||||
defparam ram_1024_x_18.INIT_29 = 256'h{INIT_29};
|
||||
defparam ram_1024_x_18.INIT_2A = 256'h{INIT_2A};
|
||||
defparam ram_1024_x_18.INIT_2B = 256'h{INIT_2B};
|
||||
defparam ram_1024_x_18.INIT_2C = 256'h{INIT_2C};
|
||||
defparam ram_1024_x_18.INIT_2D = 256'h{INIT_2D};
|
||||
defparam ram_1024_x_18.INIT_2E = 256'h{INIT_2E};
|
||||
defparam ram_1024_x_18.INIT_2F = 256'h{INIT_2F};
|
||||
defparam ram_1024_x_18.INIT_30 = 256'h{INIT_30};
|
||||
defparam ram_1024_x_18.INIT_31 = 256'h{INIT_31};
|
||||
defparam ram_1024_x_18.INIT_32 = 256'h{INIT_32};
|
||||
defparam ram_1024_x_18.INIT_33 = 256'h{INIT_33};
|
||||
defparam ram_1024_x_18.INIT_34 = 256'h{INIT_34};
|
||||
defparam ram_1024_x_18.INIT_35 = 256'h{INIT_35};
|
||||
defparam ram_1024_x_18.INIT_36 = 256'h{INIT_36};
|
||||
defparam ram_1024_x_18.INIT_37 = 256'h{INIT_37};
|
||||
defparam ram_1024_x_18.INIT_38 = 256'h{INIT_38};
|
||||
defparam ram_1024_x_18.INIT_39 = 256'h{INIT_39};
|
||||
defparam ram_1024_x_18.INIT_3A = 256'h{INIT_3A};
|
||||
defparam ram_1024_x_18.INIT_3B = 256'h{INIT_3B};
|
||||
defparam ram_1024_x_18.INIT_3C = 256'h{INIT_3C};
|
||||
defparam ram_1024_x_18.INIT_3D = 256'h{INIT_3D};
|
||||
defparam ram_1024_x_18.INIT_3E = 256'h{INIT_3E};
|
||||
defparam ram_1024_x_18.INIT_3F = 256'h{INIT_3F};
|
||||
defparam ram_1024_x_18.INITP_00 = 256'h{INITP_00};
|
||||
defparam ram_1024_x_18.INITP_01 = 256'h{INITP_01};
|
||||
defparam ram_1024_x_18.INITP_02 = 256'h{INITP_02};
|
||||
defparam ram_1024_x_18.INITP_03 = 256'h{INITP_03};
|
||||
defparam ram_1024_x_18.INITP_04 = 256'h{INITP_04};
|
||||
defparam ram_1024_x_18.INITP_05 = 256'h{INITP_05};
|
||||
defparam ram_1024_x_18.INITP_06 = 256'h{INITP_06};
|
||||
defparam ram_1024_x_18.INITP_07 = 256'h{INITP_07};
|
||||
|
||||
// synthesis translate_on
|
||||
// Attributes for XST (Synplicity attributes are in-line)
|
||||
// synthesis attribute INIT_00 of ram_1024_x_18 is "{INIT_00}"
|
||||
// synthesis attribute INIT_01 of ram_1024_x_18 is "{INIT_01}"
|
||||
// synthesis attribute INIT_02 of ram_1024_x_18 is "{INIT_02}"
|
||||
// synthesis attribute INIT_03 of ram_1024_x_18 is "{INIT_03}"
|
||||
// synthesis attribute INIT_04 of ram_1024_x_18 is "{INIT_04}"
|
||||
// synthesis attribute INIT_05 of ram_1024_x_18 is "{INIT_05}"
|
||||
// synthesis attribute INIT_06 of ram_1024_x_18 is "{INIT_06}"
|
||||
// synthesis attribute INIT_07 of ram_1024_x_18 is "{INIT_07}"
|
||||
// synthesis attribute INIT_08 of ram_1024_x_18 is "{INIT_08}"
|
||||
// synthesis attribute INIT_09 of ram_1024_x_18 is "{INIT_09}"
|
||||
// synthesis attribute INIT_0A of ram_1024_x_18 is "{INIT_0A}"
|
||||
// synthesis attribute INIT_0B of ram_1024_x_18 is "{INIT_0B}"
|
||||
// synthesis attribute INIT_0C of ram_1024_x_18 is "{INIT_0C}"
|
||||
// synthesis attribute INIT_0D of ram_1024_x_18 is "{INIT_0D}"
|
||||
// synthesis attribute INIT_0E of ram_1024_x_18 is "{INIT_0E}"
|
||||
// synthesis attribute INIT_0F of ram_1024_x_18 is "{INIT_0F}"
|
||||
// synthesis attribute INIT_10 of ram_1024_x_18 is "{INIT_10}"
|
||||
// synthesis attribute INIT_11 of ram_1024_x_18 is "{INIT_11}"
|
||||
// synthesis attribute INIT_12 of ram_1024_x_18 is "{INIT_12}"
|
||||
// synthesis attribute INIT_13 of ram_1024_x_18 is "{INIT_13}"
|
||||
// synthesis attribute INIT_14 of ram_1024_x_18 is "{INIT_14}"
|
||||
// synthesis attribute INIT_15 of ram_1024_x_18 is "{INIT_15}"
|
||||
// synthesis attribute INIT_16 of ram_1024_x_18 is "{INIT_16}"
|
||||
// synthesis attribute INIT_17 of ram_1024_x_18 is "{INIT_17}"
|
||||
// synthesis attribute INIT_18 of ram_1024_x_18 is "{INIT_18}"
|
||||
// synthesis attribute INIT_19 of ram_1024_x_18 is "{INIT_19}"
|
||||
// synthesis attribute INIT_1A of ram_1024_x_18 is "{INIT_1A}"
|
||||
// synthesis attribute INIT_1B of ram_1024_x_18 is "{INIT_1B}"
|
||||
// synthesis attribute INIT_1C of ram_1024_x_18 is "{INIT_1C}"
|
||||
// synthesis attribute INIT_1D of ram_1024_x_18 is "{INIT_1D}"
|
||||
// synthesis attribute INIT_1E of ram_1024_x_18 is "{INIT_1E}"
|
||||
// synthesis attribute INIT_1F of ram_1024_x_18 is "{INIT_1F}"
|
||||
// synthesis attribute INIT_20 of ram_1024_x_18 is "{INIT_20}"
|
||||
// synthesis attribute INIT_21 of ram_1024_x_18 is "{INIT_21}"
|
||||
// synthesis attribute INIT_22 of ram_1024_x_18 is "{INIT_22}"
|
||||
// synthesis attribute INIT_23 of ram_1024_x_18 is "{INIT_23}"
|
||||
// synthesis attribute INIT_24 of ram_1024_x_18 is "{INIT_24}"
|
||||
// synthesis attribute INIT_25 of ram_1024_x_18 is "{INIT_25}"
|
||||
// synthesis attribute INIT_26 of ram_1024_x_18 is "{INIT_26}"
|
||||
// synthesis attribute INIT_27 of ram_1024_x_18 is "{INIT_27}"
|
||||
// synthesis attribute INIT_28 of ram_1024_x_18 is "{INIT_28}"
|
||||
// synthesis attribute INIT_29 of ram_1024_x_18 is "{INIT_29}"
|
||||
// synthesis attribute INIT_2A of ram_1024_x_18 is "{INIT_2A}"
|
||||
// synthesis attribute INIT_2B of ram_1024_x_18 is "{INIT_2B}"
|
||||
// synthesis attribute INIT_2C of ram_1024_x_18 is "{INIT_2C}"
|
||||
// synthesis attribute INIT_2D of ram_1024_x_18 is "{INIT_2D}"
|
||||
// synthesis attribute INIT_2E of ram_1024_x_18 is "{INIT_2E}"
|
||||
// synthesis attribute INIT_2F of ram_1024_x_18 is "{INIT_2F}"
|
||||
// synthesis attribute INIT_30 of ram_1024_x_18 is "{INIT_30}"
|
||||
// synthesis attribute INIT_31 of ram_1024_x_18 is "{INIT_31}"
|
||||
// synthesis attribute INIT_32 of ram_1024_x_18 is "{INIT_32}"
|
||||
// synthesis attribute INIT_33 of ram_1024_x_18 is "{INIT_33}"
|
||||
// synthesis attribute INIT_34 of ram_1024_x_18 is "{INIT_34}"
|
||||
// synthesis attribute INIT_35 of ram_1024_x_18 is "{INIT_35}"
|
||||
// synthesis attribute INIT_36 of ram_1024_x_18 is "{INIT_36}"
|
||||
// synthesis attribute INIT_37 of ram_1024_x_18 is "{INIT_37}"
|
||||
// synthesis attribute INIT_38 of ram_1024_x_18 is "{INIT_38}"
|
||||
// synthesis attribute INIT_39 of ram_1024_x_18 is "{INIT_39}"
|
||||
// synthesis attribute INIT_3A of ram_1024_x_18 is "{INIT_3A}"
|
||||
// synthesis attribute INIT_3B of ram_1024_x_18 is "{INIT_3B}"
|
||||
// synthesis attribute INIT_3C of ram_1024_x_18 is "{INIT_3C}"
|
||||
// synthesis attribute INIT_3D of ram_1024_x_18 is "{INIT_3D}"
|
||||
// synthesis attribute INIT_3E of ram_1024_x_18 is "{INIT_3E}"
|
||||
// synthesis attribute INIT_3F of ram_1024_x_18 is "{INIT_3F}"
|
||||
// synthesis attribute INITP_00 of ram_1024_x_18 is "{INITP_00}"
|
||||
// synthesis attribute INITP_01 of ram_1024_x_18 is "{INITP_01}"
|
||||
// synthesis attribute INITP_02 of ram_1024_x_18 is "{INITP_02}"
|
||||
// synthesis attribute INITP_03 of ram_1024_x_18 is "{INITP_03}"
|
||||
// synthesis attribute INITP_04 of ram_1024_x_18 is "{INITP_04}"
|
||||
// synthesis attribute INITP_05 of ram_1024_x_18 is "{INITP_05}"
|
||||
// synthesis attribute INITP_06 of ram_1024_x_18 is "{INITP_06}"
|
||||
// synthesis attribute INITP_07 of ram_1024_x_18 is "{INITP_07}"
|
||||
|
||||
endmodule
|
||||
|
||||
// END OF FILE {name}.v
|
||||
@@ -0,0 +1,305 @@
|
||||
ROM_form.vhd
|
||||
|
||||
Ken Chapman (Xilinx Ltd) July 2003
|
||||
|
||||
This is the VHDL template file for the KCPSM3 assembler.
|
||||
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
|
||||
a single port program ROM.
|
||||
|
||||
This VHDL file is not valid as input directly into a synthesis or simulation tool.
|
||||
The assembler will read this template and insert the data required to complete the
|
||||
definition of program ROM and write it out to a new '.vhd' file associated with the
|
||||
name of the original '.psm' file being assembled.
|
||||
|
||||
This template can be modified to define alternative memory definitions such as dual port.
|
||||
However, you are responsible for ensuring the template is correct as the assembler does
|
||||
not perform any checking of the VHDL.
|
||||
|
||||
The assembler identifies all text enclosed by {} characters, and replaces these
|
||||
character strings. All templates should include these {} character strings for
|
||||
the assembler to work correctly.
|
||||
|
||||
****************************************************************************************
|
||||
|
||||
This template defines a block RAM configured in 1024 x 18-bit single port mode and
|
||||
conneceted to act as a single port ROM.
|
||||
|
||||
****************************************************************************************
|
||||
|
||||
The next line is used to determine where the template actually starts and must exist.
|
||||
{begin template}
|
||||
--
|
||||
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
|
||||
--
|
||||
-- Generated by KCPSM3 Assembler {timestamp}.
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
--
|
||||
entity {name} is
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end {name};
|
||||
--
|
||||
architecture low_level_definition of {name} is
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
-- The information is repeated in the generic map for functional simulation
|
||||
--
|
||||
attribute INIT_00 : string;
|
||||
attribute INIT_01 : string;
|
||||
attribute INIT_02 : string;
|
||||
attribute INIT_03 : string;
|
||||
attribute INIT_04 : string;
|
||||
attribute INIT_05 : string;
|
||||
attribute INIT_06 : string;
|
||||
attribute INIT_07 : string;
|
||||
attribute INIT_08 : string;
|
||||
attribute INIT_09 : string;
|
||||
attribute INIT_0A : string;
|
||||
attribute INIT_0B : string;
|
||||
attribute INIT_0C : string;
|
||||
attribute INIT_0D : string;
|
||||
attribute INIT_0E : string;
|
||||
attribute INIT_0F : string;
|
||||
attribute INIT_10 : string;
|
||||
attribute INIT_11 : string;
|
||||
attribute INIT_12 : string;
|
||||
attribute INIT_13 : string;
|
||||
attribute INIT_14 : string;
|
||||
attribute INIT_15 : string;
|
||||
attribute INIT_16 : string;
|
||||
attribute INIT_17 : string;
|
||||
attribute INIT_18 : string;
|
||||
attribute INIT_19 : string;
|
||||
attribute INIT_1A : string;
|
||||
attribute INIT_1B : string;
|
||||
attribute INIT_1C : string;
|
||||
attribute INIT_1D : string;
|
||||
attribute INIT_1E : string;
|
||||
attribute INIT_1F : string;
|
||||
attribute INIT_20 : string;
|
||||
attribute INIT_21 : string;
|
||||
attribute INIT_22 : string;
|
||||
attribute INIT_23 : string;
|
||||
attribute INIT_24 : string;
|
||||
attribute INIT_25 : string;
|
||||
attribute INIT_26 : string;
|
||||
attribute INIT_27 : string;
|
||||
attribute INIT_28 : string;
|
||||
attribute INIT_29 : string;
|
||||
attribute INIT_2A : string;
|
||||
attribute INIT_2B : string;
|
||||
attribute INIT_2C : string;
|
||||
attribute INIT_2D : string;
|
||||
attribute INIT_2E : string;
|
||||
attribute INIT_2F : string;
|
||||
attribute INIT_30 : string;
|
||||
attribute INIT_31 : string;
|
||||
attribute INIT_32 : string;
|
||||
attribute INIT_33 : string;
|
||||
attribute INIT_34 : string;
|
||||
attribute INIT_35 : string;
|
||||
attribute INIT_36 : string;
|
||||
attribute INIT_37 : string;
|
||||
attribute INIT_38 : string;
|
||||
attribute INIT_39 : string;
|
||||
attribute INIT_3A : string;
|
||||
attribute INIT_3B : string;
|
||||
attribute INIT_3C : string;
|
||||
attribute INIT_3D : string;
|
||||
attribute INIT_3E : string;
|
||||
attribute INIT_3F : string;
|
||||
attribute INITP_00 : string;
|
||||
attribute INITP_01 : string;
|
||||
attribute INITP_02 : string;
|
||||
attribute INITP_03 : string;
|
||||
attribute INITP_04 : string;
|
||||
attribute INITP_05 : string;
|
||||
attribute INITP_06 : string;
|
||||
attribute INITP_07 : string;
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
--
|
||||
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
|
||||
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
|
||||
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
|
||||
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
|
||||
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
|
||||
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
|
||||
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
|
||||
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
|
||||
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
|
||||
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
|
||||
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
|
||||
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
|
||||
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
|
||||
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
|
||||
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
|
||||
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
|
||||
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
|
||||
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
|
||||
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
|
||||
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
|
||||
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
|
||||
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
|
||||
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
|
||||
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
|
||||
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
|
||||
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
|
||||
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
|
||||
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
|
||||
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
|
||||
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
|
||||
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
|
||||
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
|
||||
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
|
||||
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
|
||||
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
|
||||
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
|
||||
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
|
||||
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
|
||||
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
|
||||
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
|
||||
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
|
||||
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
|
||||
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
|
||||
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
|
||||
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
|
||||
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
|
||||
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
|
||||
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
|
||||
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
|
||||
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
|
||||
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
|
||||
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
|
||||
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
|
||||
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
|
||||
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
|
||||
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
|
||||
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
|
||||
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
|
||||
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
|
||||
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
|
||||
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
|
||||
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
|
||||
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
|
||||
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
|
||||
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
|
||||
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
|
||||
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
|
||||
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
|
||||
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
|
||||
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
|
||||
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
|
||||
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
|
||||
--
|
||||
begin
|
||||
--
|
||||
--Instantiate the Xilinx primitive for a block RAM
|
||||
ram_1024_x_18: RAMB16_S18
|
||||
--synthesis translate_off
|
||||
--INIT values repeated to define contents for functional simulation
|
||||
generic map ( INIT_00 => X"{INIT_00}",
|
||||
INIT_01 => X"{INIT_01}",
|
||||
INIT_02 => X"{INIT_02}",
|
||||
INIT_03 => X"{INIT_03}",
|
||||
INIT_04 => X"{INIT_04}",
|
||||
INIT_05 => X"{INIT_05}",
|
||||
INIT_06 => X"{INIT_06}",
|
||||
INIT_07 => X"{INIT_07}",
|
||||
INIT_08 => X"{INIT_08}",
|
||||
INIT_09 => X"{INIT_09}",
|
||||
INIT_0A => X"{INIT_0A}",
|
||||
INIT_0B => X"{INIT_0B}",
|
||||
INIT_0C => X"{INIT_0C}",
|
||||
INIT_0D => X"{INIT_0D}",
|
||||
INIT_0E => X"{INIT_0E}",
|
||||
INIT_0F => X"{INIT_0F}",
|
||||
INIT_10 => X"{INIT_10}",
|
||||
INIT_11 => X"{INIT_11}",
|
||||
INIT_12 => X"{INIT_12}",
|
||||
INIT_13 => X"{INIT_13}",
|
||||
INIT_14 => X"{INIT_14}",
|
||||
INIT_15 => X"{INIT_15}",
|
||||
INIT_16 => X"{INIT_16}",
|
||||
INIT_17 => X"{INIT_17}",
|
||||
INIT_18 => X"{INIT_18}",
|
||||
INIT_19 => X"{INIT_19}",
|
||||
INIT_1A => X"{INIT_1A}",
|
||||
INIT_1B => X"{INIT_1B}",
|
||||
INIT_1C => X"{INIT_1C}",
|
||||
INIT_1D => X"{INIT_1D}",
|
||||
INIT_1E => X"{INIT_1E}",
|
||||
INIT_1F => X"{INIT_1F}",
|
||||
INIT_20 => X"{INIT_20}",
|
||||
INIT_21 => X"{INIT_21}",
|
||||
INIT_22 => X"{INIT_22}",
|
||||
INIT_23 => X"{INIT_23}",
|
||||
INIT_24 => X"{INIT_24}",
|
||||
INIT_25 => X"{INIT_25}",
|
||||
INIT_26 => X"{INIT_26}",
|
||||
INIT_27 => X"{INIT_27}",
|
||||
INIT_28 => X"{INIT_28}",
|
||||
INIT_29 => X"{INIT_29}",
|
||||
INIT_2A => X"{INIT_2A}",
|
||||
INIT_2B => X"{INIT_2B}",
|
||||
INIT_2C => X"{INIT_2C}",
|
||||
INIT_2D => X"{INIT_2D}",
|
||||
INIT_2E => X"{INIT_2E}",
|
||||
INIT_2F => X"{INIT_2F}",
|
||||
INIT_30 => X"{INIT_30}",
|
||||
INIT_31 => X"{INIT_31}",
|
||||
INIT_32 => X"{INIT_32}",
|
||||
INIT_33 => X"{INIT_33}",
|
||||
INIT_34 => X"{INIT_34}",
|
||||
INIT_35 => X"{INIT_35}",
|
||||
INIT_36 => X"{INIT_36}",
|
||||
INIT_37 => X"{INIT_37}",
|
||||
INIT_38 => X"{INIT_38}",
|
||||
INIT_39 => X"{INIT_39}",
|
||||
INIT_3A => X"{INIT_3A}",
|
||||
INIT_3B => X"{INIT_3B}",
|
||||
INIT_3C => X"{INIT_3C}",
|
||||
INIT_3D => X"{INIT_3D}",
|
||||
INIT_3E => X"{INIT_3E}",
|
||||
INIT_3F => X"{INIT_3F}",
|
||||
INITP_00 => X"{INITP_00}",
|
||||
INITP_01 => X"{INITP_01}",
|
||||
INITP_02 => X"{INITP_02}",
|
||||
INITP_03 => X"{INITP_03}",
|
||||
INITP_04 => X"{INITP_04}",
|
||||
INITP_05 => X"{INITP_05}",
|
||||
INITP_06 => X"{INITP_06}",
|
||||
INITP_07 => X"{INITP_07}")
|
||||
--synthesis translate_on
|
||||
port map( DI => "0000000000000000",
|
||||
DIP => "00",
|
||||
EN => '1',
|
||||
WE => '0',
|
||||
SSR => '0',
|
||||
CLK => clk,
|
||||
ADDR => address,
|
||||
DO => instruction(15 downto 0),
|
||||
DOP => instruction(17 downto 16));
|
||||
--
|
||||
end low_level_definition;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE {name}.vhd
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,92 @@
|
||||
component_name=uclock;
|
||||
width_a=18;
|
||||
depth_a=1024;
|
||||
configuration_port_a=read_only;
|
||||
port_a_enable_pin=false;
|
||||
port_a_handshaking_pins=false;
|
||||
port_a_register_inputs=false;
|
||||
port_a_init_pin=false;
|
||||
port_a_init_value=00000;
|
||||
port_a_additional_output_pipe_stages = 0;
|
||||
port_a_register_inputs = false;
|
||||
port_a_active_clock_edge = Rising_Edge_Triggered;
|
||||
width_b=18;
|
||||
depth_b=1024;
|
||||
configuration_port_b=read_and_write;
|
||||
write_mode_port_b=read_after_write;
|
||||
port_b_enable_pin=false;
|
||||
port_b_handshaking_pins=false;
|
||||
port_b_register_inputs=false;
|
||||
port_b_init_pin=false;
|
||||
port_b_init_value=00000;
|
||||
port_b_additional_output_pipe_stages = 0;
|
||||
port_b_register_inputs = false;
|
||||
port_b_active_clock_edge = Rising_Edge_Triggered;
|
||||
port_b_write_enable_polarity = Active_High;
|
||||
memory_initialization_radix=16;
|
||||
global_init_value=00000;
|
||||
memory_initialization_vector=
|
||||
00000, 2E000, 2E001, 2E002, 2E003, 2E004, 2E005, 2E006, 2E007, 2E008, 2E009, 2E00A, 2E00B, 2E00C, 300A4, 00D00,
|
||||
00C00, 3C001, 30115, 300C3, 00120, 30091, 1400D, 35012, 14054, 3501E, 14041, 35037, 300ED, 35012, 30091, 14049,
|
||||
3541C, 30091, 1404D, 3541C, 30091, 14045, 3541C, 30091, 1400D, 3542C, 300A8, 34012, 14020, 3541C, 3006D, 35812,
|
||||
2E606, 2E507, 2E408, 2E004, 2E005, 300A8, 34012, 30091, 1404C, 3541C, 30091, 14041, 3541C, 30091, 14052, 3541C,
|
||||
30091, 1404D, 3541C, 30091, 1400D, 35448, 300AC, 34012, 14020, 3541C, 30091, 1404F, 35055, 1C101, 3006D, 35812,
|
||||
2E609, 2E50A, 2E40B, 300AC, 34012, 30091, 1404E, 35460, 30091, 1400D, 3541C, 0600C, 0C002, 2E00C, 300AC, 34012,
|
||||
14046, 3541C, 30091, 14046, 3541C, 30091, 1400D, 3541C, 00000, 2E00C, 300A4, 300AC, 34012, 301EC, 3588B, 01620,
|
||||
18101, 30091, 1403A, 3548B, 301EC, 3588B, 01520, 18101, 30091, 1403A, 3548B, 301EC, 3588B, 01420, 18101, 30091,
|
||||
1400D, 3548B, 14618, 35C8B, 1453C, 35C8B, 1443C, 35C8B, 00000, 2000E, 2A000, 30125, 300E7, 30134, 00001, 2000E,
|
||||
2A000, 07010, 301E2, 18101, 2A000, 04000, 12010, 3549A, 30185, 34095, 04F01, 3009D, 2A000, 04000, 12002, 350A2,
|
||||
30185, 3409D, 2CF01, 2A000, 0600C, 0A001, 2C000, 2A000, 00E06, 30160, 300BC, 2A000, 00E09, 30160, 300BC, 3013D,
|
||||
300E7, 0600C, 12001, 350B6, 30153, 2A000, 12002, 350BA, 3014E, 2A000, 30148, 2A000, 00120, 07F10, 3009D, 14F0D,
|
||||
2B000, 18101, 340BD, 00120, 01210, 18210, 04000, 12008, 354DB, 30095, 2FF10, 14F0D, 2B000, 14F08, 350D3, 18101,
|
||||
15120, 354C6, 300EA, 1C101, 14120, 358D9, 300E7, 300EA, 340C6, 30122, 340C3, 300E4, 2EF20, 300FA, 300E4, 04000,
|
||||
12010, 2B000, 04F01, 340DF, 00F0D, 3009D, 2A000, 00F20, 3009D, 2A000, 00F08, 3009D, 2A000, 00F53, 3009D, 00F79,
|
||||
3009D, 00F6E, 3009D, 00F74, 3009D, 00F61, 3009D, 00F78, 3009D, 3410A, 00F4F, 3009D, 00F76, 3009D, 00F65, 3009D,
|
||||
00F72, 3009D, 00F66, 3009D, 00F6C, 3009D, 00F6F, 3009D, 00F77, 3009D, 300E7, 00F45, 3009D, 00F72, 3009D, 3009D,
|
||||
00F6F, 3009D, 00F72, 3009D, 2A000, 300E4, 00F4B, 3009D, 00F43, 3009D, 00F50, 3009D, 00F53, 3009D, 00F4D, 3009D,
|
||||
00F33, 3009D, 00F3E, 3009D, 2A000, 00F49, 3009D, 00F6E, 3009D, 00F76, 3009D, 00F61, 3009D, 00F6C, 3009D, 00F69,
|
||||
3009D, 00F64, 3009D, 2A000, 00F54, 3009D, 00F69, 3009D, 00F6D, 3009D, 00F65, 3009D, 2A000, 00F41, 3009D, 00F6C,
|
||||
3009D, 00F61, 3009D, 00F72, 3009D, 00F6D, 3009D, 2A000, 00F4F, 3009D, 00F46, 3009D, 3009D, 2A000, 00F4F, 3009D,
|
||||
00F4E, 3009D, 2A000, 00F41, 3009D, 00F63, 3009D, 00F74, 3009D, 00F69, 3009D, 00F76, 3009D, 00F65, 3009D, 2A000,
|
||||
00220, 070E0, 3017E, 2F120, 18201, 2F020, 18201, 0003A, 2F020, 18201, 18E01, 070E0, 3017E, 2F120, 18201, 2F020,
|
||||
18201, 0003A, 2F020, 18201, 18E01, 070E0, 3017E, 2F120, 18201, 2F020, 18201, 0000D, 2F020, 2A000, 00130, 18101,
|
||||
1C00A, 35D7F, 1C101, 1803A, 2A000, 2E010, 2E111, 2E212, 2E313, 2E414, 2E515, 06200, 06301, 3C000, 2ED00, 2EC01,
|
||||
3C001, 06400, 06501, 1D420, 1F530, 06202, 06303, 19240, 1B350, 00000, 1C2E8, 1E303, 3599F, 18001, 3419A, 182E8,
|
||||
1A303, 2E202, 2E303, 06204, 06305, 19200, 1A300, 00000, 1C2E8, 1E303, 359AD, 18001, 341AF, 182E8, 1A303, 2E204,
|
||||
2E305, 06108, 19100, 1413C, 351B7, 2E108, 341C9, 00100, 2E108, 06107, 18101, 1413C, 351BF, 2E107, 341C9, 00100,
|
||||
2E107, 06106, 18101, 14118, 351C7, 2E106, 341C9, 00100, 2E106, 06006, 06109, 15010, 355DB, 06007, 0610A, 15010,
|
||||
355DB, 06008, 0610B, 15010, 355DB, 0600C, 12002, 351DB, 0C001, 2E00C, 300A4, 06010, 06111, 06212, 06313, 06414,
|
||||
06515, 2A000, 14061, 2B800, 1407B, 2BC00, 0A0DF, 2A000, 180C6, 2B800, 1C0F6, 2A000, 07010, 301E8, 2B800, 01200,
|
||||
20206, 20206, 19200, 20206, 18101, 07010, 301E8, 2B800, 19200, 2A000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 18D01, 1AC00, 38001, 343FC;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,69 @@
|
||||
function bits = fill_uclock_program_store()
|
||||
bits = [ ...
|
||||
0, 188416, 188417, 188418, 188419, 188420, 188421, 188422, 188423, 188424, 188425, 188426, 188427, 188428, 196772, 3328, ...
|
||||
3072, 245761, 196885, 196803, 288, 196753, 81933, 217106, 82004, 217118, 81985, 217143, 196845, 217106, 196753, 81993, ...
|
||||
218140, 196753, 81997, 218140, 196753, 81989, 218140, 196753, 81933, 218156, 196776, 213010, 81952, 218140, 196717, 219154, ...
|
||||
189958, 189703, 189448, 188420, 188421, 196776, 213010, 196753, 81996, 218140, 196753, 81985, 218140, 196753, 82002, 218140, ...
|
||||
196753, 81997, 218140, 196753, 81933, 218184, 196780, 213010, 81952, 218140, 196753, 81999, 217173, 114945, 196717, 219154, ...
|
||||
189961, 189706, 189451, 196780, 213010, 196753, 81998, 218208, 196753, 81933, 218140, 24588, 49154, 188428, 196780, 213010, ...
|
||||
81990, 218140, 196753, 81990, 218140, 196753, 81933, 218140, 0, 188428, 196772, 196780, 213010, 197100, 219275, 5664, ...
|
||||
98561, 196753, 81978, 218251, 197100, 219275, 5408, 98561, 196753, 81978, 218251, 197100, 219275, 5152, 98561, 196753, ...
|
||||
81933, 218251, 83480, 220299, 83260, 220299, 83004, 220299, 0, 131086, 172032, 196901, 196839, 196916, 1, 131086, ...
|
||||
172032, 28688, 197090, 98561, 172032, 16384, 73744, 218266, 196997, 213141, 20225, 196765, 172032, 16384, 73730, 217250, ...
|
||||
196997, 213149, 184065, 172032, 24588, 40961, 180224, 172032, 3590, 196960, 196796, 172032, 3593, 196960, 196796, 196925, ...
|
||||
196839, 24588, 73729, 217270, 196947, 172032, 73730, 217274, 196942, 172032, 196936, 172032, 288, 32528, 196765, 85773, ...
|
||||
176128, 98561, 213181, 288, 4624, 98832, 16384, 73736, 218331, 196757, 196368, 85773, 176128, 85768, 217299, 98561, ...
|
||||
86304, 218310, 196842, 114945, 82208, 219353, 196839, 196842, 213190, 196898, 213187, 196836, 192288, 196858, 196836, 16384, ...
|
||||
73744, 176128, 20225, 213215, 3853, 196765, 172032, 3872, 196765, 172032, 3848, 196765, 172032, 3923, 196765, 3961, ...
|
||||
196765, 3950, 196765, 3956, 196765, 3937, 196765, 3960, 196765, 213258, 3919, 196765, 3958, 196765, 3941, 196765, ...
|
||||
3954, 196765, 3942, 196765, 3948, 196765, 3951, 196765, 3959, 196765, 196839, 3909, 196765, 3954, 196765, 196765, ...
|
||||
3951, 196765, 3954, 196765, 172032, 196836, 3915, 196765, 3907, 196765, 3920, 196765, 3923, 196765, 3917, 196765, ...
|
||||
3891, 196765, 3902, 196765, 172032, 3913, 196765, 3950, 196765, 3958, 196765, 3937, 196765, 3948, 196765, 3945, ...
|
||||
196765, 3940, 196765, 172032, 3924, 196765, 3945, 196765, 3949, 196765, 3941, 196765, 172032, 3905, 196765, 3948, ...
|
||||
196765, 3937, 196765, 3954, 196765, 3949, 196765, 172032, 3919, 196765, 3910, 196765, 196765, 172032, 3919, 196765, ...
|
||||
3918, 196765, 172032, 3905, 196765, 3939, 196765, 3956, 196765, 3945, 196765, 3958, 196765, 3941, 196765, 172032, ...
|
||||
544, 28896, 196990, 192800, 98817, 192544, 98817, 58, 192544, 98817, 101889, 28896, 196990, 192800, 98817, 192544, ...
|
||||
98817, 58, 192544, 98817, 101889, 28896, 196990, 192800, 98817, 192544, 98817, 13, 192544, 172032, 304, 98561, ...
|
||||
114698, 220543, 114945, 98362, 172032, 188432, 188689, 188946, 189203, 189460, 189717, 25088, 25345, 245760, 191744, 191489, ...
|
||||
245761, 25600, 25857, 119840, 128304, 25090, 25347, 102976, 111440, 0, 115432, 123651, 219551, 98305, 213402, 99048, ...
|
||||
107267, 188930, 189187, 25092, 25349, 102912, 107264, 0, 115432, 123651, 219565, 98305, 213423, 99048, 107267, 188932, ...
|
||||
189189, 24840, 102656, 82236, 217527, 188680, 213449, 256, 188680, 24839, 98561, 82236, 217535, 188679, 213449, 256, ...
|
||||
188679, 24838, 98561, 82200, 217543, 188678, 213449, 256, 188678, 24582, 24841, 86032, 218587, 24583, 24842, 86032, ...
|
||||
218587, 24584, 24843, 86032, 218587, 24588, 73730, 217563, 49153, 188428, 196772, 24592, 24849, 25106, 25363, 25620, ...
|
||||
25877, 172032, 82017, 178176, 82043, 179200, 41183, 172032, 98502, 178176, 114934, 172032, 28688, 197096, 178176, 4608, ...
|
||||
131590, 131590, 102912, 131590, 98561, 28688, 197096, 178176, 102912, 172032, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101633, 109568, 229377, 214012, ...
|
||||
];
|
||||
|
||||
return;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,262 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2004 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: v1.30
|
||||
// \ \ Application : KCPSM3
|
||||
// / / Filename: uclock.v
|
||||
// /___/ /\
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Command: kcpsm3 uclock.psm
|
||||
//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs
|
||||
//Design Name: uclock
|
||||
//Generated 25Sep2005-15:52:57.
|
||||
//Purpose:
|
||||
// uclock verilog program definition.
|
||||
//
|
||||
//Reference:
|
||||
// PicoBlaze 8-bit Embedded Microcontroller User Guide
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1 ps / 1ps
|
||||
module uclock (address, instruction, clk);
|
||||
input [9:0] address;
|
||||
input clk;
|
||||
output [17:0] instruction;
|
||||
RAMB16_S18 ram_1024_x_18(
|
||||
.DI (16'h0000),
|
||||
.DIP (2'b00),
|
||||
.EN (1'b1),
|
||||
.WE (1'b0),
|
||||
.SSR (1'b0),
|
||||
.CLK (clk),
|
||||
.ADDR (address),
|
||||
.DO (instruction[15:0]),
|
||||
.DOP (instruction[17:16]))
|
||||
/*synthesis
|
||||
init_00 = "0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000"
|
||||
init_01 = "40490091501200ED50374041501E40545012400D0091012000C30115C0010C00"
|
||||
init_02 = "5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C"
|
||||
init_03 = "541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606"
|
||||
init_04 = "5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091"
|
||||
init_05 = "401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609"
|
||||
init_06 = "1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046"
|
||||
init_07 = "009181011420588B01EC548B403A009181011520588B01EC548B403A00918101"
|
||||
init_08 = "000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D"
|
||||
init_09 = "50A220024000A000009D4F0140950185549A20104000A000810101E27010A000"
|
||||
init_0A = "013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185"
|
||||
init_0B = "4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7"
|
||||
init_0C = "810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000"
|
||||
init_0D = "400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120"
|
||||
init_0E = "0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010"
|
||||
init_0F = "009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D"
|
||||
init_10 = "009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72"
|
||||
init_11 = "009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F"
|
||||
init_12 = "0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33"
|
||||
init_13 = "0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D"
|
||||
init_14 = "009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D"
|
||||
init_15 = "A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E"
|
||||
init_16 = "F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220"
|
||||
init_17 = "81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201"
|
||||
init_18 = "EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A"
|
||||
init_19 = "82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001"
|
||||
init_1A = "E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303"
|
||||
init_1B = "010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305"
|
||||
init_1C = "5010610A600755DB501061096006E106010041C9E10651C7411881016106E107"
|
||||
init_1D = "6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB"
|
||||
init_1E = "1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515"
|
||||
init_1F = "000000000000000000000000A0009200B80001E8701081010206920002060206"
|
||||
init_20 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_21 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_22 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_23 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_24 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_25 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_26 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_27 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_28 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_29 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2B = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2F = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_30 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_31 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_32 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_33 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_34 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_35 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_36 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_37 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_38 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_39 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3B = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3F = "43FC8001AC008D01000000000000000000000000000000000000000000000000"
|
||||
initp_00 = "D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8"
|
||||
initp_01 = "CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD"
|
||||
initp_02 = "4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC"
|
||||
initp_03 = "0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D"
|
||||
initp_04 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_05 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_06 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_07 = "F500000000000000000000000000000000000000000000000000000000000000" */;
|
||||
// synthesis translate_off
|
||||
// Attributes for Simulation
|
||||
defparam ram_1024_x_18.INIT_00 = 256'h0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000;
|
||||
defparam ram_1024_x_18.INIT_01 = 256'h40490091501200ED50374041501E40545012400D0091012000C30115C0010C00;
|
||||
defparam ram_1024_x_18.INIT_02 = 256'h5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C;
|
||||
defparam ram_1024_x_18.INIT_03 = 256'h541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606;
|
||||
defparam ram_1024_x_18.INIT_04 = 256'h5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091;
|
||||
defparam ram_1024_x_18.INIT_05 = 256'h401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609;
|
||||
defparam ram_1024_x_18.INIT_06 = 256'h1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046;
|
||||
defparam ram_1024_x_18.INIT_07 = 256'h009181011420588B01EC548B403A009181011520588B01EC548B403A00918101;
|
||||
defparam ram_1024_x_18.INIT_08 = 256'h000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D;
|
||||
defparam ram_1024_x_18.INIT_09 = 256'h50A220024000A000009D4F0140950185549A20104000A000810101E27010A000;
|
||||
defparam ram_1024_x_18.INIT_0A = 256'h013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185;
|
||||
defparam ram_1024_x_18.INIT_0B = 256'h4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7;
|
||||
defparam ram_1024_x_18.INIT_0C = 256'h810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000;
|
||||
defparam ram_1024_x_18.INIT_0D = 256'h400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120;
|
||||
defparam ram_1024_x_18.INIT_0E = 256'h0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010;
|
||||
defparam ram_1024_x_18.INIT_0F = 256'h009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D;
|
||||
defparam ram_1024_x_18.INIT_10 = 256'h009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72;
|
||||
defparam ram_1024_x_18.INIT_11 = 256'h009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F;
|
||||
defparam ram_1024_x_18.INIT_12 = 256'h0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33;
|
||||
defparam ram_1024_x_18.INIT_13 = 256'h0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D;
|
||||
defparam ram_1024_x_18.INIT_14 = 256'h009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D;
|
||||
defparam ram_1024_x_18.INIT_15 = 256'hA000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E;
|
||||
defparam ram_1024_x_18.INIT_16 = 256'hF0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220;
|
||||
defparam ram_1024_x_18.INIT_17 = 256'h81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201;
|
||||
defparam ram_1024_x_18.INIT_18 = 256'hEC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A;
|
||||
defparam ram_1024_x_18.INIT_19 = 256'h82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001;
|
||||
defparam ram_1024_x_18.INIT_1A = 256'hE204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303;
|
||||
defparam ram_1024_x_18.INIT_1B = 256'h010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305;
|
||||
defparam ram_1024_x_18.INIT_1C = 256'h5010610A600755DB501061096006E106010041C9E10651C7411881016106E107;
|
||||
defparam ram_1024_x_18.INIT_1D = 256'h6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB;
|
||||
defparam ram_1024_x_18.INIT_1E = 256'h1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515;
|
||||
defparam ram_1024_x_18.INIT_1F = 256'h000000000000000000000000A0009200B80001E8701081010206920002060206;
|
||||
defparam ram_1024_x_18.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3F = 256'h43FC8001AC008D01000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_00 = 256'hD3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8;
|
||||
defparam ram_1024_x_18.INITP_01 = 256'hCCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD;
|
||||
defparam ram_1024_x_18.INITP_02 = 256'h4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC;
|
||||
defparam ram_1024_x_18.INITP_03 = 256'h0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D;
|
||||
defparam ram_1024_x_18.INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_07 = 256'hF500000000000000000000000000000000000000000000000000000000000000;
|
||||
// synthesis translate_on
|
||||
// Attributes for XST (Synplicity attributes are in-line)
|
||||
// synthesis attribute INIT_00 of ram_1024_x_18 is "0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000"
|
||||
// synthesis attribute INIT_01 of ram_1024_x_18 is "40490091501200ED50374041501E40545012400D0091012000C30115C0010C00"
|
||||
// synthesis attribute INIT_02 of ram_1024_x_18 is "5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C"
|
||||
// synthesis attribute INIT_03 of ram_1024_x_18 is "541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606"
|
||||
// synthesis attribute INIT_04 of ram_1024_x_18 is "5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091"
|
||||
// synthesis attribute INIT_05 of ram_1024_x_18 is "401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609"
|
||||
// synthesis attribute INIT_06 of ram_1024_x_18 is "1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046"
|
||||
// synthesis attribute INIT_07 of ram_1024_x_18 is "009181011420588B01EC548B403A009181011520588B01EC548B403A00918101"
|
||||
// synthesis attribute INIT_08 of ram_1024_x_18 is "000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D"
|
||||
// synthesis attribute INIT_09 of ram_1024_x_18 is "50A220024000A000009D4F0140950185549A20104000A000810101E27010A000"
|
||||
// synthesis attribute INIT_0A of ram_1024_x_18 is "013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185"
|
||||
// synthesis attribute INIT_0B of ram_1024_x_18 is "4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7"
|
||||
// synthesis attribute INIT_0C of ram_1024_x_18 is "810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000"
|
||||
// synthesis attribute INIT_0D of ram_1024_x_18 is "400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120"
|
||||
// synthesis attribute INIT_0E of ram_1024_x_18 is "0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010"
|
||||
// synthesis attribute INIT_0F of ram_1024_x_18 is "009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D"
|
||||
// synthesis attribute INIT_10 of ram_1024_x_18 is "009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72"
|
||||
// synthesis attribute INIT_11 of ram_1024_x_18 is "009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F"
|
||||
// synthesis attribute INIT_12 of ram_1024_x_18 is "0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33"
|
||||
// synthesis attribute INIT_13 of ram_1024_x_18 is "0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D"
|
||||
// synthesis attribute INIT_14 of ram_1024_x_18 is "009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D"
|
||||
// synthesis attribute INIT_15 of ram_1024_x_18 is "A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E"
|
||||
// synthesis attribute INIT_16 of ram_1024_x_18 is "F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220"
|
||||
// synthesis attribute INIT_17 of ram_1024_x_18 is "81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201"
|
||||
// synthesis attribute INIT_18 of ram_1024_x_18 is "EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A"
|
||||
// synthesis attribute INIT_19 of ram_1024_x_18 is "82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001"
|
||||
// synthesis attribute INIT_1A of ram_1024_x_18 is "E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303"
|
||||
// synthesis attribute INIT_1B of ram_1024_x_18 is "010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305"
|
||||
// synthesis attribute INIT_1C of ram_1024_x_18 is "5010610A600755DB501061096006E106010041C9E10651C7411881016106E107"
|
||||
// synthesis attribute INIT_1D of ram_1024_x_18 is "6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB"
|
||||
// synthesis attribute INIT_1E of ram_1024_x_18 is "1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515"
|
||||
// synthesis attribute INIT_1F of ram_1024_x_18 is "000000000000000000000000A0009200B80001E8701081010206920002060206"
|
||||
// synthesis attribute INIT_20 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_21 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_22 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_23 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_24 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_25 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_26 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_27 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_28 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_29 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_30 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_31 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_32 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_33 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_34 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_35 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_36 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_37 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_38 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_39 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3F of ram_1024_x_18 is "43FC8001AC008D01000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_00 of ram_1024_x_18 is "D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8"
|
||||
// synthesis attribute INITP_01 of ram_1024_x_18 is "CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD"
|
||||
// synthesis attribute INITP_02 of ram_1024_x_18 is "4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC"
|
||||
// synthesis attribute INITP_03 of ram_1024_x_18 is "0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D"
|
||||
// synthesis attribute INITP_04 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_05 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_06 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_07 of ram_1024_x_18 is "F500000000000000000000000000000000000000000000000000000000000000"
|
||||
endmodule
|
||||
// END OF FILE uclock.v
|
||||
@@ -0,0 +1,274 @@
|
||||
--
|
||||
-- Definition of a single port ROM for KCPSM3 program defined by uclock.psm
|
||||
--
|
||||
-- Generated by KCPSM3 Assembler 25Sep2005-15:52:57.
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
--
|
||||
entity uclock is
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end uclock;
|
||||
--
|
||||
architecture low_level_definition of uclock is
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
-- The information is repeated in the generic map for functional simulation
|
||||
--
|
||||
attribute INIT_00 : string;
|
||||
attribute INIT_01 : string;
|
||||
attribute INIT_02 : string;
|
||||
attribute INIT_03 : string;
|
||||
attribute INIT_04 : string;
|
||||
attribute INIT_05 : string;
|
||||
attribute INIT_06 : string;
|
||||
attribute INIT_07 : string;
|
||||
attribute INIT_08 : string;
|
||||
attribute INIT_09 : string;
|
||||
attribute INIT_0A : string;
|
||||
attribute INIT_0B : string;
|
||||
attribute INIT_0C : string;
|
||||
attribute INIT_0D : string;
|
||||
attribute INIT_0E : string;
|
||||
attribute INIT_0F : string;
|
||||
attribute INIT_10 : string;
|
||||
attribute INIT_11 : string;
|
||||
attribute INIT_12 : string;
|
||||
attribute INIT_13 : string;
|
||||
attribute INIT_14 : string;
|
||||
attribute INIT_15 : string;
|
||||
attribute INIT_16 : string;
|
||||
attribute INIT_17 : string;
|
||||
attribute INIT_18 : string;
|
||||
attribute INIT_19 : string;
|
||||
attribute INIT_1A : string;
|
||||
attribute INIT_1B : string;
|
||||
attribute INIT_1C : string;
|
||||
attribute INIT_1D : string;
|
||||
attribute INIT_1E : string;
|
||||
attribute INIT_1F : string;
|
||||
attribute INIT_20 : string;
|
||||
attribute INIT_21 : string;
|
||||
attribute INIT_22 : string;
|
||||
attribute INIT_23 : string;
|
||||
attribute INIT_24 : string;
|
||||
attribute INIT_25 : string;
|
||||
attribute INIT_26 : string;
|
||||
attribute INIT_27 : string;
|
||||
attribute INIT_28 : string;
|
||||
attribute INIT_29 : string;
|
||||
attribute INIT_2A : string;
|
||||
attribute INIT_2B : string;
|
||||
attribute INIT_2C : string;
|
||||
attribute INIT_2D : string;
|
||||
attribute INIT_2E : string;
|
||||
attribute INIT_2F : string;
|
||||
attribute INIT_30 : string;
|
||||
attribute INIT_31 : string;
|
||||
attribute INIT_32 : string;
|
||||
attribute INIT_33 : string;
|
||||
attribute INIT_34 : string;
|
||||
attribute INIT_35 : string;
|
||||
attribute INIT_36 : string;
|
||||
attribute INIT_37 : string;
|
||||
attribute INIT_38 : string;
|
||||
attribute INIT_39 : string;
|
||||
attribute INIT_3A : string;
|
||||
attribute INIT_3B : string;
|
||||
attribute INIT_3C : string;
|
||||
attribute INIT_3D : string;
|
||||
attribute INIT_3E : string;
|
||||
attribute INIT_3F : string;
|
||||
attribute INITP_00 : string;
|
||||
attribute INITP_01 : string;
|
||||
attribute INITP_02 : string;
|
||||
attribute INITP_03 : string;
|
||||
attribute INITP_04 : string;
|
||||
attribute INITP_05 : string;
|
||||
attribute INITP_06 : string;
|
||||
attribute INITP_07 : string;
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
--
|
||||
attribute INIT_00 of ram_1024_x_18 : label is "0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000";
|
||||
attribute INIT_01 of ram_1024_x_18 : label is "40490091501200ED50374041501E40545012400D0091012000C30115C0010C00";
|
||||
attribute INIT_02 of ram_1024_x_18 : label is "5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C";
|
||||
attribute INIT_03 of ram_1024_x_18 : label is "541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606";
|
||||
attribute INIT_04 of ram_1024_x_18 : label is "5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091";
|
||||
attribute INIT_05 of ram_1024_x_18 : label is "401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609";
|
||||
attribute INIT_06 of ram_1024_x_18 : label is "1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046";
|
||||
attribute INIT_07 of ram_1024_x_18 : label is "009181011420588B01EC548B403A009181011520588B01EC548B403A00918101";
|
||||
attribute INIT_08 of ram_1024_x_18 : label is "000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D";
|
||||
attribute INIT_09 of ram_1024_x_18 : label is "50A220024000A000009D4F0140950185549A20104000A000810101E27010A000";
|
||||
attribute INIT_0A of ram_1024_x_18 : label is "013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185";
|
||||
attribute INIT_0B of ram_1024_x_18 : label is "4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7";
|
||||
attribute INIT_0C of ram_1024_x_18 : label is "810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000";
|
||||
attribute INIT_0D of ram_1024_x_18 : label is "400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120";
|
||||
attribute INIT_0E of ram_1024_x_18 : label is "0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010";
|
||||
attribute INIT_0F of ram_1024_x_18 : label is "009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D";
|
||||
attribute INIT_10 of ram_1024_x_18 : label is "009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72";
|
||||
attribute INIT_11 of ram_1024_x_18 : label is "009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F";
|
||||
attribute INIT_12 of ram_1024_x_18 : label is "0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33";
|
||||
attribute INIT_13 of ram_1024_x_18 : label is "0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D";
|
||||
attribute INIT_14 of ram_1024_x_18 : label is "009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D";
|
||||
attribute INIT_15 of ram_1024_x_18 : label is "A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E";
|
||||
attribute INIT_16 of ram_1024_x_18 : label is "F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220";
|
||||
attribute INIT_17 of ram_1024_x_18 : label is "81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201";
|
||||
attribute INIT_18 of ram_1024_x_18 : label is "EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A";
|
||||
attribute INIT_19 of ram_1024_x_18 : label is "82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001";
|
||||
attribute INIT_1A of ram_1024_x_18 : label is "E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303";
|
||||
attribute INIT_1B of ram_1024_x_18 : label is "010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305";
|
||||
attribute INIT_1C of ram_1024_x_18 : label is "5010610A600755DB501061096006E106010041C9E10651C7411881016106E107";
|
||||
attribute INIT_1D of ram_1024_x_18 : label is "6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB";
|
||||
attribute INIT_1E of ram_1024_x_18 : label is "1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515";
|
||||
attribute INIT_1F of ram_1024_x_18 : label is "000000000000000000000000A0009200B80001E8701081010206920002060206";
|
||||
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3F of ram_1024_x_18 : label is "43FC8001AC008D01000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_00 of ram_1024_x_18 : label is "D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8";
|
||||
attribute INITP_01 of ram_1024_x_18 : label is "CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD";
|
||||
attribute INITP_02 of ram_1024_x_18 : label is "4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC";
|
||||
attribute INITP_03 of ram_1024_x_18 : label is "0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D";
|
||||
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_07 of ram_1024_x_18 : label is "F500000000000000000000000000000000000000000000000000000000000000";
|
||||
--
|
||||
begin
|
||||
--
|
||||
--Instantiate the Xilinx primitive for a block RAM
|
||||
ram_1024_x_18: RAMB16_S18
|
||||
--synthesis translate_off
|
||||
--INIT values repeated to define contents for functional simulation
|
||||
generic map ( INIT_00 => X"0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000",
|
||||
INIT_01 => X"40490091501200ED50374041501E40545012400D0091012000C30115C0010C00",
|
||||
INIT_02 => X"5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C",
|
||||
INIT_03 => X"541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606",
|
||||
INIT_04 => X"5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091",
|
||||
INIT_05 => X"401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609",
|
||||
INIT_06 => X"1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046",
|
||||
INIT_07 => X"009181011420588B01EC548B403A009181011520588B01EC548B403A00918101",
|
||||
INIT_08 => X"000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D",
|
||||
INIT_09 => X"50A220024000A000009D4F0140950185549A20104000A000810101E27010A000",
|
||||
INIT_0A => X"013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185",
|
||||
INIT_0B => X"4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7",
|
||||
INIT_0C => X"810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000",
|
||||
INIT_0D => X"400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120",
|
||||
INIT_0E => X"0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010",
|
||||
INIT_0F => X"009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D",
|
||||
INIT_10 => X"009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72",
|
||||
INIT_11 => X"009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F",
|
||||
INIT_12 => X"0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33",
|
||||
INIT_13 => X"0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D",
|
||||
INIT_14 => X"009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D",
|
||||
INIT_15 => X"A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E",
|
||||
INIT_16 => X"F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220",
|
||||
INIT_17 => X"81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201",
|
||||
INIT_18 => X"EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A",
|
||||
INIT_19 => X"82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001",
|
||||
INIT_1A => X"E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303",
|
||||
INIT_1B => X"010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305",
|
||||
INIT_1C => X"5010610A600755DB501061096006E106010041C9E10651C7411881016106E107",
|
||||
INIT_1D => X"6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB",
|
||||
INIT_1E => X"1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515",
|
||||
INIT_1F => X"000000000000000000000000A0009200B80001E8701081010206920002060206",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"43FC8001AC008D01000000000000000000000000000000000000000000000000",
|
||||
INITP_00 => X"D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8",
|
||||
INITP_01 => X"CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD",
|
||||
INITP_02 => X"4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC",
|
||||
INITP_03 => X"0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D",
|
||||
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_07 => X"F500000000000000000000000000000000000000000000000000000000000000")
|
||||
--synthesis translate_on
|
||||
port map( DI => "0000000000000000",
|
||||
DIP => "00",
|
||||
EN => '1',
|
||||
WE => '0',
|
||||
SSR => '0',
|
||||
CLK => clk,
|
||||
ADDR => address,
|
||||
DO => instruction(15 downto 0),
|
||||
DOP => instruction(17 downto 16));
|
||||
--
|
||||
end low_level_definition;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE uclock.vhd
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
@@ -0,0 +1,3 @@
|
||||
copy %1.psm previous_%1.psm
|
||||
del %1.psm
|
||||
copy %1.fmt %1.psm
|
||||
@@ -0,0 +1,25 @@
|
||||
;Interrupt example
|
||||
;
|
||||
CONSTANT waveform_port, 02 ;bit0 will be data
|
||||
CONSTANT counter_port, 04
|
||||
CONSTANT pattern_10101010, AA
|
||||
NAMEREG sA, interrupt_counter
|
||||
;
|
||||
start: LOAD interrupt_counter, 00 ;reset interrupt counter
|
||||
LOAD s2, pattern_10101010 ;initial output condition
|
||||
ENABLE INTERRUPT
|
||||
;
|
||||
drive_wave: OUTPUT s2, waveform_port
|
||||
LOAD s0, 07 ;delay size
|
||||
loop: SUB s0, 01 ;delay loop
|
||||
JUMP NZ, loop
|
||||
XOR s2, FF ;toggle waveform
|
||||
JUMP drive_wave
|
||||
;
|
||||
ADDRESS 2B0
|
||||
int_routine: ADD interrupt_counter, 01 ;increment counter
|
||||
OUTPUT interrupt_counter, counter_port
|
||||
RETURNI ENABLE
|
||||
;
|
||||
ADDRESS 3FF ;set interrupt vector
|
||||
JUMP int_routine
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,458 @@
|
||||
UART9 readme.txt
|
||||
|
||||
Please open this file in Notepad or WordPad or use a non proportional font for best display format.
|
||||
|
||||
|
||||
|
||||
9-Bit UART Macros with Integral FIFO Buffers.
|
||||
Suitable for communication with Parity.
|
||||
|
||||
|
||||
Release 1 - 3rd March 2005
|
||||
|
||||
|
||||
|
||||
|
||||
Author
|
||||
------
|
||||
|
||||
Ken Chapman
|
||||
Staff Engineer - Spartan Applications Specialist
|
||||
Xilinx Ltd (UK)
|
||||
|
||||
email: ken.chapman@xilinx.com
|
||||
|
||||
|
||||
Introduction
|
||||
------------
|
||||
|
||||
These macros have been supplied to complement the standard 8-bit UART macros supplied with PicoBlaze.
|
||||
You are advised to look at the standard macros and documentation (UART_manual.pdf) first as these
|
||||
variants take almost the same format and must be used and controlled in the same fundamental way.
|
||||
|
||||
The UART9 macros provide a UART which has 1 start bit, 9 data bits and 1 stop bit.
|
||||
The additional data bit can be used to provide different functionality depending on the way you
|
||||
choose to interpret it.
|
||||
|
||||
Transmitter macro is called 'uart9_tx.vhd' and the additional bit is data_in(8).
|
||||
Receiver macro is called 'uart9_rx.vhd' and the additional bit is data_out(8).
|
||||
|
||||
Parity - Drive data_in(8) with a High or Low depending on the state or the remaining data bits
|
||||
data_in(7 downto 0) and the desired ODD or EVEN parity.
|
||||
Interpret and check the received data_out(8) as required by your application.
|
||||
|
||||
Data - The additional bit can be used as an additional data bit.
|
||||
|
||||
Stop bit - Forcing a High and checking for High allows the UART to provide 1 start bit, 8 data
|
||||
bits and 2 stop bits format.
|
||||
|
||||
|
||||
Is Parity Required?
|
||||
-------------------
|
||||
|
||||
The most common reason for the 9th bit is to provide support for parity. Before choosing to
|
||||
implement parity in a system you should ask the fundamental question "Do I really need it?".
|
||||
To help answer that question, you need to consider what your system will do if a parity error
|
||||
should occur. Will it just ignore an error and what will be the effect if it does? If it
|
||||
does not ignore the error, then what will it do? All of these factors will need to be solved
|
||||
at a higher level than these macros and PicoBlaze will almost certainly provide a suitable
|
||||
platform in which to implement this protocol.
|
||||
|
||||
In many cases the need for parity is simply to enable connection to another piece of equipment
|
||||
which expects parity and which can not be changed. It is not unusual in these cases for the received
|
||||
parity to be ignored or for incorrect data to be discarded with unpredictable results. Fortunately
|
||||
most serial connections such as RS232 are now very reliable once initial communication has
|
||||
been established.
|
||||
|
||||
|
||||
|
||||
Using the Macros
|
||||
----------------
|
||||
|
||||
The macros are provided as source VHDL and should be instantiated in your design. Each macro
|
||||
also uses two sub macros and therefore these files must also be added to the project.
|
||||
|
||||
uart9_tx
|
||||
|
|
||||
|__kcuart9_tx
|
||||
|
|
||||
|__bbfifo_16x9
|
||||
|
||||
|
||||
uart9_rx
|
||||
|
|
||||
|__kcuart9_rx
|
||||
|
|
||||
|__bbfifo_16x9
|
||||
|
||||
|
||||
The instantiation templates are exactly the same as those required for the standard 8-bit
|
||||
macros except that the data bus in each case is now 9 bits.
|
||||
|
||||
|
||||
Component declaration........
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
component uart9_tx
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
|
||||
|
||||
component uart9_rx
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
Component Instantiation......
|
||||
|
||||
Signal names will probably change to fit with your design.
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
transmit: uart9_tx
|
||||
port map ( data_in => data_in,
|
||||
write_buffer => write_buffer,
|
||||
reset_buffer => reset_buffer,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => serial_out,
|
||||
buffer_full => buffer_full,
|
||||
buffer_half_full => buffer_half_full,
|
||||
clk => clk );
|
||||
|
||||
receive: uart9_rx
|
||||
port map ( serial_in => serial_in,
|
||||
data_out => data_out
|
||||
read_buffer => read_buffer
|
||||
reset_buffer => reset_buffer,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
buffer_data_present => buffer_data_present,
|
||||
buffer_full => buffer_full,
|
||||
buffer_half_full => buffer_half_full,
|
||||
clk => clk );
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Providing Parity
|
||||
----------------
|
||||
|
||||
Parity is defined as being ODD or EVEN. The term ODD and EVEN refers to the total number of
|
||||
High (1) bits being transmitted including the parity bit itself.
|
||||
|
||||
For example the ASCII code for the letter 'A' is 41 hex. The 8-bit binary representation is
|
||||
therefore 01000001 which clearly has an even number of 1's. So the parity bit will High (1)
|
||||
for ODD parity and '0' for EVEN parity.
|
||||
|
||||
To transmit parity using the uart9_tx macro, the parity bit needs to be computed and then
|
||||
applied along with the 8 data bits when activating the write_buffer control. This could be
|
||||
achieved in hardware by creating an XOR gate for EVEN parity or an XNOR for ODD parity.
|
||||
|
||||
--ODD parity
|
||||
data_in(8) <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(3)
|
||||
xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(7);
|
||||
|
||||
PicoBlaze can also be used to calculate parity and may offer additional flexibility.
|
||||
Since the ports and operation of PicoBlaze is 8-bits, connections to the uart_tx now
|
||||
requires 2 ports. The first port can be used to provide the parity bit which will then
|
||||
be held in a register. Then when the second port writes the main 8-bit data directly
|
||||
into the FIFO buffer the parity bit is combined to form the complete 9-bit value. By
|
||||
careful design the spare bits of the port used to set the parity bits can also be used
|
||||
for control the reset on the UART FIFO buffers if required.
|
||||
|
||||
When receiving data, hardware logic could again be used to compute the parity of the data
|
||||
and compare this with the received parity bit (XNOR gate). This would result in a
|
||||
'parity error' flag which the associated processor would still need to read. So unless
|
||||
the processor is really very occupied, it is probably easier and more efficient to read
|
||||
the parity bit directly and perform the error test in software.
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
PicoBlaze interface to uart9_tx and uart_rx supporting parity.
|
||||
|
||||
The following sections of code describe a potential interface between PicoBlaze and the
|
||||
uart9 macros. Notice how the FIFO buffers are fully controlled and monitored by the
|
||||
Processor and the parity bit is treated as bit7 of allocated input and output ports.
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
signal rx_data : std_logic_vector(8 downto 0);
|
||||
signal tx_data : std_logic_vector(8 downto 0);
|
||||
signal tx_parity : std_logic;
|
||||
signal write_to_uart : std_logic;
|
||||
signal tx_full : std_logic;
|
||||
signal tx_half_full : std_logic;
|
||||
signal read_from_uart : std_logic;
|
||||
signal rx_data_present : std_logic;
|
||||
signal rx_full : std_logic;
|
||||
signal rx_half_full : std_logic;
|
||||
signal uart_status : std_logic_vector(7 downto 0);
|
||||
signal tx_reset : std_logic;
|
||||
signal rx_reset : std_logic;
|
||||
|
||||
...............
|
||||
|
||||
--UART Transmitter interface
|
||||
|
||||
parity_tx_port: process(clk)
|
||||
begin
|
||||
|
||||
if clk'event and clk='1' then
|
||||
if write_strobe='1' then
|
||||
|
||||
-- PORT 20 : UART FIFO control and transmitter parity.
|
||||
if port_id(5)='1' then
|
||||
tx_reset <= out_port(0);
|
||||
rx_reset <= out_port(1);
|
||||
tx_parity <= out_port(7);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process parity_tx_port;
|
||||
|
||||
-- PORT 10 : Write data to UART transmitter.
|
||||
write_to_uart <= write_strobe and port_id(4);
|
||||
|
||||
tx_data <= tx_parity & out_port;
|
||||
|
||||
transmit: uart9_tx
|
||||
port map ( data_in => tx_data,
|
||||
write_buffer => write_to_uart,
|
||||
reset_buffer => reset_buffer,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => serial_out,
|
||||
buffer_full => buffer_full,
|
||||
buffer_half_full => buffer_half_full,
|
||||
clk => clk );
|
||||
|
||||
...............
|
||||
|
||||
--UART Receiver interface
|
||||
|
||||
input_ports: process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
|
||||
case port_id(1 downto 0) is
|
||||
|
||||
--PORT 00 : Read FIFO status including receiver parity bit
|
||||
when "00" => in_port <= uart_status;
|
||||
|
||||
--PORT 01 : Read receiver UART
|
||||
when "01" => in_port <= rx_data(7 downto 0);
|
||||
|
||||
--PORT 02 - if required
|
||||
--when "10" => in_port <= ?????;
|
||||
|
||||
--PORT 03 - if required
|
||||
--when "11" => in_port <= ?????;
|
||||
|
||||
-- Don't care used to ensure minimum logic
|
||||
when others => in_port <= "XXXXXXXX";
|
||||
|
||||
end case;
|
||||
|
||||
-- Form read strobe for UART receiver FIFO buffer for address 01.
|
||||
|
||||
read_from_uart <= read_strobe and (not port_id(1)) and port_id(0);
|
||||
|
||||
end if;
|
||||
|
||||
receive: uart9_rx
|
||||
port map ( serial_in => rx,
|
||||
data_out => rx_data,
|
||||
read_buffer => read_from_uart,
|
||||
reset_buffer => rx_reset,
|
||||
en_16_x_baud => en_38400_baud,
|
||||
buffer_data_present => rx_data_present,
|
||||
buffer_full => rx_full,
|
||||
buffer_half_full => rx_half_full,
|
||||
clk => clk );
|
||||
|
||||
|
||||
uart_status <= rx_data(8) & "00" & rx_full & rx_half_full & rx_data_present & tx_full & tx_half_full ;
|
||||
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
PicoBlaze to uart9_tx PSM code example
|
||||
|
||||
The following sections of PSM code relate to the VHDL interface above and enable a byte
|
||||
of data to be transmitted or received via the UART including parity. CONSTANT directives
|
||||
have been used to define both the port numbers and the allocations of bits within a given
|
||||
port.
|
||||
|
||||
The parity generation is performed by the TEST instruction. It is vital that the
|
||||
transmitter code (UART_write) sets the parity output port first and then writes the
|
||||
actual data. The receiver code (UART_read) captures the received parity as part of the
|
||||
polling of the FIFO status bits. It then reads the data, computes parity and compares this
|
||||
with the received bit. The ZERO flag (Z) indicates any parity errors which can then be
|
||||
used at the higher level in the program.
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
CONSTANT UART_write_port, 10 ;UART Tx 8-bit data output
|
||||
;
|
||||
CONSTANT UART_control_port, 20 ;UART reset and parity output
|
||||
CONSTANT tx_reset, 01 ; Tx Buffer Reset - bit0
|
||||
CONSTANT rx_reset, 02 ; Rx Buffer Reset - bit1
|
||||
CONSTANT tx_parity, 80 ; Tx Parity - bit7
|
||||
;
|
||||
CONSTANT UART_status_port, 00 ;Communications status input
|
||||
CONSTANT tx_half_full, 01 ; Transmitter half full - bit0
|
||||
CONSTANT tx_full, 02 ; UART FIFO full - bit1
|
||||
CONSTANT rx_data_present, 04 ; Receiver data present - bit2
|
||||
CONSTANT rx_half_full, 08 ; UART FIFO half full - bit3
|
||||
CONSTANT rx_full, 10 ; full - bit4
|
||||
CONSTANT status_nul5, 20 ; unused - bit5
|
||||
CONSTANT status_nul6, 40 ; unused - bit6
|
||||
CONSTANT rx_parity, 80 ; Parity Bit parity - bit7
|
||||
;
|
||||
CONSTANT UART_read_port, 01 ;UART Rx 8-bit data input
|
||||
;
|
||||
|
||||
NAMEREG sF, UART_data ;used for main 8-bit UART data
|
||||
NAMEREG sE, UART_status ;used for UART status and control
|
||||
;
|
||||
|
||||
;
|
||||
;Write byte to UART with EVEN or ODD parity.
|
||||
;
|
||||
;Data should be provided in register 'UART_data'
|
||||
;
|
||||
;Odd and even Parity is describes the total number of 1's sent
|
||||
;in the complete 9-bit packet formed of 8-bit data and the parity bit.
|
||||
;For EVEN parity comment out the line indicated ***.
|
||||
;For ODD parity include the line indicated ***.
|
||||
;
|
||||
;Registers used s0, UART_data and UART_status
|
||||
;
|
||||
UART_write: INPUT UART_status, UART_status_port
|
||||
TEST UART_status, tx_full ;test for space in buffer
|
||||
JUMP NZ, UART_write ;wait if no space
|
||||
LOAD s0, 00 ;compute parity for data being sent
|
||||
TEST UART_data, FF
|
||||
SRA s0 ;move parity value into MSB
|
||||
XOR s0, 80 ;**** include this line for ODD parity
|
||||
OUTPUT s0, UART_control_port ;send parity to UART (no reset)
|
||||
OUTPUT UART_data, UART_write_port ;write data and parity into transmitter
|
||||
RETURN
|
||||
;
|
||||
|
||||
|
||||
;Read byte from UART with test for EVEN or ODD parity.
|
||||
;
|
||||
;The routine tests and waits for available data and then reads the byte
|
||||
;data into register 'UART_data'. The data is then tested against the parity
|
||||
;bit received. For good data the ZERO flag will be set. A parity error will
|
||||
;will be signified by the ZERO flag being reset.
|
||||
;
|
||||
;Odd and even Parity is describes the total number of 1's sent
|
||||
;in the complete 9-bit packet formed of 8-bit data and the parity bit.
|
||||
;For EVEN parity comment out the line indicated ***.
|
||||
;For ODD parity include the line indicated ***.
|
||||
;
|
||||
;Registers used s0, UART_data and UART_status
|
||||
;
|
||||
;
|
||||
UART_read: INPUT UART_status, UART_status_port ;Test for available character
|
||||
TEST UART_status, rx_data_present ;test for space in buffer
|
||||
INPUT UART_data, UART_read_port
|
||||
LOAD s0, 00 ;compute parity for received data
|
||||
TEST UART_data, FF
|
||||
SRA s0
|
||||
XOR s0, 80 ;****include this line for ODD parity
|
||||
AND UART_status, rx_parity ;isolate parity bit received
|
||||
XOR s0, UART_status ;ZERO set if parity matches
|
||||
RETURN
|
||||
;
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Simple Error Correction Technique
|
||||
---------------------------------
|
||||
|
||||
This is a very old technique which can provide a degree of error correction. Although a
|
||||
parity error can indicate that an error has occurred, it is not possible to know which bit
|
||||
has been received in error. This technique can be used to detect and correct the occasional
|
||||
bit error.
|
||||
|
||||
In this example we assume that 8 bytes of data are to be sent. These are the ASCII characters
|
||||
ABCDEFGH. First each byte is transmitted with ODD parity (although EVEN could also be used).
|
||||
|
||||
A 0 1 0 0 0 0 0 1 1
|
||||
B 0 1 0 0 0 0 1 0 1
|
||||
C 0 1 0 0 0 0 1 1 0
|
||||
D 0 1 0 0 0 1 0 0 1
|
||||
E 0 1 0 0 0 1 0 1 0
|
||||
F 0 1 0 0 0 1 1 0 0
|
||||
G 0 1 0 0 0 1 1 1 1
|
||||
H 0 1 0 0 0 1 0 0 1
|
||||
|
||||
Next a 'parity byte' is transmitted. Each bit represents the ODD parity of the corresponding bit
|
||||
transmitted in the last 8 bytes. In other words, it is the ODD parity associated with each of
|
||||
the above columns.
|
||||
|
||||
1 1 1 1 1 0 1 1 *
|
||||
|
||||
It is debatable as to what to transmit as parity for this 'parity byte'. It could just be the
|
||||
parity of the 'parity byte' in the normal way. It could be the parity of the previous 8 parity
|
||||
bits transmitted or a combination of both. The uart9 macros allow you to make the choice in
|
||||
software because it is treated the same way as any other data bit.
|
||||
|
||||
|
||||
Now consider receiving the above data packet, but with a bit error at bit 6 of the character 'D'.
|
||||
|
||||
A 0 1 0 0 0 0 0 1 1
|
||||
B 0 1 0 0 0 0 1 0 1
|
||||
C 0 1 0 0 0 0 1 1 0
|
||||
D 0 0 0 0 0 1 0 0 1 <----- Parity error
|
||||
E 0 1 0 0 0 1 0 1 0
|
||||
F 0 1 0 0 0 1 1 0 0
|
||||
G 0 1 0 0 0 1 1 1 1
|
||||
H 0 1 0 0 0 1 0 0 1
|
||||
1 1 1 1 1 0 1 1 *
|
||||
|
||||
^
|
||||
|
|
||||
parity
|
||||
error
|
||||
|
||||
The parity error on the 'D' line tells us there has been some kind of error but we do not know
|
||||
which bit caused it. The 'parity byte' also indicates that an error has occurred in the bit 6
|
||||
column, but we don't know which byte was the cause. However, it can easily be seen that the
|
||||
intersection of these error points reveals the bit error and it would therefore be reasonable
|
||||
to correct this bit by simple inversion.
|
||||
|
||||
It is possible to correct more than one bit error in a packet so long as the errors occur in
|
||||
different rows and columns. There is always a danger that the parity bits may be corrupted and
|
||||
this is where the parity of the 'parity byte' (*) could benefit from being the computation of
|
||||
all 16 parity bits.
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
End of file UART9_readme.txt
|
||||
-----------------------------------------------------------------------------------------------
|
||||
@@ -0,0 +1,458 @@
|
||||
UART9 readme.txt
|
||||
|
||||
Please open this file in Notepad or WordPad or use a non proportional font for best display format.
|
||||
|
||||
|
||||
|
||||
9-Bit UART Macros with Integral FIFO Buffers.
|
||||
Suitable for communication with Parity.
|
||||
|
||||
|
||||
Release 1 - 3rd March 2005
|
||||
|
||||
|
||||
|
||||
|
||||
Author
|
||||
------
|
||||
|
||||
Ken Chapman
|
||||
Staff Engineer - Spartan Applications Specialist
|
||||
Xilinx Ltd (UK)
|
||||
|
||||
email: ken.chapman@xilinx.com
|
||||
|
||||
|
||||
Introduction
|
||||
------------
|
||||
|
||||
These macros have been supplied to complement the standard 8-bit UART macros supplied with PicoBlaze.
|
||||
You are advised to look at the standard macros and documentation (UART_manual.pdf) first as these
|
||||
variants take almost the same format and must be used and controlled in the same fundamental way.
|
||||
|
||||
The UART9 macros provide a UART which has 1 start bit, 9 data bits and 1 stop bit.
|
||||
The additional data bit can be used to provide different functionality depending on the way you
|
||||
choose to interpret it.
|
||||
|
||||
Transmitter macro is called 'uart9_tx.vhd' and the additional bit is data_in(8).
|
||||
Receiver macro is called 'uart9_rx.vhd' and the additional bit is data_out(8).
|
||||
|
||||
Parity - Drive data_in(8) with a High or Low depending on the state or the remaining data bits
|
||||
data_in(7 downto 0) and the desired ODD or EVEN parity.
|
||||
Interpret and check the received data_out(8) as required by your application.
|
||||
|
||||
Data - The additional bit can be used as an additional data bit.
|
||||
|
||||
Stop bit - Forcing a High and checking for High allows the UART to provide 1 start bit, 8 data
|
||||
bits and 2 stop bits format.
|
||||
|
||||
|
||||
Is Parity Required?
|
||||
-------------------
|
||||
|
||||
The most common reason for the 9th bit is to provide support for parity. Before choosing to
|
||||
implement parity in a system you should ask the fundamental question "Do I really need it?".
|
||||
To help answer that question, you need to consider what your system will do if a parity error
|
||||
should occur. Will it just ignore an error and what will be the effect if it does? If it
|
||||
does not ignore the error, then what will it do? All of these factors will need to be solved
|
||||
at a higher level than these macros and PicoBlaze will almost certainly provide a suitable
|
||||
platform in which to implement this protocol.
|
||||
|
||||
In many cases the need for parity is simply to enable connection to another piece of equipment
|
||||
which expects parity and which can not be changed. It is not unusual in these cases for the received
|
||||
parity to be ignored or for incorrect data to be discarded with unpredictable results. Fortunately
|
||||
most serial connections such as RS232 are now very reliable once initial communication has
|
||||
been established.
|
||||
|
||||
|
||||
|
||||
Using the Macros
|
||||
----------------
|
||||
|
||||
The macros are provided as source VHDL and should be instantiated in your design. Each macro
|
||||
also uses two sub macros and therefore these files must also be added to the project.
|
||||
|
||||
uart9_tx
|
||||
|
|
||||
|__kcuart9_tx
|
||||
|
|
||||
|__bbfifo_16x9
|
||||
|
||||
|
||||
uart9_rx
|
||||
|
|
||||
|__kcuart9_rx
|
||||
|
|
||||
|__bbfifo_16x9
|
||||
|
||||
|
||||
The instantiation templates are exactly the same as those required for the standard 8-bit
|
||||
macros except that the data bus in each case is now 9 bits.
|
||||
|
||||
|
||||
Component declaration........
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
component uart9_tx
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
|
||||
|
||||
component uart9_rx
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
Component Instantiation......
|
||||
|
||||
Signal names will probably change to fit with your design.
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
transmit: uart9_tx
|
||||
port map ( data_in => data_in,
|
||||
write_buffer => write_buffer,
|
||||
reset_buffer => reset_buffer,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => serial_out,
|
||||
buffer_full => buffer_full,
|
||||
buffer_half_full => buffer_half_full,
|
||||
clk => clk );
|
||||
|
||||
receive: uart9_rx
|
||||
port map ( serial_in => serial_in,
|
||||
data_out => data_out
|
||||
read_buffer => read_buffer
|
||||
reset_buffer => reset_buffer,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
buffer_data_present => buffer_data_present,
|
||||
buffer_full => buffer_full,
|
||||
buffer_half_full => buffer_half_full,
|
||||
clk => clk );
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Providing Parity
|
||||
----------------
|
||||
|
||||
Parity is defined as being ODD or EVEN. The term ODD and EVEN refers to the total number of
|
||||
High (1) bits being transmitted including the parity bit itself.
|
||||
|
||||
For example the ASCII code for the letter 'A' is 41 hex. The 8-bit binary representation is
|
||||
therefore 01000001 which clearly has an even number of 1's. So the parity bit will High (1)
|
||||
for ODD parity and '0' for EVEN parity.
|
||||
|
||||
To transmit parity using the uart9_tx macro, the parity bit needs to be computed and then
|
||||
applied along with the 8 data bits when activating the write_buffer control. This could be
|
||||
achieved in hardware by creating an XOR gate for EVEN parity or an XNOR for ODD parity.
|
||||
|
||||
--ODD parity
|
||||
data_in(8) <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(3)
|
||||
xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(7);
|
||||
|
||||
PicoBlaze can also be used to calculate parity and may offer additional flexibility.
|
||||
Since the ports and operation of PicoBlaze is 8-bits, connections to the uart_tx now
|
||||
requires 2 ports. The first port can be used to provide the parity bit which will then
|
||||
be held in a register. Then when the second port writes the main 8-bit data directly
|
||||
into the FIFO buffer the parity bit is combined to form the complete 9-bit value. By
|
||||
careful design the spare bits of the port used to set the parity bits can also be used
|
||||
for control the reset on the UART FIFO buffers if required.
|
||||
|
||||
When receiving data, hardware logic could again be used to compute the parity of the data
|
||||
and compare this with the received parity bit (XNOR gate). This would result in a
|
||||
'parity error' flag which the associated processor would still need to read. So unless
|
||||
the processor is really very occupied, it is probably easier and more efficient to read
|
||||
the parity bit directly and perform the error test in software.
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
PicoBlaze interface to uart9_tx and uart_rx supporting parity.
|
||||
|
||||
The following sections of code describe a potential interface between PicoBlaze and the
|
||||
uart9 macros. Notice how the FIFO buffers are fully controlled and monitored by the
|
||||
Processor and the parity bit is treated as bit7 of allocated input and output ports.
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
signal rx_data : std_logic_vector(8 downto 0);
|
||||
signal tx_data : std_logic_vector(8 downto 0);
|
||||
signal tx_parity : std_logic;
|
||||
signal write_to_uart : std_logic;
|
||||
signal tx_full : std_logic;
|
||||
signal tx_half_full : std_logic;
|
||||
signal read_from_uart : std_logic;
|
||||
signal rx_data_present : std_logic;
|
||||
signal rx_full : std_logic;
|
||||
signal rx_half_full : std_logic;
|
||||
signal uart_status : std_logic_vector(7 downto 0);
|
||||
signal tx_reset : std_logic;
|
||||
signal rx_reset : std_logic;
|
||||
|
||||
...............
|
||||
|
||||
--UART Transmitter interface
|
||||
|
||||
parity_tx_port: process(clk)
|
||||
begin
|
||||
|
||||
if clk'event and clk='1' then
|
||||
if write_strobe='1' then
|
||||
|
||||
-- PORT 20 : UART FIFO control and transmitter parity.
|
||||
if port_id(5)='1' then
|
||||
tx_reset <= out_port(0);
|
||||
rx_reset <= out_port(1);
|
||||
tx_parity <= out_port(7);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process parity_tx_port;
|
||||
|
||||
-- PORT 10 : Write data to UART transmitter.
|
||||
write_to_uart <= write_strobe and port_id(4);
|
||||
|
||||
tx_data <= tx_parity & out_port;
|
||||
|
||||
transmit: uart9_tx
|
||||
port map ( data_in => tx_data,
|
||||
write_buffer => write_to_uart,
|
||||
reset_buffer => reset_buffer,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => serial_out,
|
||||
buffer_full => buffer_full,
|
||||
buffer_half_full => buffer_half_full,
|
||||
clk => clk );
|
||||
|
||||
...............
|
||||
|
||||
--UART Receiver interface
|
||||
|
||||
input_ports: process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
|
||||
case port_id(1 downto 0) is
|
||||
|
||||
--PORT 00 : Read FIFO status including receiver parity bit
|
||||
when "00" => in_port <= uart_status;
|
||||
|
||||
--PORT 01 : Read receiver UART
|
||||
when "01" => in_port <= rx_data(7 downto 0);
|
||||
|
||||
--PORT 02 - if required
|
||||
--when "10" => in_port <= ?????;
|
||||
|
||||
--PORT 03 - if required
|
||||
--when "11" => in_port <= ?????;
|
||||
|
||||
-- Don't care used to ensure minimum logic
|
||||
when others => in_port <= "XXXXXXXX";
|
||||
|
||||
end case;
|
||||
|
||||
-- Form read strobe for UART receiver FIFO buffer for address 01.
|
||||
|
||||
read_from_uart <= read_strobe and (not port_id(1)) and port_id(0);
|
||||
|
||||
end if;
|
||||
|
||||
receive: uart9_rx
|
||||
port map ( serial_in => rx,
|
||||
data_out => rx_data,
|
||||
read_buffer => read_from_uart,
|
||||
reset_buffer => rx_reset,
|
||||
en_16_x_baud => en_38400_baud,
|
||||
buffer_data_present => rx_data_present,
|
||||
buffer_full => rx_full,
|
||||
buffer_half_full => rx_half_full,
|
||||
clk => clk );
|
||||
|
||||
|
||||
uart_status <= rx_data(8) & "00" & rx_full & rx_half_full & rx_data_present & tx_full & tx_half_full ;
|
||||
|
||||
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
PicoBlaze to uart9_tx PSM code example
|
||||
|
||||
The following sections of PSM code relate to the VHDL interface above and enable a byte
|
||||
of data to be transmitted or received via the UART including parity. CONSTANT directives
|
||||
have been used to define both the port numbers and the allocations of bits within a given
|
||||
port.
|
||||
|
||||
The parity generation is performed by the TEST instruction. It is vital that the
|
||||
transmitter code (UART_write) sets the parity output port first and then writes the
|
||||
actual data. The receiver code (UART_read) captures the received parity as part of the
|
||||
polling of the FIFO status bits. It then reads the data, computes parity and compares this
|
||||
with the received bit. The ZERO flag (Z) indicates any parity errors which can then be
|
||||
used at the higher level in the program.
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
CONSTANT UART_write_port, 10 ;UART Tx 8-bit data output
|
||||
;
|
||||
CONSTANT UART_control_port, 20 ;UART reset and parity output
|
||||
CONSTANT tx_reset, 01 ; Tx Buffer Reset - bit0
|
||||
CONSTANT rx_reset, 02 ; Rx Buffer Reset - bit1
|
||||
CONSTANT tx_parity, 80 ; Tx Parity - bit7
|
||||
;
|
||||
CONSTANT UART_status_port, 00 ;Communications status input
|
||||
CONSTANT tx_half_full, 01 ; Transmitter half full - bit0
|
||||
CONSTANT tx_full, 02 ; UART FIFO full - bit1
|
||||
CONSTANT rx_data_present, 04 ; Receiver data present - bit2
|
||||
CONSTANT rx_half_full, 08 ; UART FIFO half full - bit3
|
||||
CONSTANT rx_full, 10 ; full - bit4
|
||||
CONSTANT status_nul5, 20 ; unused - bit5
|
||||
CONSTANT status_nul6, 40 ; unused - bit6
|
||||
CONSTANT rx_parity, 80 ; Parity Bit parity - bit7
|
||||
;
|
||||
CONSTANT UART_read_port, 01 ;UART Rx 8-bit data input
|
||||
;
|
||||
|
||||
NAMEREG sF, UART_data ;used for main 8-bit UART data
|
||||
NAMEREG sE, UART_status ;used for UART status and control
|
||||
;
|
||||
|
||||
;
|
||||
;Write byte to UART with EVEN or ODD parity.
|
||||
;
|
||||
;Data should be provided in register 'UART_data'
|
||||
;
|
||||
;Odd and even Parity is describes the total number of 1's sent
|
||||
;in the complete 9-bit packet formed of 8-bit data and the parity bit.
|
||||
;For EVEN parity comment out the line indicated ***.
|
||||
;For ODD parity include the line indicated ***.
|
||||
;
|
||||
;Registers used s0, UART_data and UART_status
|
||||
;
|
||||
UART_write: INPUT UART_status, UART_status_port
|
||||
TEST UART_status, tx_full ;test for space in buffer
|
||||
JUMP NZ, UART_write ;wait if no space
|
||||
LOAD s0, 00 ;compute parity for data being sent
|
||||
TEST UART_data, FF
|
||||
SRA s0 ;move parity value into MSB
|
||||
XOR s0, 80 ;**** include this line for ODD parity
|
||||
OUTPUT s0, UART_control_port ;send parity to UART (no reset)
|
||||
OUTPUT UART_data, UART_write_port ;write data and parity into transmitter
|
||||
RETURN
|
||||
;
|
||||
|
||||
|
||||
;Read byte from UART with test for EVEN or ODD parity.
|
||||
;
|
||||
;The routine tests and waits for available data and then reads the byte
|
||||
;data into register 'UART_data'. The data is then tested against the parity
|
||||
;bit received. For good data the ZERO flag will be set. A parity error will
|
||||
;will be signified by the ZERO flag being reset.
|
||||
;
|
||||
;Odd and even Parity is describes the total number of 1's sent
|
||||
;in the complete 9-bit packet formed of 8-bit data and the parity bit.
|
||||
;For EVEN parity comment out the line indicated ***.
|
||||
;For ODD parity include the line indicated ***.
|
||||
;
|
||||
;Registers used s0, UART_data and UART_status
|
||||
;
|
||||
;
|
||||
UART_read: INPUT UART_status, UART_status_port ;Test for available character
|
||||
TEST UART_status, rx_data_present ;test for space in buffer
|
||||
INPUT UART_data, UART_read_port
|
||||
LOAD s0, 00 ;compute parity for received data
|
||||
TEST UART_data, FF
|
||||
SRA s0
|
||||
XOR s0, 80 ;****include this line for ODD parity
|
||||
AND UART_status, rx_parity ;isolate parity bit received
|
||||
XOR s0, UART_status ;ZERO set if parity matches
|
||||
RETURN
|
||||
;
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
|
||||
Simple Error Correction Technique
|
||||
---------------------------------
|
||||
|
||||
This is a very old technique which can provide a degree of error correction. Although a
|
||||
parity error can indicate that an error has occurred, it is not possible to know which bit
|
||||
has been received in error. This technique can be used to detect and correct the occasional
|
||||
bit error.
|
||||
|
||||
In this example we assume that 8 bytes of data are to be sent. These are the ASCII characters
|
||||
ABCDEFGH. First each byte is transmitted with ODD parity (although EVEN could also be used).
|
||||
|
||||
A 0 1 0 0 0 0 0 1 1
|
||||
B 0 1 0 0 0 0 1 0 1
|
||||
C 0 1 0 0 0 0 1 1 0
|
||||
D 0 1 0 0 0 1 0 0 1
|
||||
E 0 1 0 0 0 1 0 1 0
|
||||
F 0 1 0 0 0 1 1 0 0
|
||||
G 0 1 0 0 0 1 1 1 1
|
||||
H 0 1 0 0 0 1 0 0 1
|
||||
|
||||
Next a 'parity byte' is transmitted. Each bit represents the ODD parity of the corresponding bit
|
||||
transmitted in the last 8 bytes. In other words, it is the ODD parity associated with each of
|
||||
the above columns.
|
||||
|
||||
1 1 1 1 1 0 1 1 *
|
||||
|
||||
It is debatable as to what to transmit as parity for this 'parity byte'. It could just be the
|
||||
parity of the 'parity byte' in the normal way. It could be the parity of the previous 8 parity
|
||||
bits transmitted or a combination of both. The uart9 macros allow you to make the choice in
|
||||
software because it is treated the same way as any other data bit.
|
||||
|
||||
|
||||
Now consider receiving the above data packet, but with a bit error at bit 6 of the character 'D'.
|
||||
|
||||
A 0 1 0 0 0 0 0 1 1
|
||||
B 0 1 0 0 0 0 1 0 1
|
||||
C 0 1 0 0 0 0 1 1 0
|
||||
D 0 0 0 0 0 1 0 0 1 <----- Parity error
|
||||
E 0 1 0 0 0 1 0 1 0
|
||||
F 0 1 0 0 0 1 1 0 0
|
||||
G 0 1 0 0 0 1 1 1 1
|
||||
H 0 1 0 0 0 1 0 0 1
|
||||
1 1 1 1 1 0 1 1 *
|
||||
|
||||
^
|
||||
|
|
||||
parity
|
||||
error
|
||||
|
||||
The parity error on the 'D' line tells us there has been some kind of error but we do not know
|
||||
which bit caused it. The 'parity byte' also indicates that an error has occurred in the bit 6
|
||||
column, but we don't know which byte was the cause. However, it can easily be seen that the
|
||||
intersection of these error points reveals the bit error and it would therefore be reasonable
|
||||
to correct this bit by simple inversion.
|
||||
|
||||
It is possible to correct more than one bit error in a packet so long as the errors occur in
|
||||
different rows and columns. There is always a danger that the parity bits may be corrupted and
|
||||
this is where the parity of the 'parity byte' (*) could benefit from being the computation of
|
||||
all 16 parity bits.
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
End of file UART9_readme.txt
|
||||
-----------------------------------------------------------------------------------------------
|
||||
@@ -0,0 +1,281 @@
|
||||
-- 'Bucket Brigade' FIFO
|
||||
-- 16 deep
|
||||
-- 8-bit data
|
||||
--
|
||||
-- Version : 1.10
|
||||
-- Version Date : 3rd December 2003
|
||||
-- Reason : '--translate' directives changed to '--synthesis translate' directives
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 14th October 2002
|
||||
--
|
||||
-- Start of design entry : 14th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for BBFIFO_16x8
|
||||
--
|
||||
entity bbfifo_16x8 is
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end bbfifo_16x8;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for BBFIFO_16x8
|
||||
--
|
||||
architecture low_level_definition of bbfifo_16x8 is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in BBFIFO_16x8
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal pointer : std_logic_vector(3 downto 0);
|
||||
signal next_count : std_logic_vector(3 downto 0);
|
||||
signal half_count : std_logic_vector(3 downto 0);
|
||||
signal count_carry : std_logic_vector(2 downto 0);
|
||||
|
||||
signal pointer_zero : std_logic;
|
||||
signal pointer_full : std_logic;
|
||||
signal decode_data_present : std_logic;
|
||||
signal data_present_int : std_logic;
|
||||
signal valid_write : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of zero_lut : label is "0001";
|
||||
attribute INIT of full_lut : label is "8000";
|
||||
attribute INIT of dp_lut : label is "BFA0";
|
||||
attribute INIT of valid_lut : label is "C4";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of BBFIFO_16x8 circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- SRL16E data storage
|
||||
|
||||
data_width_loop: for i in 0 to 7 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of data_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
data_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_in(i),
|
||||
CE => valid_write,
|
||||
CLK => clk,
|
||||
A0 => pointer(0),
|
||||
A1 => pointer(1),
|
||||
A2 => pointer(2),
|
||||
A3 => pointer(3),
|
||||
Q => data_out(i) );
|
||||
|
||||
end generate data_width_loop;
|
||||
|
||||
-- 4-bit counter to act as data pointer
|
||||
-- Counter is clock enabled by 'data_present'
|
||||
-- Counter will be reset when 'reset' is active
|
||||
-- Counter will increment when 'valid_write' is active
|
||||
|
||||
count_width_loop: for i in 0 to 3 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of count_lut : label is "6606";
|
||||
--
|
||||
begin
|
||||
|
||||
register_bit: FDRE
|
||||
port map ( D => next_count(i),
|
||||
Q => pointer(i),
|
||||
CE => data_present_int,
|
||||
R => reset,
|
||||
C => clk);
|
||||
|
||||
count_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"6606")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(i),
|
||||
I1 => read,
|
||||
I2 => pointer_zero,
|
||||
I3 => write,
|
||||
O => half_count(i));
|
||||
|
||||
lsb_count: if i=0 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => pointer(i),
|
||||
CI => valid_write,
|
||||
S => half_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => valid_write,
|
||||
O => next_count(i));
|
||||
|
||||
end generate lsb_count;
|
||||
|
||||
mid_count: if i>0 and i<3 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => pointer(i),
|
||||
CI => count_carry(i-1),
|
||||
S => half_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate mid_count;
|
||||
|
||||
upper_count: if i=3 generate
|
||||
begin
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate upper_count;
|
||||
|
||||
end generate count_width_loop;
|
||||
|
||||
|
||||
-- Detect when pointer is zero and maximum
|
||||
|
||||
zero_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0001")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(0),
|
||||
I1 => pointer(1),
|
||||
I2 => pointer(2),
|
||||
I3 => pointer(3),
|
||||
O => pointer_zero );
|
||||
|
||||
|
||||
full_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8000")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(0),
|
||||
I1 => pointer(1),
|
||||
I2 => pointer(2),
|
||||
I3 => pointer(3),
|
||||
O => pointer_full );
|
||||
|
||||
|
||||
-- Data Present status
|
||||
|
||||
dp_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"BFA0")
|
||||
--synthesis translate_on
|
||||
port map( I0 => write,
|
||||
I1 => read,
|
||||
I2 => pointer_zero,
|
||||
I3 => data_present_int,
|
||||
O => decode_data_present );
|
||||
|
||||
dp_flop: FDR
|
||||
port map ( D => decode_data_present,
|
||||
Q => data_present_int,
|
||||
R => reset,
|
||||
C => clk);
|
||||
|
||||
-- Valid write signal
|
||||
|
||||
valid_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"C4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer_full,
|
||||
I1 => write,
|
||||
I2 => read,
|
||||
O => valid_write );
|
||||
|
||||
|
||||
-- assign internal signals to outputs
|
||||
|
||||
full <= pointer_full;
|
||||
half_full <= pointer(3);
|
||||
data_present <= data_present_int;
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE BBFIFO_16x8.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,275 @@
|
||||
-- 'Bucket Brigade' FIFO
|
||||
-- 16 deep
|
||||
-- 9-bit data
|
||||
--
|
||||
-- Version : 1.00 (derived from bbfifo_16x8 version 1.10)
|
||||
-- Version Date : 10th February 2005
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for BBFIFO_16x9
|
||||
--
|
||||
entity bbfifo_16x9 is
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end bbfifo_16x9;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for BBFIFO_16x9
|
||||
--
|
||||
architecture low_level_definition of bbfifo_16x9 is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in BBFIFO_16x9
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal pointer : std_logic_vector(3 downto 0);
|
||||
signal next_count : std_logic_vector(3 downto 0);
|
||||
signal half_count : std_logic_vector(3 downto 0);
|
||||
signal count_carry : std_logic_vector(2 downto 0);
|
||||
|
||||
signal pointer_zero : std_logic;
|
||||
signal pointer_full : std_logic;
|
||||
signal decode_data_present : std_logic;
|
||||
signal data_present_int : std_logic;
|
||||
signal valid_write : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of zero_lut : label is "0001";
|
||||
attribute INIT of full_lut : label is "8000";
|
||||
attribute INIT of dp_lut : label is "BFA0";
|
||||
attribute INIT of valid_lut : label is "C4";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of BBFIFO_16x9 circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- SRL16E data storage
|
||||
|
||||
data_width_loop: for i in 0 to 8 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of data_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
data_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_in(i),
|
||||
CE => valid_write,
|
||||
CLK => clk,
|
||||
A0 => pointer(0),
|
||||
A1 => pointer(1),
|
||||
A2 => pointer(2),
|
||||
A3 => pointer(3),
|
||||
Q => data_out(i) );
|
||||
|
||||
end generate data_width_loop;
|
||||
|
||||
-- 4-bit counter to act as data pointer
|
||||
-- Counter is clock enabled by 'data_present'
|
||||
-- Counter will be reset when 'reset' is active
|
||||
-- Counter will increment when 'valid_write' is active
|
||||
|
||||
count_width_loop: for i in 0 to 3 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of count_lut : label is "6606";
|
||||
--
|
||||
begin
|
||||
|
||||
register_bit: FDRE
|
||||
port map ( D => next_count(i),
|
||||
Q => pointer(i),
|
||||
CE => data_present_int,
|
||||
R => reset,
|
||||
C => clk);
|
||||
|
||||
count_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"6606")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(i),
|
||||
I1 => read,
|
||||
I2 => pointer_zero,
|
||||
I3 => write,
|
||||
O => half_count(i));
|
||||
|
||||
lsb_count: if i=0 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => pointer(i),
|
||||
CI => valid_write,
|
||||
S => half_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => valid_write,
|
||||
O => next_count(i));
|
||||
|
||||
end generate lsb_count;
|
||||
|
||||
mid_count: if i>0 and i<3 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => pointer(i),
|
||||
CI => count_carry(i-1),
|
||||
S => half_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate mid_count;
|
||||
|
||||
upper_count: if i=3 generate
|
||||
begin
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate upper_count;
|
||||
|
||||
end generate count_width_loop;
|
||||
|
||||
|
||||
-- Detect when pointer is zero and maximum
|
||||
|
||||
zero_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0001")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(0),
|
||||
I1 => pointer(1),
|
||||
I2 => pointer(2),
|
||||
I3 => pointer(3),
|
||||
O => pointer_zero );
|
||||
|
||||
|
||||
full_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8000")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(0),
|
||||
I1 => pointer(1),
|
||||
I2 => pointer(2),
|
||||
I3 => pointer(3),
|
||||
O => pointer_full );
|
||||
|
||||
|
||||
-- Data Present status
|
||||
|
||||
dp_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"BFA0")
|
||||
--synthesis translate_on
|
||||
port map( I0 => write,
|
||||
I1 => read,
|
||||
I2 => pointer_zero,
|
||||
I3 => data_present_int,
|
||||
O => decode_data_present );
|
||||
|
||||
dp_flop: FDR
|
||||
port map ( D => decode_data_present,
|
||||
Q => data_present_int,
|
||||
R => reset,
|
||||
C => clk);
|
||||
|
||||
-- Valid write signal
|
||||
|
||||
valid_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"C4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer_full,
|
||||
I1 => write,
|
||||
I2 => read,
|
||||
O => valid_write );
|
||||
|
||||
|
||||
-- assign internal signals to outputs
|
||||
|
||||
full <= pointer_full;
|
||||
half_full <= pointer(3);
|
||||
data_present <= data_present_int;
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE BBFIFO_16x9.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,106 @@
|
||||
--
|
||||
-- EMBEDDED_KCPSM3.VHD
|
||||
--
|
||||
-- Ken Chapman - Xilinx Ltd - 3rd June 2003
|
||||
--
|
||||
-- This file instantiates the KCPSM3 processor macro and connects the
|
||||
-- program ROM.
|
||||
--
|
||||
-- NOTE: The name of the program ROM will probably need to be changed to
|
||||
-- reflect the name of the program (PSM) file applied to the assembler.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
--
|
||||
entity embedded_kcpsm3 is
|
||||
Port ( port_id : out std_logic_vector(7 downto 0);
|
||||
write_strobe : out std_logic;
|
||||
read_strobe : out std_logic;
|
||||
out_port : out std_logic_vector(7 downto 0);
|
||||
in_port : in std_logic_vector(7 downto 0);
|
||||
interrupt : in std_logic;
|
||||
interrupt_ack : out std_logic;
|
||||
reset : in std_logic;
|
||||
clk : in std_logic);
|
||||
end embedded_kcpsm3;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of test achitecture
|
||||
--
|
||||
architecture connectivity of embedded_kcpsm3 is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- declaration of KCPSM3
|
||||
--
|
||||
component kcpsm3
|
||||
Port ( address : out std_logic_vector(9 downto 0);
|
||||
instruction : in std_logic_vector(17 downto 0);
|
||||
port_id : out std_logic_vector(7 downto 0);
|
||||
write_strobe : out std_logic;
|
||||
out_port : out std_logic_vector(7 downto 0);
|
||||
read_strobe : out std_logic;
|
||||
in_port : in std_logic_vector(7 downto 0);
|
||||
interrupt : in std_logic;
|
||||
interrupt_ack : out std_logic;
|
||||
reset : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of program ROM
|
||||
--
|
||||
component prog_rom
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used to connect KCPSM3 to program ROM
|
||||
--
|
||||
signal address : std_logic_vector(9 downto 0);
|
||||
signal instruction : std_logic_vector(17 downto 0);
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of test circuit description
|
||||
--
|
||||
begin
|
||||
|
||||
processor: kcpsm3
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
port_id => port_id,
|
||||
write_strobe => write_strobe,
|
||||
out_port => out_port,
|
||||
read_strobe => read_strobe,
|
||||
in_port => in_port,
|
||||
interrupt => interrupt,
|
||||
interrupt_ack => interrupt_ack,
|
||||
reset => reset,
|
||||
clk => clk);
|
||||
|
||||
program: prog_rom
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
clk => clk);
|
||||
|
||||
end connectivity;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE EMBEDDED_KCPSM3.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,155 @@
|
||||
--
|
||||
-- Interrupt test for KCPSM3
|
||||
--
|
||||
-- Ken Chapman - Xilinx Ltd - June 2003
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
--
|
||||
entity kcpsm3_int_test is
|
||||
Port ( counter : out std_logic_vector(7 downto 0);
|
||||
waveforms : out std_logic_vector(7 downto 0);
|
||||
interrupt_event : in std_logic;
|
||||
clk : in std_logic);
|
||||
end kcpsm3_int_test;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of test achitecture
|
||||
--
|
||||
architecture Behavioral of kcpsm3_int_test is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- declaration of KCPSM3
|
||||
--
|
||||
component kcpsm3
|
||||
Port ( address : out std_logic_vector(9 downto 0);
|
||||
instruction : in std_logic_vector(17 downto 0);
|
||||
port_id : out std_logic_vector(7 downto 0);
|
||||
write_strobe : out std_logic;
|
||||
out_port : out std_logic_vector(7 downto 0);
|
||||
read_strobe : out std_logic;
|
||||
in_port : in std_logic_vector(7 downto 0);
|
||||
interrupt : in std_logic;
|
||||
interrupt_ack : out std_logic;
|
||||
reset : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of program ROM
|
||||
--
|
||||
component int_test
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used to connect KCPSM3 to program ROM and I/O logic
|
||||
--
|
||||
signal address : std_logic_vector(9 downto 0);
|
||||
signal instruction : std_logic_vector(17 downto 0);
|
||||
signal port_id : std_logic_vector(7 downto 0);
|
||||
signal out_port : std_logic_vector(7 downto 0);
|
||||
signal in_port : std_logic_vector(7 downto 0);
|
||||
signal write_strobe : std_logic;
|
||||
signal read_strobe : std_logic;
|
||||
signal interrupt : std_logic :='0';
|
||||
signal interrupt_ack : std_logic;
|
||||
signal reset : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of circuit description
|
||||
--
|
||||
begin
|
||||
|
||||
-- Inserting KCPSM3 and the program memory
|
||||
|
||||
processor: kcpsm3
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
port_id => port_id,
|
||||
write_strobe => write_strobe,
|
||||
out_port => out_port,
|
||||
read_strobe => read_strobe,
|
||||
in_port => in_port,
|
||||
interrupt => interrupt,
|
||||
interrupt_ack => interrupt_ack,
|
||||
reset => reset,
|
||||
clk => clk);
|
||||
|
||||
program: int_test
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
clk => clk);
|
||||
|
||||
-- Unused inputs on processor
|
||||
|
||||
in_port <= "00000000";
|
||||
reset <= '0';
|
||||
|
||||
-- Adding the output registers to the processor
|
||||
|
||||
IO_registers: process(clk)
|
||||
begin
|
||||
|
||||
if clk'event and clk='1' then
|
||||
|
||||
-- waveform register at address 02
|
||||
if port_id(1)='1' and write_strobe='1' then
|
||||
waveforms <= out_port;
|
||||
end if;
|
||||
|
||||
-- Interrupt Counter register at address 04
|
||||
if port_id(2)='1' and write_strobe='1' then
|
||||
counter <= out_port;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end process IO_registers;
|
||||
|
||||
|
||||
|
||||
-- Adding the interrupt input
|
||||
-- Note that the initial value of interrupt (low) is
|
||||
-- defined at signal declaration.
|
||||
|
||||
interrupt_control: process(clk)
|
||||
begin
|
||||
|
||||
if clk'event and clk='1' then
|
||||
if interrupt_ack='1' then
|
||||
interrupt <= '0';
|
||||
elsif interrupt_event='1' then
|
||||
interrupt <= '1';
|
||||
else
|
||||
interrupt <= interrupt;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process interrupt_control;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCPSM3_INT_TEST.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,351 @@
|
||||
-- 9-Bit Constant (K) Compact UART Receiver
|
||||
--
|
||||
-- 9 data bits, no parity, 1 stop bit
|
||||
-- or
|
||||
-- 8 data bits, parity, 1 stop bit
|
||||
-- where the value of the parity bit must be checked externally and is provided as data_out(8).
|
||||
--
|
||||
-- Version : 1.00 (derived from kcuart_rx version 1.00)
|
||||
-- Version Date : 11th February 2005
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for KCUART9_RX
|
||||
--
|
||||
entity kcuart9_rx is
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
data_strobe : out std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
clk : in std_logic);
|
||||
end kcuart9_rx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for KCUART9_RX
|
||||
--
|
||||
architecture low_level_definition of kcuart9_rx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in KCUART9_RX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal sync_serial : std_logic;
|
||||
signal stop_bit : std_logic;
|
||||
signal data_int : std_logic_vector(8 downto 0);
|
||||
signal data_delay : std_logic_vector(8 downto 0);
|
||||
signal start_delay : std_logic;
|
||||
signal start_bit : std_logic;
|
||||
signal edge_delay : std_logic;
|
||||
signal start_edge : std_logic;
|
||||
signal decode_valid_char : std_logic;
|
||||
signal valid_char : std_logic;
|
||||
signal decode_purge : std_logic;
|
||||
signal purge : std_logic;
|
||||
signal valid_srl_delay : std_logic_vector(9 downto 0);
|
||||
signal valid_reg_delay : std_logic_vector(9 downto 0);
|
||||
signal decode_data_strobe : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of start_srl : label is "0000";
|
||||
attribute INIT of edge_srl : label is "0000";
|
||||
attribute INIT of valid_lut : label is "0040";
|
||||
attribute INIT of purge_lut : label is "54";
|
||||
attribute INIT of strobe_lut : label is "8";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of KCUART9_RX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- Synchronise input serial data to system clock
|
||||
|
||||
sync_reg: FD
|
||||
port map ( D => serial_in,
|
||||
Q => sync_serial,
|
||||
C => clk);
|
||||
|
||||
stop_reg: FD
|
||||
port map ( D => sync_serial,
|
||||
Q => stop_bit,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Data delays to capture data at 16 times baud rate
|
||||
-- Each SRL16E is followed by a flip-flop for best timing
|
||||
|
||||
data_loop: for i in 0 to 8 generate
|
||||
begin
|
||||
|
||||
lsbs: if i<8 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_int(i+1),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => data_delay(i) );
|
||||
|
||||
end generate lsbs;
|
||||
|
||||
msb: if i=8 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => stop_bit,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => data_delay(i) );
|
||||
|
||||
end generate msb;
|
||||
|
||||
data_reg: FDE
|
||||
port map ( D => data_delay(i),
|
||||
Q => data_int(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
end generate data_loop;
|
||||
|
||||
-- Assign internal signals to outputs
|
||||
|
||||
data_out <= data_int;
|
||||
|
||||
-- Data delays to capture start bit at 16 time baud rate
|
||||
|
||||
start_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_int(0),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => start_delay );
|
||||
|
||||
start_reg: FDE
|
||||
port map ( D => start_delay,
|
||||
Q => start_bit,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Data delays to capture start bit leading edge at 16 time baud rate
|
||||
-- Delay ensures data is captured at mid-bit position
|
||||
|
||||
edge_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => start_bit,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '0',
|
||||
A2 => '1',
|
||||
A3 => '0',
|
||||
Q => edge_delay );
|
||||
|
||||
edge_reg: FDE
|
||||
port map ( D => edge_delay,
|
||||
Q => start_edge,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Detect a valid character
|
||||
|
||||
valid_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0040")
|
||||
--synthesis translate_on
|
||||
port map( I0 => purge,
|
||||
I1 => stop_bit,
|
||||
I2 => start_edge,
|
||||
I3 => edge_delay,
|
||||
O => decode_valid_char );
|
||||
|
||||
valid_reg: FDE
|
||||
port map ( D => decode_valid_char,
|
||||
Q => valid_char,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Purge of data status
|
||||
|
||||
purge_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"54")
|
||||
--synthesis translate_on
|
||||
port map( I0 => valid_reg_delay(9),
|
||||
I1 => valid_char,
|
||||
I2 => purge,
|
||||
O => decode_purge );
|
||||
|
||||
purge_reg: FDE
|
||||
port map ( D => decode_purge,
|
||||
Q => purge,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Delay of valid_char pulse of length equivalent to the time taken
|
||||
-- to purge data shift register of all data which has been used.
|
||||
-- Requires 10x16 + 8 delays which is achieved by packing of SRL16E with
|
||||
-- up to 16 delays and utilising the dedicated flip flop in each stage.
|
||||
|
||||
valid_loop: for i in 0 to 9 generate
|
||||
begin
|
||||
|
||||
lsb: if i=0 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay14_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay14_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => valid_char,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '0',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => valid_srl_delay(i) );
|
||||
|
||||
end generate lsb;
|
||||
|
||||
msbs: if i>0 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay16_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay16_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => valid_reg_delay(i-1),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => valid_srl_delay(i) );
|
||||
|
||||
end generate msbs;
|
||||
|
||||
data_reg: FDE
|
||||
port map ( D => valid_srl_delay(i),
|
||||
Q => valid_reg_delay(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
end generate valid_loop;
|
||||
|
||||
-- Form data strobe
|
||||
|
||||
strobe_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => valid_char,
|
||||
I1 => en_16_x_baud,
|
||||
O => decode_data_strobe );
|
||||
|
||||
strobe_reg: FD
|
||||
port map ( D => decode_data_strobe,
|
||||
Q => data_strobe,
|
||||
C => clk);
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCUART9_RX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,433 @@
|
||||
-- Constant (K) Compact UART Transmitter
|
||||
--
|
||||
-- 9-Bit UART Transmitter
|
||||
--
|
||||
-- 9 data bits, no parity, 1 stop bit
|
||||
-- or
|
||||
-- 8 data bits, parity, 1 stop bit
|
||||
-- where the value of the parity bit must be computed externally and provided as data_in(8).
|
||||
--
|
||||
-- NOTE : This macro is intended to be attached to bbfifo_16x9 and operation requires the
|
||||
-- interaction of signals to and from that FIFO buffer to work correctly.
|
||||
--
|
||||
-- Version : 1.00 (derived from kcuart_tx version 1.10)
|
||||
-- Version Date : 10th February 2005
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for KCUART9_TX
|
||||
--
|
||||
entity kcuart9_tx is
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
send_character : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
tx_complete : out std_logic;
|
||||
clk : in std_logic);
|
||||
end kcuart9_tx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for KCUART9_TX
|
||||
--
|
||||
architecture low_level_definition of kcuart9_tx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in KCUART9_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal data_01 : std_logic;
|
||||
signal data_23 : std_logic;
|
||||
signal data_45 : std_logic;
|
||||
signal data_67 : std_logic;
|
||||
signal data_0123 : std_logic;
|
||||
signal data_4567 : std_logic;
|
||||
signal data_01234567 : std_logic;
|
||||
signal data_01234567_reg : std_logic;
|
||||
|
||||
signal data8_buf : std_logic;
|
||||
signal force_serial : std_logic;
|
||||
signal next_serial : std_logic;
|
||||
|
||||
signal bit_count : std_logic_vector(2 downto 0);
|
||||
signal next_bit_count : std_logic_vector(2 downto 0);
|
||||
signal half_bit_count : std_logic_vector(2 downto 0);
|
||||
signal bit_count_cy : std_logic_vector(1 downto 0);
|
||||
|
||||
signal baud_count : std_logic_vector(3 downto 0);
|
||||
signal next_baud_count : std_logic_vector(3 downto 0);
|
||||
signal half_baud_count : std_logic_vector(3 downto 0);
|
||||
signal baud_count_cy : std_logic_vector(3 downto 0);
|
||||
signal tx_bit_en : std_logic;
|
||||
|
||||
signal decode7 : std_logic;
|
||||
signal sel_last_bit : std_logic;
|
||||
signal parity_bit : std_logic;
|
||||
signal next_transmit : std_logic;
|
||||
signal transmit : std_logic;
|
||||
signal next_tx_complete : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of mux1_lut : label is "E4";
|
||||
attribute INIT of mux2_lut : label is "E4";
|
||||
attribute INIT of mux3_lut : label is "E4";
|
||||
attribute INIT of mux4_lut : label is "E4";
|
||||
|
||||
attribute INIT of buf_data8 : label is "2";
|
||||
attribute INIT of force_lut : label is "E0FF";
|
||||
|
||||
attribute INIT of count7_lut : label is "80";
|
||||
attribute INIT of transmit_lut : label is "32";
|
||||
attribute INIT of complete_lut : label is "8";
|
||||
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of KCUART9_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- 8 to 1 multiplexer to convert parallel data to serial
|
||||
|
||||
mux1_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(0),
|
||||
I1 => data_in(0),
|
||||
I2 => data_in(1),
|
||||
O => data_01 );
|
||||
|
||||
mux2_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(0),
|
||||
I1 => data_in(2),
|
||||
I2 => data_in(3),
|
||||
O => data_23 );
|
||||
|
||||
mux3_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(0),
|
||||
I1 => data_in(4),
|
||||
I2 => data_in(5),
|
||||
O => data_45 );
|
||||
|
||||
mux4_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(0),
|
||||
I1 => data_in(6),
|
||||
I2 => data_in(7),
|
||||
O => data_67 );
|
||||
|
||||
|
||||
mux5_muxf5: MUXF5
|
||||
port map( I1 => data_23,
|
||||
I0 => data_01,
|
||||
S => bit_count(1),
|
||||
O => data_0123 );
|
||||
|
||||
mux6_muxf5: MUXF5
|
||||
port map( I1 => data_67,
|
||||
I0 => data_45,
|
||||
S => bit_count(1),
|
||||
O => data_4567 );
|
||||
|
||||
mux7_muxf6: MUXF6
|
||||
port map( I1 => data_4567,
|
||||
I0 => data_0123,
|
||||
S => bit_count(2),
|
||||
O => data_01234567 );
|
||||
|
||||
pipeline_mux: FD
|
||||
port map ( D => data_01234567,
|
||||
Q => data_01234567_reg,
|
||||
C => clk);
|
||||
|
||||
-- Serial output logic
|
||||
|
||||
buf_data8: LUT1
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"2")
|
||||
--synthesis translate_on
|
||||
port map( I0 => data_in(8),
|
||||
O => data8_buf );
|
||||
|
||||
force_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E0FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => data_01234567_reg,
|
||||
I1 => parity_bit,
|
||||
I2 => transmit,
|
||||
I3 => send_character,
|
||||
O => force_serial );
|
||||
|
||||
|
||||
mux8_muxf5: MUXF5
|
||||
port map( I1 => data8_buf,
|
||||
I0 => force_serial,
|
||||
S => sel_last_bit,
|
||||
O => next_serial );
|
||||
|
||||
-- Final output flip-flop initialised to start at '1'
|
||||
high_start: for i in 1 to 1 generate
|
||||
--
|
||||
attribute INIT : bit;
|
||||
attribute INIT of output_reg : label is '1';
|
||||
--
|
||||
begin
|
||||
|
||||
output_reg: FDE
|
||||
--synthesis translate_off
|
||||
generic map (INIT => '1')
|
||||
--synthesis translate_on
|
||||
port map ( D => next_serial,
|
||||
Q => serial_out,
|
||||
CE => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
end generate high_start;
|
||||
|
||||
|
||||
-- bit counter
|
||||
|
||||
bit_count_loop: for i in 0 to 2 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of bit_count_lut : label is "B";
|
||||
--
|
||||
begin
|
||||
|
||||
bit_reg: FDE
|
||||
port map ( D => next_bit_count(i),
|
||||
Q => bit_count(i),
|
||||
CE => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
bit_count_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"B")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(i),
|
||||
I1 => transmit,
|
||||
O => half_bit_count(i));
|
||||
|
||||
lsb_bit_count: if i=0 generate
|
||||
begin
|
||||
|
||||
bit_count_xor: XORCY
|
||||
port map( LI => half_bit_count(i),
|
||||
CI => '1',
|
||||
O => next_bit_count(i));
|
||||
|
||||
bit_count_muxcy: MUXCY
|
||||
port map( DI => '0',
|
||||
CI => '1',
|
||||
S => half_bit_count(i),
|
||||
O => bit_count_cy(i));
|
||||
|
||||
end generate lsb_bit_count;
|
||||
|
||||
upper_bit_count: if i>0 generate
|
||||
begin
|
||||
|
||||
bit_count_xor: XORCY
|
||||
port map( LI => half_bit_count(i),
|
||||
CI => bit_count_cy(i-1),
|
||||
O => next_bit_count(i));
|
||||
|
||||
middle_bit_count: if i=1 generate
|
||||
begin
|
||||
|
||||
bit_count_muxcy: MUXCY
|
||||
port map( DI => '0',
|
||||
CI => bit_count_cy(i-1),
|
||||
S => half_bit_count(i),
|
||||
O => bit_count_cy(i));
|
||||
|
||||
end generate middle_bit_count;
|
||||
|
||||
end generate upper_bit_count;
|
||||
|
||||
end generate bit_count_loop;
|
||||
|
||||
|
||||
-- baud counter
|
||||
|
||||
baud_count_loop: for i in 0 to 3 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of baud_count_lut : label is "2";
|
||||
--
|
||||
begin
|
||||
|
||||
baud_reg: FDE
|
||||
port map ( D => next_baud_count(i),
|
||||
Q => baud_count(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
baud_count_lut: LUT1
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"2")
|
||||
--synthesis translate_on
|
||||
port map( I0 => baud_count(i),
|
||||
O => half_baud_count(i));
|
||||
|
||||
lsb_baud_count: if i=0 generate
|
||||
begin
|
||||
|
||||
baud_count_xor: XORCY
|
||||
port map( LI => half_baud_count(i),
|
||||
CI => en_16_x_baud,
|
||||
O => next_baud_count(i));
|
||||
|
||||
baud_count_muxcy: MUXCY
|
||||
port map( DI => '0',
|
||||
CI => en_16_x_baud,
|
||||
S => half_baud_count(i),
|
||||
O => baud_count_cy(i));
|
||||
|
||||
end generate lsb_baud_count;
|
||||
|
||||
upper_baud_count: if i>0 generate
|
||||
begin
|
||||
|
||||
baud_count_xor: XORCY
|
||||
port map( LI => half_baud_count(i),
|
||||
CI => baud_count_cy(i-1),
|
||||
O => next_baud_count(i));
|
||||
|
||||
baud_count_muxcy: MUXCY
|
||||
port map( DI => '0',
|
||||
CI => baud_count_cy(i-1),
|
||||
S => half_baud_count(i),
|
||||
O => baud_count_cy(i));
|
||||
|
||||
end generate upper_baud_count;
|
||||
|
||||
end generate baud_count_loop;
|
||||
|
||||
bit_en_reg: FD
|
||||
port map ( D => baud_count_cy(3),
|
||||
Q => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
-- state machine
|
||||
|
||||
count7_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"80")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(0),
|
||||
I1 => bit_count(1),
|
||||
I2 => bit_count(2),
|
||||
O => decode7 );
|
||||
|
||||
sel_last_reg: FDE
|
||||
port map ( D => decode7,
|
||||
Q => sel_last_bit,
|
||||
CE => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
parity_reg: FDE
|
||||
port map ( D => sel_last_bit,
|
||||
Q => parity_bit,
|
||||
CE => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
transmit_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"32")
|
||||
--synthesis translate_on
|
||||
port map( I0 => send_character,
|
||||
I1 => parity_bit,
|
||||
I2 => transmit,
|
||||
O => next_transmit );
|
||||
|
||||
transmit_reg: FDE
|
||||
port map ( D => next_transmit,
|
||||
Q => transmit,
|
||||
CE => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
complete_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => parity_bit,
|
||||
I1 => tx_bit_en,
|
||||
O => next_tx_complete );
|
||||
|
||||
complete_reg: FD
|
||||
port map ( D => next_tx_complete,
|
||||
Q => tx_complete,
|
||||
C => clk);
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCUART9_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,352 @@
|
||||
-- Constant (K) Compact UART Receiver
|
||||
--
|
||||
-- Version : 1.10
|
||||
-- Version Date : 3rd December 2003
|
||||
-- Reason : '--translate' directives changed to '--synthesis translate' directives
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 16th October 2002
|
||||
--
|
||||
-- Start of design entry : 16th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for KCUART_RX
|
||||
--
|
||||
entity kcuart_rx is
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
data_strobe : out std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
clk : in std_logic);
|
||||
end kcuart_rx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for KCUART_RX
|
||||
--
|
||||
architecture low_level_definition of kcuart_rx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in KCUART_RX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal sync_serial : std_logic;
|
||||
signal stop_bit : std_logic;
|
||||
signal data_int : std_logic_vector(7 downto 0);
|
||||
signal data_delay : std_logic_vector(7 downto 0);
|
||||
signal start_delay : std_logic;
|
||||
signal start_bit : std_logic;
|
||||
signal edge_delay : std_logic;
|
||||
signal start_edge : std_logic;
|
||||
signal decode_valid_char : std_logic;
|
||||
signal valid_char : std_logic;
|
||||
signal decode_purge : std_logic;
|
||||
signal purge : std_logic;
|
||||
signal valid_srl_delay : std_logic_vector(8 downto 0);
|
||||
signal valid_reg_delay : std_logic_vector(8 downto 0);
|
||||
signal decode_data_strobe : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of start_srl : label is "0000";
|
||||
attribute INIT of edge_srl : label is "0000";
|
||||
attribute INIT of valid_lut : label is "0040";
|
||||
attribute INIT of purge_lut : label is "54";
|
||||
attribute INIT of strobe_lut : label is "8";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of KCUART_RX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- Synchronise input serial data to system clock
|
||||
|
||||
sync_reg: FD
|
||||
port map ( D => serial_in,
|
||||
Q => sync_serial,
|
||||
C => clk);
|
||||
|
||||
stop_reg: FD
|
||||
port map ( D => sync_serial,
|
||||
Q => stop_bit,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Data delays to capture data at 16 time baud rate
|
||||
-- Each SRL16E is followed by a flip-flop for best timing
|
||||
|
||||
data_loop: for i in 0 to 7 generate
|
||||
begin
|
||||
|
||||
lsbs: if i<7 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_int(i+1),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => data_delay(i) );
|
||||
|
||||
end generate lsbs;
|
||||
|
||||
msb: if i=7 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => stop_bit,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => data_delay(i) );
|
||||
|
||||
end generate msb;
|
||||
|
||||
data_reg: FDE
|
||||
port map ( D => data_delay(i),
|
||||
Q => data_int(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
end generate data_loop;
|
||||
|
||||
-- Assign internal signals to outputs
|
||||
|
||||
data_out <= data_int;
|
||||
|
||||
-- Data delays to capture start bit at 16 time baud rate
|
||||
|
||||
start_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_int(0),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => start_delay );
|
||||
|
||||
start_reg: FDE
|
||||
port map ( D => start_delay,
|
||||
Q => start_bit,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Data delays to capture start bit leading edge at 16 time baud rate
|
||||
-- Delay ensures data is captured at mid-bit position
|
||||
|
||||
edge_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => start_bit,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '0',
|
||||
A2 => '1',
|
||||
A3 => '0',
|
||||
Q => edge_delay );
|
||||
|
||||
edge_reg: FDE
|
||||
port map ( D => edge_delay,
|
||||
Q => start_edge,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Detect a valid character
|
||||
|
||||
valid_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0040")
|
||||
--synthesis translate_on
|
||||
port map( I0 => purge,
|
||||
I1 => stop_bit,
|
||||
I2 => start_edge,
|
||||
I3 => edge_delay,
|
||||
O => decode_valid_char );
|
||||
|
||||
valid_reg: FDE
|
||||
port map ( D => decode_valid_char,
|
||||
Q => valid_char,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Purge of data status
|
||||
|
||||
purge_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"54")
|
||||
--synthesis translate_on
|
||||
port map( I0 => valid_reg_delay(8),
|
||||
I1 => valid_char,
|
||||
I2 => purge,
|
||||
O => decode_purge );
|
||||
|
||||
purge_reg: FDE
|
||||
port map ( D => decode_purge,
|
||||
Q => purge,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Delay of valid_char pulse of length equivalent to the time taken
|
||||
-- to purge data shift register of all data which has been used.
|
||||
-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
|
||||
-- up to 16 delays and utilising the dedicated flip flop in each stage.
|
||||
|
||||
valid_loop: for i in 0 to 8 generate
|
||||
begin
|
||||
|
||||
lsb: if i=0 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => valid_char,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => valid_srl_delay(i) );
|
||||
|
||||
end generate lsb;
|
||||
|
||||
msbs: if i>0 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay16_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay16_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => valid_reg_delay(i-1),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => valid_srl_delay(i) );
|
||||
|
||||
end generate msbs;
|
||||
|
||||
data_reg: FDE
|
||||
port map ( D => valid_srl_delay(i),
|
||||
Q => valid_reg_delay(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
end generate valid_loop;
|
||||
|
||||
-- Form data strobe
|
||||
|
||||
strobe_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => valid_char,
|
||||
I1 => en_16_x_baud,
|
||||
O => decode_data_strobe );
|
||||
|
||||
strobe_reg: FD
|
||||
port map ( D => decode_data_strobe,
|
||||
Q => data_strobe,
|
||||
C => clk);
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCUART_RX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,394 @@
|
||||
-- Constant (K) Compact UART Transmitter
|
||||
--
|
||||
-- Version : 1.10
|
||||
-- Version Date : 3rd December 2003
|
||||
-- Reason : '--translate' directives changed to '--synthesis translate' directives
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 14th October 2002
|
||||
--
|
||||
-- Start of design entry : 2nd October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for KCUART_TX
|
||||
--
|
||||
entity kcuart_tx is
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
send_character : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
Tx_complete : out std_logic;
|
||||
clk : in std_logic);
|
||||
end kcuart_tx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for KCUART_TX
|
||||
--
|
||||
architecture low_level_definition of kcuart_tx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in KCUART_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal data_01 : std_logic;
|
||||
signal data_23 : std_logic;
|
||||
signal data_45 : std_logic;
|
||||
signal data_67 : std_logic;
|
||||
signal data_0123 : std_logic;
|
||||
signal data_4567 : std_logic;
|
||||
signal data_01234567 : std_logic;
|
||||
signal bit_select : std_logic_vector(2 downto 0);
|
||||
signal next_count : std_logic_vector(2 downto 0);
|
||||
signal mask_count : std_logic_vector(2 downto 0);
|
||||
signal mask_count_carry : std_logic_vector(2 downto 0);
|
||||
signal count_carry : std_logic_vector(2 downto 0);
|
||||
signal ready_to_start : std_logic;
|
||||
signal decode_Tx_start : std_logic;
|
||||
signal Tx_start : std_logic;
|
||||
signal decode_Tx_run : std_logic;
|
||||
signal Tx_run : std_logic;
|
||||
signal decode_hot_state : std_logic;
|
||||
signal hot_state : std_logic;
|
||||
signal hot_delay : std_logic;
|
||||
signal Tx_bit : std_logic;
|
||||
signal decode_Tx_stop : std_logic;
|
||||
signal Tx_stop : std_logic;
|
||||
signal decode_Tx_complete : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of mux1_lut : label is "E4FF";
|
||||
attribute INIT of mux2_lut : label is "E4FF";
|
||||
attribute INIT of mux3_lut : label is "E4FF";
|
||||
attribute INIT of mux4_lut : label is "E4FF";
|
||||
attribute INIT of ready_lut : label is "10";
|
||||
attribute INIT of start_lut : label is "0190";
|
||||
attribute INIT of run_lut : label is "1540";
|
||||
attribute INIT of hot_state_lut : label is "94";
|
||||
attribute INIT of delay14_srl : label is "0000";
|
||||
attribute INIT of stop_lut : label is "0180";
|
||||
attribute INIT of complete_lut : label is "8";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of KCUART_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- 8 to 1 multiplexer to convert parallel data to serial
|
||||
|
||||
mux1_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(0),
|
||||
I2 => data_in(1),
|
||||
I3 => Tx_run,
|
||||
O => data_01 );
|
||||
|
||||
mux2_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(2),
|
||||
I2 => data_in(3),
|
||||
I3 => Tx_run,
|
||||
O => data_23 );
|
||||
|
||||
mux3_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(4),
|
||||
I2 => data_in(5),
|
||||
I3 => Tx_run,
|
||||
O => data_45 );
|
||||
|
||||
mux4_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(6),
|
||||
I2 => data_in(7),
|
||||
I3 => Tx_run,
|
||||
O => data_67 );
|
||||
|
||||
mux5_muxf5: MUXF5
|
||||
port map( I1 => data_23,
|
||||
I0 => data_01,
|
||||
S => bit_select(1),
|
||||
O => data_0123 );
|
||||
|
||||
mux6_muxf5: MUXF5
|
||||
port map( I1 => data_67,
|
||||
I0 => data_45,
|
||||
S => bit_select(1),
|
||||
O => data_4567 );
|
||||
|
||||
mux7_muxf6: MUXF6
|
||||
port map( I1 => data_4567,
|
||||
I0 => data_0123,
|
||||
S => bit_select(2),
|
||||
O => data_01234567 );
|
||||
|
||||
-- Register serial output and force start and stop bits
|
||||
|
||||
pipeline_serial: FDRS
|
||||
port map ( D => data_01234567,
|
||||
Q => serial_out,
|
||||
R => Tx_start,
|
||||
S => Tx_stop,
|
||||
C => clk);
|
||||
|
||||
-- 3-bit counter
|
||||
-- Counter is clock enabled by en_16_x_baud
|
||||
-- Counter will be reset when 'Tx_start' is active
|
||||
-- Counter will increment when Tx_bit is active
|
||||
-- Tx_run must be active to count
|
||||
-- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow)
|
||||
|
||||
count_width_loop: for i in 0 to 2 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of count_lut : label is "8";
|
||||
--
|
||||
begin
|
||||
|
||||
register_bit: FDRE
|
||||
port map ( D => next_count(i),
|
||||
Q => bit_select(i),
|
||||
CE => en_16_x_baud,
|
||||
R => Tx_start,
|
||||
C => clk);
|
||||
|
||||
count_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(i),
|
||||
I1 => Tx_run,
|
||||
O => mask_count(i));
|
||||
|
||||
mask_and: MULT_AND
|
||||
port map( I0 => bit_select(i),
|
||||
I1 => Tx_run,
|
||||
LO => mask_count_carry(i));
|
||||
|
||||
lsb_count: if i=0 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => mask_count_carry(i),
|
||||
CI => Tx_bit,
|
||||
S => mask_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => mask_count(i),
|
||||
CI => Tx_bit,
|
||||
O => next_count(i));
|
||||
|
||||
end generate lsb_count;
|
||||
|
||||
upper_count: if i>0 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => mask_count_carry(i),
|
||||
CI => count_carry(i-1),
|
||||
S => mask_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => mask_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate upper_count;
|
||||
|
||||
end generate count_width_loop;
|
||||
|
||||
-- Ready to start decode
|
||||
|
||||
ready_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"10")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_run,
|
||||
I1 => Tx_start,
|
||||
I2 => send_character,
|
||||
O => ready_to_start );
|
||||
|
||||
-- Start bit enable
|
||||
|
||||
start_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0190")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_bit,
|
||||
I1 => Tx_stop,
|
||||
I2 => ready_to_start,
|
||||
I3 => Tx_start,
|
||||
O => decode_Tx_start );
|
||||
|
||||
Tx_start_reg: FDE
|
||||
port map ( D => decode_Tx_start,
|
||||
Q => Tx_start,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Run bit enable
|
||||
|
||||
run_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"1540")
|
||||
--synthesis translate_on
|
||||
port map( I0 => count_carry(2),
|
||||
I1 => Tx_bit,
|
||||
I2 => Tx_start,
|
||||
I3 => Tx_run,
|
||||
O => decode_Tx_run );
|
||||
|
||||
Tx_run_reg: FDE
|
||||
port map ( D => decode_Tx_run,
|
||||
Q => Tx_run,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Bit rate enable
|
||||
|
||||
hot_state_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"94")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_stop,
|
||||
I1 => ready_to_start,
|
||||
I2 => Tx_bit,
|
||||
O => decode_hot_state );
|
||||
|
||||
hot_state_reg: FDE
|
||||
port map ( D => decode_hot_state,
|
||||
Q => hot_state,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
delay14_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => hot_state,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '0',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => hot_delay );
|
||||
|
||||
Tx_bit_reg: FDE
|
||||
port map ( D => hot_delay,
|
||||
Q => Tx_bit,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Stop bit enable
|
||||
|
||||
stop_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0180")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_bit,
|
||||
I1 => Tx_run,
|
||||
I2 => count_carry(2),
|
||||
I3 => Tx_stop,
|
||||
O => decode_Tx_stop );
|
||||
|
||||
Tx_stop_reg: FDE
|
||||
port map ( D => decode_Tx_stop,
|
||||
Q => Tx_stop,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Tx_complete strobe
|
||||
|
||||
complete_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => count_carry(2),
|
||||
I1 => en_16_x_baud,
|
||||
O => decode_Tx_complete );
|
||||
|
||||
Tx_complete_reg: FD
|
||||
port map ( D => decode_Tx_complete,
|
||||
Q => Tx_complete,
|
||||
C => clk);
|
||||
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCUART_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,77 @@
|
||||
-- Test Bench for kcpsm3_int_test.vhd
|
||||
--
|
||||
-- Ken Chapman - Xilinx Ltd - June 2003
|
||||
--
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY testbench IS
|
||||
END testbench;
|
||||
|
||||
ARCHITECTURE behavior OF testbench IS
|
||||
|
||||
-- Design to be tested
|
||||
|
||||
COMPONENT kcpsm3_int_test
|
||||
Port ( counter : out std_logic_vector(7 downto 0);
|
||||
waveforms : out std_logic_vector(7 downto 0);
|
||||
interrupt_event : in std_logic;
|
||||
clk : in std_logic);
|
||||
END COMPONENT;
|
||||
|
||||
-- signals to connect kcpsm3_int_test
|
||||
|
||||
SIGNAL counter : std_logic_vector(7 downto 0);
|
||||
SIGNAL waveforms : std_logic_vector(7 downto 0);
|
||||
SIGNAL interrupt_event : std_logic := '0';
|
||||
SIGNAL clk : std_logic := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Define the unit under test
|
||||
|
||||
uut: kcpsm3_int_test
|
||||
port map ( counter => counter,
|
||||
waveforms => waveforms,
|
||||
interrupt_event => interrupt_event,
|
||||
clk => clk);
|
||||
|
||||
|
||||
-- Test Bench begins
|
||||
|
||||
-- Nominal 50MHz clock which also defines number of cycles in simulation
|
||||
test_clock: process
|
||||
variable max_cycles : integer :=400;
|
||||
variable cycle_count : integer := 0;
|
||||
begin
|
||||
-- Define the clock cycles and the clock cycle counter
|
||||
while cycle_count < max_cycles loop
|
||||
clk <= '0';
|
||||
wait for 10 ns;
|
||||
clk <= '1';
|
||||
cycle_count := cycle_count + 1;
|
||||
wait for 10 ns;
|
||||
|
||||
--Now define stimulus relative to a given clock cycle
|
||||
|
||||
case cycle_count is
|
||||
|
||||
when 30 => interrupt_event <= '1';
|
||||
|
||||
when 67 => interrupt_event <= '1';
|
||||
|
||||
when 183 => interrupt_event <= '1';
|
||||
|
||||
when others => interrupt_event <= '0'; -- no interrupt
|
||||
|
||||
end case;
|
||||
|
||||
end loop;
|
||||
|
||||
wait; -- end of simulation.
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,148 @@
|
||||
-- 9-Bit UART Receiver with integral 16 byte FIFO buffer
|
||||
--
|
||||
-- 9 data bits, no parity, 1 stop bit
|
||||
-- or
|
||||
-- 8 data bits, parity, 1 stop bit
|
||||
-- where the value of the parity bit must be checked externally and is provided as data_out(8).
|
||||
--
|
||||
-- Version : 1.00 (derived from uart_rx version 1.00)
|
||||
-- Version Date : 11th February 2005
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART9_RX
|
||||
--
|
||||
entity uart9_rx is
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end uart9_rx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART9_RX
|
||||
--
|
||||
architecture macro_level_definition of uart9_rx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART9_RX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART Receiver
|
||||
--
|
||||
component kcuart9_rx
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
data_strobe : out std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo_16x9
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART9_RX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal uart_data_out : std_logic_vector(8 downto 0);
|
||||
signal fifo_write : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART9_RX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- Constant (K) Compact UART 9-bit Receiver
|
||||
|
||||
receiver: kcuart9_rx
|
||||
port map ( serial_in => serial_in,
|
||||
data_out => uart_data_out,
|
||||
data_strobe => fifo_write,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
clk => clk );
|
||||
|
||||
-- 9-bit 'Bucket Brigade' FIFO
|
||||
|
||||
buf: bbfifo_16x9
|
||||
port map ( data_in => uart_data_out,
|
||||
data_out => data_out,
|
||||
reset => reset_buffer,
|
||||
write => fifo_write,
|
||||
read => read_buffer,
|
||||
full => buffer_full,
|
||||
half_full => buffer_half_full,
|
||||
data_present => buffer_data_present,
|
||||
clk => clk);
|
||||
|
||||
end macro_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART9_RX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,150 @@
|
||||
-- 9-Bit UART Transmitter with integral 16 byte FIFO buffer
|
||||
--
|
||||
-- 9 data bits, no parity, 1 stop bit
|
||||
-- or
|
||||
-- 8 data bits, parity, 1 stop bit
|
||||
-- where the value of the parity bit must be computed externally and provided as data_in(8).
|
||||
--
|
||||
-- Version : 1.00 (derived from uart_tx version 1.00)
|
||||
-- Version Date : 10th February 2005
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART9_TX
|
||||
--
|
||||
entity uart9_tx is
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end uart9_tx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART_TX
|
||||
--
|
||||
architecture macro_level_definition of uart9_tx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART9_TX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART 9-bit Transmitter
|
||||
--
|
||||
component kcuart9_tx
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
send_character : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
tx_complete : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- 9-bit 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo_16x9
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART9_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal fifo_data_out : std_logic_vector(8 downto 0);
|
||||
signal fifo_data_present : std_logic;
|
||||
signal fifo_read : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- Constant (K) Compact UART 9-bit Transmitter
|
||||
|
||||
transmitter: kcuart9_tx
|
||||
port map ( data_in => fifo_data_out,
|
||||
send_character => fifo_data_present,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => serial_out,
|
||||
Tx_complete => fifo_read,
|
||||
clk => clk);
|
||||
|
||||
-- 9-bit 'Bucket Brigade' FIFO
|
||||
|
||||
buf: bbfifo_16x9
|
||||
port map ( data_in => data_in,
|
||||
data_out => fifo_data_out,
|
||||
reset => reset_buffer,
|
||||
write => write_buffer,
|
||||
read => fifo_read,
|
||||
full => buffer_full,
|
||||
half_full => buffer_half_full,
|
||||
data_present => fifo_data_present,
|
||||
clk => clk);
|
||||
|
||||
end macro_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,352 @@
|
||||
--
|
||||
-- KCPSM3 reference design - Real Time Clock with UART communications
|
||||
--
|
||||
-- Ken Chapman - Xilinx Ltd - October 2003
|
||||
--
|
||||
-- The design demonstrates the following:-
|
||||
-- Connection of KCPSM3 to Program ROM
|
||||
-- Connection of UART macros supplied with PicoBlaze with
|
||||
-- Baud rate generation
|
||||
-- Definition of input and output ports with
|
||||
-- Minimum decoding
|
||||
-- Pipelining where appropriate
|
||||
-- Interrupt circuit with
|
||||
-- Simple fixed period timer
|
||||
-- Automatic clearing using interrupt acknowledge from KCPSM3
|
||||
--
|
||||
-- The design is set up for a 55MHz system clock and UART communications rate of 38400 baud.
|
||||
-- Please read design documentation to modify to your own requirements.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2003. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Furthermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
--
|
||||
entity uart_clock is
|
||||
Port ( tx : out std_logic;
|
||||
rx : in std_logic;
|
||||
alarm : out std_logic;
|
||||
clk : in std_logic);
|
||||
end uart_clock;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of test architecture
|
||||
--
|
||||
architecture Behavioral of uart_clock is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- declaration of KCPSM3
|
||||
--
|
||||
component kcpsm3
|
||||
Port ( address : out std_logic_vector(9 downto 0);
|
||||
instruction : in std_logic_vector(17 downto 0);
|
||||
port_id : out std_logic_vector(7 downto 0);
|
||||
write_strobe : out std_logic;
|
||||
out_port : out std_logic_vector(7 downto 0);
|
||||
read_strobe : out std_logic;
|
||||
in_port : in std_logic_vector(7 downto 0);
|
||||
interrupt : in std_logic;
|
||||
interrupt_ack : out std_logic;
|
||||
reset : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of program ROM
|
||||
--
|
||||
component uclock
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of UART transmitter with integral 16 byte FIFO buffer
|
||||
--
|
||||
component uart_tx
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of UART Receiver with integral 16 byte FIFO buffer
|
||||
--
|
||||
component uart_rx
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used to connect KCPSM3 to program ROM and I/O logic
|
||||
--
|
||||
signal address : std_logic_vector(9 downto 0);
|
||||
signal instruction : std_logic_vector(17 downto 0);
|
||||
signal port_id : std_logic_vector(7 downto 0);
|
||||
signal out_port : std_logic_vector(7 downto 0);
|
||||
signal in_port : std_logic_vector(7 downto 0);
|
||||
signal write_strobe : std_logic;
|
||||
signal read_strobe : std_logic;
|
||||
signal interrupt : std_logic;
|
||||
signal interrupt_ack : std_logic;
|
||||
--
|
||||
-- Signals for connection of peripherals
|
||||
--
|
||||
signal uart_status_port : std_logic_vector(7 downto 0);
|
||||
--
|
||||
-- Signals to form an timer generating an interrupt every microsecond
|
||||
--
|
||||
signal timer_count : integer range 0 to 63 :=0;
|
||||
signal timer_pulse : std_logic;
|
||||
--
|
||||
-- Signals for UART connections
|
||||
--
|
||||
signal baud_count : integer range 0 to 255 :=0;
|
||||
signal en_16_x_baud : std_logic;
|
||||
signal write_to_uart : std_logic;
|
||||
signal tx_full : std_logic;
|
||||
signal tx_half_full : std_logic;
|
||||
signal read_from_uart : std_logic;
|
||||
signal rx_data : std_logic_vector(7 downto 0);
|
||||
signal rx_data_present : std_logic;
|
||||
signal rx_full : std_logic;
|
||||
signal rx_half_full : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of circuit description
|
||||
--
|
||||
begin
|
||||
--
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
-- KCPSM3 and the program memory
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
|
||||
processor: kcpsm3
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
port_id => port_id,
|
||||
write_strobe => write_strobe,
|
||||
out_port => out_port,
|
||||
read_strobe => read_strobe,
|
||||
in_port => in_port,
|
||||
interrupt => interrupt,
|
||||
interrupt_ack => interrupt_ack,
|
||||
reset => '0',
|
||||
clk => clk);
|
||||
|
||||
program_rom: uclock
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
clk => clk);
|
||||
|
||||
--
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
-- Interrupt
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
--
|
||||
-- Interrupt is a generated once every 55 clock cycles to provide a 1us reference.
|
||||
-- Interrupt is automatically cleared by interrupt acknowledgment from KCPSM3.
|
||||
--
|
||||
|
||||
Timer: process(clk)
|
||||
begin
|
||||
|
||||
if clk'event and clk='1' then
|
||||
|
||||
if timer_count=54 then
|
||||
timer_count <= 0;
|
||||
timer_pulse <= '1';
|
||||
else
|
||||
timer_count <= timer_count + 1;
|
||||
timer_pulse <= '0';
|
||||
end if;
|
||||
|
||||
if interrupt_ack = '1' then
|
||||
interrupt <= '0';
|
||||
elsif timer_pulse = '1' then
|
||||
interrupt <= '1';
|
||||
else
|
||||
interrupt <= interrupt;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end process Timer;
|
||||
|
||||
|
||||
--
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
-- KCPSM3 input ports
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
--
|
||||
-- UART FIFO status signals to form a bus
|
||||
--
|
||||
|
||||
uart_status_port <= "000" & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
|
||||
|
||||
--
|
||||
-- The inputs connect via a pipelined multiplexer
|
||||
--
|
||||
|
||||
input_ports: process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
|
||||
case port_id(0) is
|
||||
|
||||
|
||||
-- read UART status at address 00 hex
|
||||
when '0' => in_port <= uart_status_port;
|
||||
|
||||
-- read UART receive data at address 01 hex
|
||||
when '1' => in_port <= rx_data;
|
||||
|
||||
-- Don't care used for all other addresses to ensure minimum logic implementation
|
||||
when others => in_port <= "XXXXXXXX";
|
||||
|
||||
end case;
|
||||
|
||||
-- Form read strobe for UART receiver FIFO buffer.
|
||||
-- The fact that the read strobe will occur after the actual data is read by
|
||||
-- the KCPSM3 is acceptable because it is really means 'I have read you'!
|
||||
|
||||
read_from_uart <= read_strobe and port_id(0);
|
||||
|
||||
end if;
|
||||
|
||||
end process input_ports;
|
||||
|
||||
|
||||
--
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
-- KCPSM3 output ports
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
|
||||
-- adding the output registers to the clock processor
|
||||
|
||||
output_ports: process(clk)
|
||||
begin
|
||||
|
||||
if clk'event and clk='1' then
|
||||
if write_strobe='1' then
|
||||
|
||||
-- Alarm register at address 00 hex with data bit0 providing control
|
||||
|
||||
if port_id(0)='0' then
|
||||
alarm <= out_port(0);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end process output_ports;
|
||||
|
||||
--
|
||||
-- write to UART transmitter FIFO buffer at address 01 hex.
|
||||
-- This is a combinatorial decode because the FIFO is the 'port register'.
|
||||
--
|
||||
|
||||
write_to_uart <= write_strobe and port_id(0);
|
||||
|
||||
--
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
-- UART
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
|
||||
-- Each contains an embedded 16-byte FIFO buffer.
|
||||
--
|
||||
|
||||
transmit: uart_tx
|
||||
port map ( data_in => out_port,
|
||||
write_buffer => write_to_uart,
|
||||
reset_buffer => '0',
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => tx,
|
||||
buffer_full => tx_full,
|
||||
buffer_half_full => tx_half_full,
|
||||
clk => clk );
|
||||
|
||||
receive: uart_rx
|
||||
port map ( serial_in => rx,
|
||||
data_out => rx_data,
|
||||
read_buffer => read_from_uart,
|
||||
reset_buffer => '0',
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
buffer_data_present => rx_data_present,
|
||||
buffer_full => rx_full,
|
||||
buffer_half_full => rx_half_full,
|
||||
clk => clk );
|
||||
|
||||
--
|
||||
-- Set baud rate to 38400 for the UART communications
|
||||
-- Requires en_16_x_baud to be 614400Hz which is a single cycle pulse every 163 cycles at 100MHz
|
||||
--
|
||||
-- NOTE : If the highest value for baud_count exceeds 127 you will need to adjust
|
||||
-- the range of integers in the signal declaration for baud_count.
|
||||
--
|
||||
|
||||
baud_timer: process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
if baud_count=162 then
|
||||
baud_count <= 0;
|
||||
en_16_x_baud <= '1';
|
||||
else
|
||||
baud_count <= baud_count + 1;
|
||||
en_16_x_baud <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process baud_timer;
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE uart_clock.vhd
|
||||
--
|
||||
------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,146 @@
|
||||
-- UART Receiver with integral 16 byte FIFO buffer
|
||||
--
|
||||
-- 8 bit, no parity, 1 stop bit
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 16th October 2002
|
||||
--
|
||||
-- Start of design entry : 16th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART_RX
|
||||
--
|
||||
entity uart_rx is
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end uart_rx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART_RX
|
||||
--
|
||||
architecture macro_level_definition of uart_rx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART_RX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART Receiver
|
||||
--
|
||||
component kcuart_rx
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
data_strobe : out std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo_16x8
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART_RX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal uart_data_out : std_logic_vector(7 downto 0);
|
||||
signal fifo_write : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART_RX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- 8 to 1 multiplexer to convert parallel data to serial
|
||||
|
||||
kcuart: kcuart_rx
|
||||
port map ( serial_in => serial_in,
|
||||
data_out => uart_data_out,
|
||||
data_strobe => fifo_write,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
clk => clk );
|
||||
|
||||
|
||||
buf: bbfifo_16x8
|
||||
port map ( data_in => uart_data_out,
|
||||
data_out => data_out,
|
||||
reset => reset_buffer,
|
||||
write => fifo_write,
|
||||
read => read_buffer,
|
||||
full => buffer_full,
|
||||
half_full => buffer_half_full,
|
||||
data_present => buffer_data_present,
|
||||
clk => clk);
|
||||
|
||||
end macro_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART_RX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,148 @@
|
||||
-- UART Transmitter with integral 16 byte FIFO buffer
|
||||
--
|
||||
-- 8 bit, no parity, 1 stop bit
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 14th October 2002
|
||||
--
|
||||
-- Start of design entry : 14th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART_TX
|
||||
--
|
||||
entity uart_tx is
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end uart_tx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART_TX
|
||||
--
|
||||
architecture macro_level_definition of uart_tx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART_TX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART Transmitter
|
||||
--
|
||||
component kcuart_tx
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
send_character : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
Tx_complete : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo_16x8
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal fifo_data_out : std_logic_vector(7 downto 0);
|
||||
signal fifo_data_present : std_logic;
|
||||
signal fifo_read : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- 8 to 1 multiplexer to convert parallel data to serial
|
||||
|
||||
kcuart: kcuart_tx
|
||||
port map ( data_in => fifo_data_out,
|
||||
send_character => fifo_data_present,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => serial_out,
|
||||
Tx_complete => fifo_read,
|
||||
clk => clk);
|
||||
|
||||
|
||||
buf: bbfifo_16x8
|
||||
port map ( data_in => data_in,
|
||||
data_out => fifo_data_out,
|
||||
reset => reset_buffer,
|
||||
write => write_buffer,
|
||||
read => fifo_read,
|
||||
full => buffer_full,
|
||||
half_full => buffer_half_full,
|
||||
data_present => fifo_data_present,
|
||||
clk => clk);
|
||||
|
||||
end macro_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,34 @@
|
||||
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:4
|
||||
-g CclkPin:PullUp
|
||||
-g M0Pin:PullUp
|
||||
-g M1Pin:PullUp
|
||||
-g M2Pin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g InitPin:Pullup
|
||||
-g CsPin:Pullup
|
||||
-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
||||
-g RdWrPin:Pullup
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullNone
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g DCMShutDown:Disable
|
||||
-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:CClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,2 @@
|
||||
vhdl work "kcpsm3.vhd"
|
||||
vhdl work "embedded_kcpsm3.vhd"
|
||||
@@ -0,0 +1,55 @@
|
||||
set -tmpdir ./xst/projnav.tmp
|
||||
set -xsthdpdir ./xst
|
||||
run
|
||||
-ifn embedded_kcpsm3.prj
|
||||
-ifmt mixed
|
||||
-ofn embedded_kcpsm3
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top embedded_kcpsm3
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-lso embedded_kcpsm3.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,3 @@
|
||||
vhdl work "kcpsm3.vhd"
|
||||
vhdl work "E:/work/VHDL/XilinxISE/Projects/PicoBlaze/Assembler/INT_TEST.VHD"
|
||||
vhdl work "kcpsm3_int_test.vhd"
|
||||
@@ -0,0 +1,55 @@
|
||||
set -tmpdir ./xst/projnav.tmp
|
||||
set -xsthdpdir ./xst
|
||||
run
|
||||
-ifn kcpsm3_int_test.prj
|
||||
-ifmt mixed
|
||||
-ofn kcpsm3_int_test
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top kcpsm3_int_test
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-lso kcpsm3_int_test.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,40 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
# Bus clock nets
|
||||
NET sys_clk_in TNM_NET = "sys_clk_in";
|
||||
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
|
||||
|
||||
NET sys_clk_in LOC = AE14;
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET sys_rst_in LOC = D6;
|
||||
NET sys_rst_in PULLUP;
|
||||
NET sys_rst_in TIG;
|
||||
|
||||
NET sys_rx LOC = W2;
|
||||
NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET sys_tx LOC = W1;
|
||||
NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET sys_tx TIG;
|
||||
|
||||
NET sys_alarm LOC = G5; #GPLED0
|
||||
NET sys_alarm TIG;
|
||||
NET sys_alarm SLEW = SLOW;
|
||||
NET sys_alarm DRIVE = 2;
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Oct 01 18:35:41 Westeuropäische Sommerzeit 2005
|
||||
##
|
||||
vlib work
|
||||
vcom -93 -explicit kcpsm3.vhd
|
||||
vcom -93 -explicit ./Assembler/INT_TEST.VHD
|
||||
vcom -93 -explicit kcpsm3_int_test.vhd
|
||||
vcom -93 -explicit test_bench.vhd
|
||||
vsim -t 1ps -lib work testbench
|
||||
do {testbench.udo}
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for Post-PAR Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-PAR Model
|
||||
vcom -explicit -93 "E:/work/VHDL/XilinxISE/Projects/PicoBlaze/netgen/par/kcpsm3_int_test_timesim.vhd"
|
||||
vcom -explicit -93 "test_bench.vhd"
|
||||
vsim -t 1ps -sdfmax /UUT=E:/work/VHDL/XilinxISE/Projects/PicoBlaze/netgen/par/kcpsm3_int_test_timesim.sdf -lib work testbench
|
||||
do {testbench.udo}
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 10us
|
||||
## End
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: testbench.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,8 @@
|
||||
vhdl work "kcuart_tx.vhd"
|
||||
vhdl work "kcuart_rx.vhd"
|
||||
vhdl work "bbfifo_16x8.vhd"
|
||||
vhdl work "uart_tx.vhd"
|
||||
vhdl work "uart_rx.vhd"
|
||||
vhdl work "kcpsm3.vhd"
|
||||
vhdl work "E:/work/VHDL/XilinxISE/Projects/PicoBlaze/Assembler/UCLOCK.VHD"
|
||||
vhdl work "uart_clock.vhd"
|
||||
@@ -0,0 +1,4 @@
|
||||
NET "sys_clk_in" TNM_NET = "sys_clk_in";
|
||||
TIMESPEC "TS_sys_clk_in" = PERIOD "sys_clk_in" 10 ns HIGH 50 %;
|
||||
OFFSET = IN 8 ns BEFORE "sys_clk_in" ;
|
||||
OFFSET = OUT 12 ns AFTER "sys_clk_in" ;
|
||||
@@ -0,0 +1,34 @@
|
||||
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:4
|
||||
-g CclkPin:PullUp
|
||||
-g M0Pin:PullUp
|
||||
-g M1Pin:PullUp
|
||||
-g M2Pin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g InitPin:Pullup
|
||||
-g CsPin:Pullup
|
||||
-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
||||
-g RdWrPin:Pullup
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullNone
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g DCMShutDown:Disable
|
||||
-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:CClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
|
||||
@@ -0,0 +1,55 @@
|
||||
set -tmpdir ./xst/projnav.tmp
|
||||
set -xsthdpdir ./xst
|
||||
run
|
||||
-ifn uart_clock.prj
|
||||
-ifmt mixed
|
||||
-ofn uart_clock
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top uart_clock
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-lso uart_clock.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,3 @@
|
||||
vhdl work "kcuart_rx.vhd"
|
||||
vhdl work "bbfifo_16x8.vhd"
|
||||
vhdl work "uart_rx.vhd"
|
||||
@@ -0,0 +1,281 @@
|
||||
-- 'Bucket Brigade' FIFO
|
||||
-- 16 deep
|
||||
-- 8-bit data
|
||||
--
|
||||
-- Version : 1.10
|
||||
-- Version Date : 3rd December 2003
|
||||
-- Reason : '--translate' directives changed to '--synthesis translate' directives
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 14th October 2002
|
||||
--
|
||||
-- Start of design entry : 14th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for BBFIFO_16x8
|
||||
--
|
||||
entity bbfifo_16x8 is
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end bbfifo_16x8;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for BBFIFO_16x8
|
||||
--
|
||||
architecture low_level_definition of bbfifo_16x8 is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in BBFIFO_16x8
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal pointer : std_logic_vector(3 downto 0);
|
||||
signal next_count : std_logic_vector(3 downto 0);
|
||||
signal half_count : std_logic_vector(3 downto 0);
|
||||
signal count_carry : std_logic_vector(2 downto 0);
|
||||
|
||||
signal pointer_zero : std_logic;
|
||||
signal pointer_full : std_logic;
|
||||
signal decode_data_present : std_logic;
|
||||
signal data_present_int : std_logic;
|
||||
signal valid_write : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of zero_lut : label is "0001";
|
||||
attribute INIT of full_lut : label is "8000";
|
||||
attribute INIT of dp_lut : label is "BFA0";
|
||||
attribute INIT of valid_lut : label is "C4";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of BBFIFO_16x8 circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- SRL16E data storage
|
||||
|
||||
data_width_loop: for i in 0 to 7 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of data_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
data_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_in(i),
|
||||
CE => valid_write,
|
||||
CLK => clk,
|
||||
A0 => pointer(0),
|
||||
A1 => pointer(1),
|
||||
A2 => pointer(2),
|
||||
A3 => pointer(3),
|
||||
Q => data_out(i) );
|
||||
|
||||
end generate data_width_loop;
|
||||
|
||||
-- 4-bit counter to act as data pointer
|
||||
-- Counter is clock enabled by 'data_present'
|
||||
-- Counter will be reset when 'reset' is active
|
||||
-- Counter will increment when 'valid_write' is active
|
||||
|
||||
count_width_loop: for i in 0 to 3 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of count_lut : label is "6606";
|
||||
--
|
||||
begin
|
||||
|
||||
register_bit: FDRE
|
||||
port map ( D => next_count(i),
|
||||
Q => pointer(i),
|
||||
CE => data_present_int,
|
||||
R => reset,
|
||||
C => clk);
|
||||
|
||||
count_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"6606")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(i),
|
||||
I1 => read,
|
||||
I2 => pointer_zero,
|
||||
I3 => write,
|
||||
O => half_count(i));
|
||||
|
||||
lsb_count: if i=0 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => pointer(i),
|
||||
CI => valid_write,
|
||||
S => half_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => valid_write,
|
||||
O => next_count(i));
|
||||
|
||||
end generate lsb_count;
|
||||
|
||||
mid_count: if i>0 and i<3 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => pointer(i),
|
||||
CI => count_carry(i-1),
|
||||
S => half_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate mid_count;
|
||||
|
||||
upper_count: if i=3 generate
|
||||
begin
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate upper_count;
|
||||
|
||||
end generate count_width_loop;
|
||||
|
||||
|
||||
-- Detect when pointer is zero and maximum
|
||||
|
||||
zero_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0001")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(0),
|
||||
I1 => pointer(1),
|
||||
I2 => pointer(2),
|
||||
I3 => pointer(3),
|
||||
O => pointer_zero );
|
||||
|
||||
|
||||
full_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8000")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(0),
|
||||
I1 => pointer(1),
|
||||
I2 => pointer(2),
|
||||
I3 => pointer(3),
|
||||
O => pointer_full );
|
||||
|
||||
|
||||
-- Data Present status
|
||||
|
||||
dp_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"BFA0")
|
||||
--synthesis translate_on
|
||||
port map( I0 => write,
|
||||
I1 => read,
|
||||
I2 => pointer_zero,
|
||||
I3 => data_present_int,
|
||||
O => decode_data_present );
|
||||
|
||||
dp_flop: FDR
|
||||
port map ( D => decode_data_present,
|
||||
Q => data_present_int,
|
||||
R => reset,
|
||||
C => clk);
|
||||
|
||||
-- Valid write signal
|
||||
|
||||
valid_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"C4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer_full,
|
||||
I1 => write,
|
||||
I2 => read,
|
||||
O => valid_write );
|
||||
|
||||
|
||||
-- assign internal signals to outputs
|
||||
|
||||
full <= pointer_full;
|
||||
half_full <= pointer(3);
|
||||
data_present <= data_present_int;
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE BBFIFO_16x8.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,275 @@
|
||||
-- 'Bucket Brigade' FIFO
|
||||
-- 16 deep
|
||||
-- 9-bit data
|
||||
--
|
||||
-- Version : 1.00 (derived from bbfifo_16x8 version 1.10)
|
||||
-- Version Date : 10th February 2005
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for BBFIFO_16x9
|
||||
--
|
||||
entity bbfifo_16x9 is
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end bbfifo_16x9;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for BBFIFO_16x9
|
||||
--
|
||||
architecture low_level_definition of bbfifo_16x9 is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in BBFIFO_16x9
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal pointer : std_logic_vector(3 downto 0);
|
||||
signal next_count : std_logic_vector(3 downto 0);
|
||||
signal half_count : std_logic_vector(3 downto 0);
|
||||
signal count_carry : std_logic_vector(2 downto 0);
|
||||
|
||||
signal pointer_zero : std_logic;
|
||||
signal pointer_full : std_logic;
|
||||
signal decode_data_present : std_logic;
|
||||
signal data_present_int : std_logic;
|
||||
signal valid_write : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of zero_lut : label is "0001";
|
||||
attribute INIT of full_lut : label is "8000";
|
||||
attribute INIT of dp_lut : label is "BFA0";
|
||||
attribute INIT of valid_lut : label is "C4";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of BBFIFO_16x9 circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- SRL16E data storage
|
||||
|
||||
data_width_loop: for i in 0 to 8 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of data_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
data_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_in(i),
|
||||
CE => valid_write,
|
||||
CLK => clk,
|
||||
A0 => pointer(0),
|
||||
A1 => pointer(1),
|
||||
A2 => pointer(2),
|
||||
A3 => pointer(3),
|
||||
Q => data_out(i) );
|
||||
|
||||
end generate data_width_loop;
|
||||
|
||||
-- 4-bit counter to act as data pointer
|
||||
-- Counter is clock enabled by 'data_present'
|
||||
-- Counter will be reset when 'reset' is active
|
||||
-- Counter will increment when 'valid_write' is active
|
||||
|
||||
count_width_loop: for i in 0 to 3 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of count_lut : label is "6606";
|
||||
--
|
||||
begin
|
||||
|
||||
register_bit: FDRE
|
||||
port map ( D => next_count(i),
|
||||
Q => pointer(i),
|
||||
CE => data_present_int,
|
||||
R => reset,
|
||||
C => clk);
|
||||
|
||||
count_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"6606")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(i),
|
||||
I1 => read,
|
||||
I2 => pointer_zero,
|
||||
I3 => write,
|
||||
O => half_count(i));
|
||||
|
||||
lsb_count: if i=0 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => pointer(i),
|
||||
CI => valid_write,
|
||||
S => half_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => valid_write,
|
||||
O => next_count(i));
|
||||
|
||||
end generate lsb_count;
|
||||
|
||||
mid_count: if i>0 and i<3 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => pointer(i),
|
||||
CI => count_carry(i-1),
|
||||
S => half_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate mid_count;
|
||||
|
||||
upper_count: if i=3 generate
|
||||
begin
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => half_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate upper_count;
|
||||
|
||||
end generate count_width_loop;
|
||||
|
||||
|
||||
-- Detect when pointer is zero and maximum
|
||||
|
||||
zero_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0001")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(0),
|
||||
I1 => pointer(1),
|
||||
I2 => pointer(2),
|
||||
I3 => pointer(3),
|
||||
O => pointer_zero );
|
||||
|
||||
|
||||
full_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8000")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer(0),
|
||||
I1 => pointer(1),
|
||||
I2 => pointer(2),
|
||||
I3 => pointer(3),
|
||||
O => pointer_full );
|
||||
|
||||
|
||||
-- Data Present status
|
||||
|
||||
dp_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"BFA0")
|
||||
--synthesis translate_on
|
||||
port map( I0 => write,
|
||||
I1 => read,
|
||||
I2 => pointer_zero,
|
||||
I3 => data_present_int,
|
||||
O => decode_data_present );
|
||||
|
||||
dp_flop: FDR
|
||||
port map ( D => decode_data_present,
|
||||
Q => data_present_int,
|
||||
R => reset,
|
||||
C => clk);
|
||||
|
||||
-- Valid write signal
|
||||
|
||||
valid_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"C4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => pointer_full,
|
||||
I1 => write,
|
||||
I2 => read,
|
||||
O => valid_write );
|
||||
|
||||
|
||||
-- assign internal signals to outputs
|
||||
|
||||
full <= pointer_full;
|
||||
half_full <= pointer(3);
|
||||
data_present <= data_present_int;
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE BBFIFO_16x9.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,106 @@
|
||||
--
|
||||
-- EMBEDDED_KCPSM3.VHD
|
||||
--
|
||||
-- Ken Chapman - Xilinx Ltd - 3rd June 2003
|
||||
--
|
||||
-- This file instantiates the KCPSM3 processor macro and connects the
|
||||
-- program ROM.
|
||||
--
|
||||
-- NOTE: The name of the program ROM will probably need to be changed to
|
||||
-- reflect the name of the program (PSM) file applied to the assembler.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
--
|
||||
entity embedded_kcpsm3 is
|
||||
Port ( port_id : out std_logic_vector(7 downto 0);
|
||||
write_strobe : out std_logic;
|
||||
read_strobe : out std_logic;
|
||||
out_port : out std_logic_vector(7 downto 0);
|
||||
in_port : in std_logic_vector(7 downto 0);
|
||||
interrupt : in std_logic;
|
||||
interrupt_ack : out std_logic;
|
||||
reset : in std_logic;
|
||||
clk : in std_logic);
|
||||
end embedded_kcpsm3;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of test achitecture
|
||||
--
|
||||
architecture connectivity of embedded_kcpsm3 is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- declaration of KCPSM3
|
||||
--
|
||||
component kcpsm3
|
||||
Port ( address : out std_logic_vector(9 downto 0);
|
||||
instruction : in std_logic_vector(17 downto 0);
|
||||
port_id : out std_logic_vector(7 downto 0);
|
||||
write_strobe : out std_logic;
|
||||
out_port : out std_logic_vector(7 downto 0);
|
||||
read_strobe : out std_logic;
|
||||
in_port : in std_logic_vector(7 downto 0);
|
||||
interrupt : in std_logic;
|
||||
interrupt_ack : out std_logic;
|
||||
reset : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of program ROM
|
||||
--
|
||||
component prog_rom
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used to connect KCPSM3 to program ROM
|
||||
--
|
||||
signal address : std_logic_vector(9 downto 0);
|
||||
signal instruction : std_logic_vector(17 downto 0);
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of test circuit description
|
||||
--
|
||||
begin
|
||||
|
||||
processor: kcpsm3
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
port_id => port_id,
|
||||
write_strobe => write_strobe,
|
||||
out_port => out_port,
|
||||
read_strobe => read_strobe,
|
||||
in_port => in_port,
|
||||
interrupt => interrupt,
|
||||
interrupt_ack => interrupt_ack,
|
||||
reset => reset,
|
||||
clk => clk);
|
||||
|
||||
program: prog_rom
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
clk => clk);
|
||||
|
||||
end connectivity;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE EMBEDDED_KCPSM3.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,155 @@
|
||||
--
|
||||
-- Interrupt test for KCPSM3
|
||||
--
|
||||
-- Ken Chapman - Xilinx Ltd - June 2003
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
--
|
||||
entity kcpsm3_int_test is
|
||||
Port ( counter : out std_logic_vector(7 downto 0);
|
||||
waveforms : out std_logic_vector(7 downto 0);
|
||||
interrupt_event : in std_logic;
|
||||
clk : in std_logic);
|
||||
end kcpsm3_int_test;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of test achitecture
|
||||
--
|
||||
architecture Behavioral of kcpsm3_int_test is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- declaration of KCPSM3
|
||||
--
|
||||
component kcpsm3
|
||||
Port ( address : out std_logic_vector(9 downto 0);
|
||||
instruction : in std_logic_vector(17 downto 0);
|
||||
port_id : out std_logic_vector(7 downto 0);
|
||||
write_strobe : out std_logic;
|
||||
out_port : out std_logic_vector(7 downto 0);
|
||||
read_strobe : out std_logic;
|
||||
in_port : in std_logic_vector(7 downto 0);
|
||||
interrupt : in std_logic;
|
||||
interrupt_ack : out std_logic;
|
||||
reset : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of program ROM
|
||||
--
|
||||
component int_test
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used to connect KCPSM3 to program ROM and I/O logic
|
||||
--
|
||||
signal address : std_logic_vector(9 downto 0);
|
||||
signal instruction : std_logic_vector(17 downto 0);
|
||||
signal port_id : std_logic_vector(7 downto 0);
|
||||
signal out_port : std_logic_vector(7 downto 0);
|
||||
signal in_port : std_logic_vector(7 downto 0);
|
||||
signal write_strobe : std_logic;
|
||||
signal read_strobe : std_logic;
|
||||
signal interrupt : std_logic :='0';
|
||||
signal interrupt_ack : std_logic;
|
||||
signal reset : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of circuit description
|
||||
--
|
||||
begin
|
||||
|
||||
-- Inserting KCPSM3 and the program memory
|
||||
|
||||
processor: kcpsm3
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
port_id => port_id,
|
||||
write_strobe => write_strobe,
|
||||
out_port => out_port,
|
||||
read_strobe => read_strobe,
|
||||
in_port => in_port,
|
||||
interrupt => interrupt,
|
||||
interrupt_ack => interrupt_ack,
|
||||
reset => reset,
|
||||
clk => clk);
|
||||
|
||||
program: int_test
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
clk => clk);
|
||||
|
||||
-- Unused inputs on processor
|
||||
|
||||
in_port <= "00000000";
|
||||
reset <= '0';
|
||||
|
||||
-- Adding the output registers to the processor
|
||||
|
||||
IO_registers: process(clk)
|
||||
begin
|
||||
|
||||
if clk'event and clk='1' then
|
||||
|
||||
-- waveform register at address 02
|
||||
if port_id(1)='1' and write_strobe='1' then
|
||||
waveforms <= out_port;
|
||||
end if;
|
||||
|
||||
-- Interrupt Counter register at address 04
|
||||
if port_id(2)='1' and write_strobe='1' then
|
||||
counter <= out_port;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end process IO_registers;
|
||||
|
||||
|
||||
|
||||
-- Adding the interrupt input
|
||||
-- Note that the initial value of interrupt (low) is
|
||||
-- defined at signal declaration.
|
||||
|
||||
interrupt_control: process(clk)
|
||||
begin
|
||||
|
||||
if clk'event and clk='1' then
|
||||
if interrupt_ack='1' then
|
||||
interrupt <= '0';
|
||||
elsif interrupt_event='1' then
|
||||
interrupt <= '1';
|
||||
else
|
||||
interrupt <= interrupt;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end process interrupt_control;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCPSM3_INT_TEST.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,351 @@
|
||||
-- 9-Bit Constant (K) Compact UART Receiver
|
||||
--
|
||||
-- 9 data bits, no parity, 1 stop bit
|
||||
-- or
|
||||
-- 8 data bits, parity, 1 stop bit
|
||||
-- where the value of the parity bit must be checked externally and is provided as data_out(8).
|
||||
--
|
||||
-- Version : 1.00 (derived from kcuart_rx version 1.00)
|
||||
-- Version Date : 11th February 2005
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for KCUART9_RX
|
||||
--
|
||||
entity kcuart9_rx is
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
data_strobe : out std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
clk : in std_logic);
|
||||
end kcuart9_rx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for KCUART9_RX
|
||||
--
|
||||
architecture low_level_definition of kcuart9_rx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in KCUART9_RX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal sync_serial : std_logic;
|
||||
signal stop_bit : std_logic;
|
||||
signal data_int : std_logic_vector(8 downto 0);
|
||||
signal data_delay : std_logic_vector(8 downto 0);
|
||||
signal start_delay : std_logic;
|
||||
signal start_bit : std_logic;
|
||||
signal edge_delay : std_logic;
|
||||
signal start_edge : std_logic;
|
||||
signal decode_valid_char : std_logic;
|
||||
signal valid_char : std_logic;
|
||||
signal decode_purge : std_logic;
|
||||
signal purge : std_logic;
|
||||
signal valid_srl_delay : std_logic_vector(9 downto 0);
|
||||
signal valid_reg_delay : std_logic_vector(9 downto 0);
|
||||
signal decode_data_strobe : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of start_srl : label is "0000";
|
||||
attribute INIT of edge_srl : label is "0000";
|
||||
attribute INIT of valid_lut : label is "0040";
|
||||
attribute INIT of purge_lut : label is "54";
|
||||
attribute INIT of strobe_lut : label is "8";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of KCUART9_RX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- Synchronise input serial data to system clock
|
||||
|
||||
sync_reg: FD
|
||||
port map ( D => serial_in,
|
||||
Q => sync_serial,
|
||||
C => clk);
|
||||
|
||||
stop_reg: FD
|
||||
port map ( D => sync_serial,
|
||||
Q => stop_bit,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Data delays to capture data at 16 times baud rate
|
||||
-- Each SRL16E is followed by a flip-flop for best timing
|
||||
|
||||
data_loop: for i in 0 to 8 generate
|
||||
begin
|
||||
|
||||
lsbs: if i<8 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_int(i+1),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => data_delay(i) );
|
||||
|
||||
end generate lsbs;
|
||||
|
||||
msb: if i=8 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => stop_bit,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => data_delay(i) );
|
||||
|
||||
end generate msb;
|
||||
|
||||
data_reg: FDE
|
||||
port map ( D => data_delay(i),
|
||||
Q => data_int(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
end generate data_loop;
|
||||
|
||||
-- Assign internal signals to outputs
|
||||
|
||||
data_out <= data_int;
|
||||
|
||||
-- Data delays to capture start bit at 16 time baud rate
|
||||
|
||||
start_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_int(0),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => start_delay );
|
||||
|
||||
start_reg: FDE
|
||||
port map ( D => start_delay,
|
||||
Q => start_bit,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Data delays to capture start bit leading edge at 16 time baud rate
|
||||
-- Delay ensures data is captured at mid-bit position
|
||||
|
||||
edge_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => start_bit,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '0',
|
||||
A2 => '1',
|
||||
A3 => '0',
|
||||
Q => edge_delay );
|
||||
|
||||
edge_reg: FDE
|
||||
port map ( D => edge_delay,
|
||||
Q => start_edge,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Detect a valid character
|
||||
|
||||
valid_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0040")
|
||||
--synthesis translate_on
|
||||
port map( I0 => purge,
|
||||
I1 => stop_bit,
|
||||
I2 => start_edge,
|
||||
I3 => edge_delay,
|
||||
O => decode_valid_char );
|
||||
|
||||
valid_reg: FDE
|
||||
port map ( D => decode_valid_char,
|
||||
Q => valid_char,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Purge of data status
|
||||
|
||||
purge_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"54")
|
||||
--synthesis translate_on
|
||||
port map( I0 => valid_reg_delay(9),
|
||||
I1 => valid_char,
|
||||
I2 => purge,
|
||||
O => decode_purge );
|
||||
|
||||
purge_reg: FDE
|
||||
port map ( D => decode_purge,
|
||||
Q => purge,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Delay of valid_char pulse of length equivalent to the time taken
|
||||
-- to purge data shift register of all data which has been used.
|
||||
-- Requires 10x16 + 8 delays which is achieved by packing of SRL16E with
|
||||
-- up to 16 delays and utilising the dedicated flip flop in each stage.
|
||||
|
||||
valid_loop: for i in 0 to 9 generate
|
||||
begin
|
||||
|
||||
lsb: if i=0 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay14_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay14_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => valid_char,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '0',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => valid_srl_delay(i) );
|
||||
|
||||
end generate lsb;
|
||||
|
||||
msbs: if i>0 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay16_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay16_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => valid_reg_delay(i-1),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => valid_srl_delay(i) );
|
||||
|
||||
end generate msbs;
|
||||
|
||||
data_reg: FDE
|
||||
port map ( D => valid_srl_delay(i),
|
||||
Q => valid_reg_delay(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
end generate valid_loop;
|
||||
|
||||
-- Form data strobe
|
||||
|
||||
strobe_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => valid_char,
|
||||
I1 => en_16_x_baud,
|
||||
O => decode_data_strobe );
|
||||
|
||||
strobe_reg: FD
|
||||
port map ( D => decode_data_strobe,
|
||||
Q => data_strobe,
|
||||
C => clk);
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCUART9_RX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,433 @@
|
||||
-- Constant (K) Compact UART Transmitter
|
||||
--
|
||||
-- 9-Bit UART Transmitter
|
||||
--
|
||||
-- 9 data bits, no parity, 1 stop bit
|
||||
-- or
|
||||
-- 8 data bits, parity, 1 stop bit
|
||||
-- where the value of the parity bit must be computed externally and provided as data_in(8).
|
||||
--
|
||||
-- NOTE : This macro is intended to be attached to bbfifo_16x9 and operation requires the
|
||||
-- interaction of signals to and from that FIFO buffer to work correctly.
|
||||
--
|
||||
-- Version : 1.00 (derived from kcuart_tx version 1.10)
|
||||
-- Version Date : 10th February 2005
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for KCUART9_TX
|
||||
--
|
||||
entity kcuart9_tx is
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
send_character : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
tx_complete : out std_logic;
|
||||
clk : in std_logic);
|
||||
end kcuart9_tx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for KCUART9_TX
|
||||
--
|
||||
architecture low_level_definition of kcuart9_tx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in KCUART9_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal data_01 : std_logic;
|
||||
signal data_23 : std_logic;
|
||||
signal data_45 : std_logic;
|
||||
signal data_67 : std_logic;
|
||||
signal data_0123 : std_logic;
|
||||
signal data_4567 : std_logic;
|
||||
signal data_01234567 : std_logic;
|
||||
signal data_01234567_reg : std_logic;
|
||||
|
||||
signal data8_buf : std_logic;
|
||||
signal force_serial : std_logic;
|
||||
signal next_serial : std_logic;
|
||||
|
||||
signal bit_count : std_logic_vector(2 downto 0);
|
||||
signal next_bit_count : std_logic_vector(2 downto 0);
|
||||
signal half_bit_count : std_logic_vector(2 downto 0);
|
||||
signal bit_count_cy : std_logic_vector(1 downto 0);
|
||||
|
||||
signal baud_count : std_logic_vector(3 downto 0);
|
||||
signal next_baud_count : std_logic_vector(3 downto 0);
|
||||
signal half_baud_count : std_logic_vector(3 downto 0);
|
||||
signal baud_count_cy : std_logic_vector(3 downto 0);
|
||||
signal tx_bit_en : std_logic;
|
||||
|
||||
signal decode7 : std_logic;
|
||||
signal sel_last_bit : std_logic;
|
||||
signal parity_bit : std_logic;
|
||||
signal next_transmit : std_logic;
|
||||
signal transmit : std_logic;
|
||||
signal next_tx_complete : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of mux1_lut : label is "E4";
|
||||
attribute INIT of mux2_lut : label is "E4";
|
||||
attribute INIT of mux3_lut : label is "E4";
|
||||
attribute INIT of mux4_lut : label is "E4";
|
||||
|
||||
attribute INIT of buf_data8 : label is "2";
|
||||
attribute INIT of force_lut : label is "E0FF";
|
||||
|
||||
attribute INIT of count7_lut : label is "80";
|
||||
attribute INIT of transmit_lut : label is "32";
|
||||
attribute INIT of complete_lut : label is "8";
|
||||
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of KCUART9_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- 8 to 1 multiplexer to convert parallel data to serial
|
||||
|
||||
mux1_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(0),
|
||||
I1 => data_in(0),
|
||||
I2 => data_in(1),
|
||||
O => data_01 );
|
||||
|
||||
mux2_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(0),
|
||||
I1 => data_in(2),
|
||||
I2 => data_in(3),
|
||||
O => data_23 );
|
||||
|
||||
mux3_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(0),
|
||||
I1 => data_in(4),
|
||||
I2 => data_in(5),
|
||||
O => data_45 );
|
||||
|
||||
mux4_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(0),
|
||||
I1 => data_in(6),
|
||||
I2 => data_in(7),
|
||||
O => data_67 );
|
||||
|
||||
|
||||
mux5_muxf5: MUXF5
|
||||
port map( I1 => data_23,
|
||||
I0 => data_01,
|
||||
S => bit_count(1),
|
||||
O => data_0123 );
|
||||
|
||||
mux6_muxf5: MUXF5
|
||||
port map( I1 => data_67,
|
||||
I0 => data_45,
|
||||
S => bit_count(1),
|
||||
O => data_4567 );
|
||||
|
||||
mux7_muxf6: MUXF6
|
||||
port map( I1 => data_4567,
|
||||
I0 => data_0123,
|
||||
S => bit_count(2),
|
||||
O => data_01234567 );
|
||||
|
||||
pipeline_mux: FD
|
||||
port map ( D => data_01234567,
|
||||
Q => data_01234567_reg,
|
||||
C => clk);
|
||||
|
||||
-- Serial output logic
|
||||
|
||||
buf_data8: LUT1
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"2")
|
||||
--synthesis translate_on
|
||||
port map( I0 => data_in(8),
|
||||
O => data8_buf );
|
||||
|
||||
force_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E0FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => data_01234567_reg,
|
||||
I1 => parity_bit,
|
||||
I2 => transmit,
|
||||
I3 => send_character,
|
||||
O => force_serial );
|
||||
|
||||
|
||||
mux8_muxf5: MUXF5
|
||||
port map( I1 => data8_buf,
|
||||
I0 => force_serial,
|
||||
S => sel_last_bit,
|
||||
O => next_serial );
|
||||
|
||||
-- Final output flip-flop initialised to start at '1'
|
||||
high_start: for i in 1 to 1 generate
|
||||
--
|
||||
attribute INIT : bit;
|
||||
attribute INIT of output_reg : label is '1';
|
||||
--
|
||||
begin
|
||||
|
||||
output_reg: FDE
|
||||
--synthesis translate_off
|
||||
generic map (INIT => '1')
|
||||
--synthesis translate_on
|
||||
port map ( D => next_serial,
|
||||
Q => serial_out,
|
||||
CE => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
end generate high_start;
|
||||
|
||||
|
||||
-- bit counter
|
||||
|
||||
bit_count_loop: for i in 0 to 2 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of bit_count_lut : label is "B";
|
||||
--
|
||||
begin
|
||||
|
||||
bit_reg: FDE
|
||||
port map ( D => next_bit_count(i),
|
||||
Q => bit_count(i),
|
||||
CE => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
bit_count_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"B")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(i),
|
||||
I1 => transmit,
|
||||
O => half_bit_count(i));
|
||||
|
||||
lsb_bit_count: if i=0 generate
|
||||
begin
|
||||
|
||||
bit_count_xor: XORCY
|
||||
port map( LI => half_bit_count(i),
|
||||
CI => '1',
|
||||
O => next_bit_count(i));
|
||||
|
||||
bit_count_muxcy: MUXCY
|
||||
port map( DI => '0',
|
||||
CI => '1',
|
||||
S => half_bit_count(i),
|
||||
O => bit_count_cy(i));
|
||||
|
||||
end generate lsb_bit_count;
|
||||
|
||||
upper_bit_count: if i>0 generate
|
||||
begin
|
||||
|
||||
bit_count_xor: XORCY
|
||||
port map( LI => half_bit_count(i),
|
||||
CI => bit_count_cy(i-1),
|
||||
O => next_bit_count(i));
|
||||
|
||||
middle_bit_count: if i=1 generate
|
||||
begin
|
||||
|
||||
bit_count_muxcy: MUXCY
|
||||
port map( DI => '0',
|
||||
CI => bit_count_cy(i-1),
|
||||
S => half_bit_count(i),
|
||||
O => bit_count_cy(i));
|
||||
|
||||
end generate middle_bit_count;
|
||||
|
||||
end generate upper_bit_count;
|
||||
|
||||
end generate bit_count_loop;
|
||||
|
||||
|
||||
-- baud counter
|
||||
|
||||
baud_count_loop: for i in 0 to 3 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of baud_count_lut : label is "2";
|
||||
--
|
||||
begin
|
||||
|
||||
baud_reg: FDE
|
||||
port map ( D => next_baud_count(i),
|
||||
Q => baud_count(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
baud_count_lut: LUT1
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"2")
|
||||
--synthesis translate_on
|
||||
port map( I0 => baud_count(i),
|
||||
O => half_baud_count(i));
|
||||
|
||||
lsb_baud_count: if i=0 generate
|
||||
begin
|
||||
|
||||
baud_count_xor: XORCY
|
||||
port map( LI => half_baud_count(i),
|
||||
CI => en_16_x_baud,
|
||||
O => next_baud_count(i));
|
||||
|
||||
baud_count_muxcy: MUXCY
|
||||
port map( DI => '0',
|
||||
CI => en_16_x_baud,
|
||||
S => half_baud_count(i),
|
||||
O => baud_count_cy(i));
|
||||
|
||||
end generate lsb_baud_count;
|
||||
|
||||
upper_baud_count: if i>0 generate
|
||||
begin
|
||||
|
||||
baud_count_xor: XORCY
|
||||
port map( LI => half_baud_count(i),
|
||||
CI => baud_count_cy(i-1),
|
||||
O => next_baud_count(i));
|
||||
|
||||
baud_count_muxcy: MUXCY
|
||||
port map( DI => '0',
|
||||
CI => baud_count_cy(i-1),
|
||||
S => half_baud_count(i),
|
||||
O => baud_count_cy(i));
|
||||
|
||||
end generate upper_baud_count;
|
||||
|
||||
end generate baud_count_loop;
|
||||
|
||||
bit_en_reg: FD
|
||||
port map ( D => baud_count_cy(3),
|
||||
Q => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
-- state machine
|
||||
|
||||
count7_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"80")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_count(0),
|
||||
I1 => bit_count(1),
|
||||
I2 => bit_count(2),
|
||||
O => decode7 );
|
||||
|
||||
sel_last_reg: FDE
|
||||
port map ( D => decode7,
|
||||
Q => sel_last_bit,
|
||||
CE => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
parity_reg: FDE
|
||||
port map ( D => sel_last_bit,
|
||||
Q => parity_bit,
|
||||
CE => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
transmit_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"32")
|
||||
--synthesis translate_on
|
||||
port map( I0 => send_character,
|
||||
I1 => parity_bit,
|
||||
I2 => transmit,
|
||||
O => next_transmit );
|
||||
|
||||
transmit_reg: FDE
|
||||
port map ( D => next_transmit,
|
||||
Q => transmit,
|
||||
CE => tx_bit_en,
|
||||
C => clk);
|
||||
|
||||
complete_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => parity_bit,
|
||||
I1 => tx_bit_en,
|
||||
O => next_tx_complete );
|
||||
|
||||
complete_reg: FD
|
||||
port map ( D => next_tx_complete,
|
||||
Q => tx_complete,
|
||||
C => clk);
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCUART9_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,352 @@
|
||||
-- Constant (K) Compact UART Receiver
|
||||
--
|
||||
-- Version : 1.10
|
||||
-- Version Date : 3rd December 2003
|
||||
-- Reason : '--translate' directives changed to '--synthesis translate' directives
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 16th October 2002
|
||||
--
|
||||
-- Start of design entry : 16th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for KCUART_RX
|
||||
--
|
||||
entity kcuart_rx is
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
data_strobe : out std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
clk : in std_logic);
|
||||
end kcuart_rx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for KCUART_RX
|
||||
--
|
||||
architecture low_level_definition of kcuart_rx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in KCUART_RX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal sync_serial : std_logic;
|
||||
signal stop_bit : std_logic;
|
||||
signal data_int : std_logic_vector(7 downto 0);
|
||||
signal data_delay : std_logic_vector(7 downto 0);
|
||||
signal start_delay : std_logic;
|
||||
signal start_bit : std_logic;
|
||||
signal edge_delay : std_logic;
|
||||
signal start_edge : std_logic;
|
||||
signal decode_valid_char : std_logic;
|
||||
signal valid_char : std_logic;
|
||||
signal decode_purge : std_logic;
|
||||
signal purge : std_logic;
|
||||
signal valid_srl_delay : std_logic_vector(8 downto 0);
|
||||
signal valid_reg_delay : std_logic_vector(8 downto 0);
|
||||
signal decode_data_strobe : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of start_srl : label is "0000";
|
||||
attribute INIT of edge_srl : label is "0000";
|
||||
attribute INIT of valid_lut : label is "0040";
|
||||
attribute INIT of purge_lut : label is "54";
|
||||
attribute INIT of strobe_lut : label is "8";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of KCUART_RX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- Synchronise input serial data to system clock
|
||||
|
||||
sync_reg: FD
|
||||
port map ( D => serial_in,
|
||||
Q => sync_serial,
|
||||
C => clk);
|
||||
|
||||
stop_reg: FD
|
||||
port map ( D => sync_serial,
|
||||
Q => stop_bit,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Data delays to capture data at 16 time baud rate
|
||||
-- Each SRL16E is followed by a flip-flop for best timing
|
||||
|
||||
data_loop: for i in 0 to 7 generate
|
||||
begin
|
||||
|
||||
lsbs: if i<7 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_int(i+1),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => data_delay(i) );
|
||||
|
||||
end generate lsbs;
|
||||
|
||||
msb: if i=7 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => stop_bit,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => data_delay(i) );
|
||||
|
||||
end generate msb;
|
||||
|
||||
data_reg: FDE
|
||||
port map ( D => data_delay(i),
|
||||
Q => data_int(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
end generate data_loop;
|
||||
|
||||
-- Assign internal signals to outputs
|
||||
|
||||
data_out <= data_int;
|
||||
|
||||
-- Data delays to capture start bit at 16 time baud rate
|
||||
|
||||
start_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => data_int(0),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => start_delay );
|
||||
|
||||
start_reg: FDE
|
||||
port map ( D => start_delay,
|
||||
Q => start_bit,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Data delays to capture start bit leading edge at 16 time baud rate
|
||||
-- Delay ensures data is captured at mid-bit position
|
||||
|
||||
edge_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => start_bit,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '0',
|
||||
A2 => '1',
|
||||
A3 => '0',
|
||||
Q => edge_delay );
|
||||
|
||||
edge_reg: FDE
|
||||
port map ( D => edge_delay,
|
||||
Q => start_edge,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Detect a valid character
|
||||
|
||||
valid_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0040")
|
||||
--synthesis translate_on
|
||||
port map( I0 => purge,
|
||||
I1 => stop_bit,
|
||||
I2 => start_edge,
|
||||
I3 => edge_delay,
|
||||
O => decode_valid_char );
|
||||
|
||||
valid_reg: FDE
|
||||
port map ( D => decode_valid_char,
|
||||
Q => valid_char,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Purge of data status
|
||||
|
||||
purge_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"54")
|
||||
--synthesis translate_on
|
||||
port map( I0 => valid_reg_delay(8),
|
||||
I1 => valid_char,
|
||||
I2 => purge,
|
||||
O => decode_purge );
|
||||
|
||||
purge_reg: FDE
|
||||
port map ( D => decode_purge,
|
||||
Q => purge,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Delay of valid_char pulse of length equivalent to the time taken
|
||||
-- to purge data shift register of all data which has been used.
|
||||
-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
|
||||
-- up to 16 delays and utilising the dedicated flip flop in each stage.
|
||||
|
||||
valid_loop: for i in 0 to 8 generate
|
||||
begin
|
||||
|
||||
lsb: if i=0 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay15_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay15_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => valid_char,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '0',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => valid_srl_delay(i) );
|
||||
|
||||
end generate lsb;
|
||||
|
||||
msbs: if i>0 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of delay16_srl : label is "0000";
|
||||
--
|
||||
begin
|
||||
|
||||
delay16_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => valid_reg_delay(i-1),
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '1',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => valid_srl_delay(i) );
|
||||
|
||||
end generate msbs;
|
||||
|
||||
data_reg: FDE
|
||||
port map ( D => valid_srl_delay(i),
|
||||
Q => valid_reg_delay(i),
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
end generate valid_loop;
|
||||
|
||||
-- Form data strobe
|
||||
|
||||
strobe_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => valid_char,
|
||||
I1 => en_16_x_baud,
|
||||
O => decode_data_strobe );
|
||||
|
||||
strobe_reg: FD
|
||||
port map ( D => decode_data_strobe,
|
||||
Q => data_strobe,
|
||||
C => clk);
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCUART_RX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,394 @@
|
||||
-- Constant (K) Compact UART Transmitter
|
||||
--
|
||||
-- Version : 1.10
|
||||
-- Version Date : 3rd December 2003
|
||||
-- Reason : '--translate' directives changed to '--synthesis translate' directives
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 14th October 2002
|
||||
--
|
||||
-- Start of design entry : 2nd October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for KCUART_TX
|
||||
--
|
||||
entity kcuart_tx is
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
send_character : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
Tx_complete : out std_logic;
|
||||
clk : in std_logic);
|
||||
end kcuart_tx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for KCUART_TX
|
||||
--
|
||||
architecture low_level_definition of kcuart_tx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in KCUART_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal data_01 : std_logic;
|
||||
signal data_23 : std_logic;
|
||||
signal data_45 : std_logic;
|
||||
signal data_67 : std_logic;
|
||||
signal data_0123 : std_logic;
|
||||
signal data_4567 : std_logic;
|
||||
signal data_01234567 : std_logic;
|
||||
signal bit_select : std_logic_vector(2 downto 0);
|
||||
signal next_count : std_logic_vector(2 downto 0);
|
||||
signal mask_count : std_logic_vector(2 downto 0);
|
||||
signal mask_count_carry : std_logic_vector(2 downto 0);
|
||||
signal count_carry : std_logic_vector(2 downto 0);
|
||||
signal ready_to_start : std_logic;
|
||||
signal decode_Tx_start : std_logic;
|
||||
signal Tx_start : std_logic;
|
||||
signal decode_Tx_run : std_logic;
|
||||
signal Tx_run : std_logic;
|
||||
signal decode_hot_state : std_logic;
|
||||
signal hot_state : std_logic;
|
||||
signal hot_delay : std_logic;
|
||||
signal Tx_bit : std_logic;
|
||||
signal decode_Tx_stop : std_logic;
|
||||
signal Tx_stop : std_logic;
|
||||
signal decode_Tx_complete : std_logic;
|
||||
--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Attributes to define LUT contents during implementation
|
||||
-- The information is repeated in the generic map for functional simulation--
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of mux1_lut : label is "E4FF";
|
||||
attribute INIT of mux2_lut : label is "E4FF";
|
||||
attribute INIT of mux3_lut : label is "E4FF";
|
||||
attribute INIT of mux4_lut : label is "E4FF";
|
||||
attribute INIT of ready_lut : label is "10";
|
||||
attribute INIT of start_lut : label is "0190";
|
||||
attribute INIT of run_lut : label is "1540";
|
||||
attribute INIT of hot_state_lut : label is "94";
|
||||
attribute INIT of delay14_srl : label is "0000";
|
||||
attribute INIT of stop_lut : label is "0180";
|
||||
attribute INIT of complete_lut : label is "8";
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of KCUART_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- 8 to 1 multiplexer to convert parallel data to serial
|
||||
|
||||
mux1_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(0),
|
||||
I2 => data_in(1),
|
||||
I3 => Tx_run,
|
||||
O => data_01 );
|
||||
|
||||
mux2_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(2),
|
||||
I2 => data_in(3),
|
||||
I3 => Tx_run,
|
||||
O => data_23 );
|
||||
|
||||
mux3_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(4),
|
||||
I2 => data_in(5),
|
||||
I3 => Tx_run,
|
||||
O => data_45 );
|
||||
|
||||
mux4_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"E4FF")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(0),
|
||||
I1 => data_in(6),
|
||||
I2 => data_in(7),
|
||||
I3 => Tx_run,
|
||||
O => data_67 );
|
||||
|
||||
mux5_muxf5: MUXF5
|
||||
port map( I1 => data_23,
|
||||
I0 => data_01,
|
||||
S => bit_select(1),
|
||||
O => data_0123 );
|
||||
|
||||
mux6_muxf5: MUXF5
|
||||
port map( I1 => data_67,
|
||||
I0 => data_45,
|
||||
S => bit_select(1),
|
||||
O => data_4567 );
|
||||
|
||||
mux7_muxf6: MUXF6
|
||||
port map( I1 => data_4567,
|
||||
I0 => data_0123,
|
||||
S => bit_select(2),
|
||||
O => data_01234567 );
|
||||
|
||||
-- Register serial output and force start and stop bits
|
||||
|
||||
pipeline_serial: FDRS
|
||||
port map ( D => data_01234567,
|
||||
Q => serial_out,
|
||||
R => Tx_start,
|
||||
S => Tx_stop,
|
||||
C => clk);
|
||||
|
||||
-- 3-bit counter
|
||||
-- Counter is clock enabled by en_16_x_baud
|
||||
-- Counter will be reset when 'Tx_start' is active
|
||||
-- Counter will increment when Tx_bit is active
|
||||
-- Tx_run must be active to count
|
||||
-- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow)
|
||||
|
||||
count_width_loop: for i in 0 to 2 generate
|
||||
--
|
||||
attribute INIT : string;
|
||||
attribute INIT of count_lut : label is "8";
|
||||
--
|
||||
begin
|
||||
|
||||
register_bit: FDRE
|
||||
port map ( D => next_count(i),
|
||||
Q => bit_select(i),
|
||||
CE => en_16_x_baud,
|
||||
R => Tx_start,
|
||||
C => clk);
|
||||
|
||||
count_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => bit_select(i),
|
||||
I1 => Tx_run,
|
||||
O => mask_count(i));
|
||||
|
||||
mask_and: MULT_AND
|
||||
port map( I0 => bit_select(i),
|
||||
I1 => Tx_run,
|
||||
LO => mask_count_carry(i));
|
||||
|
||||
lsb_count: if i=0 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => mask_count_carry(i),
|
||||
CI => Tx_bit,
|
||||
S => mask_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => mask_count(i),
|
||||
CI => Tx_bit,
|
||||
O => next_count(i));
|
||||
|
||||
end generate lsb_count;
|
||||
|
||||
upper_count: if i>0 generate
|
||||
begin
|
||||
|
||||
count_muxcy: MUXCY
|
||||
port map( DI => mask_count_carry(i),
|
||||
CI => count_carry(i-1),
|
||||
S => mask_count(i),
|
||||
O => count_carry(i));
|
||||
|
||||
count_xor: XORCY
|
||||
port map( LI => mask_count(i),
|
||||
CI => count_carry(i-1),
|
||||
O => next_count(i));
|
||||
|
||||
end generate upper_count;
|
||||
|
||||
end generate count_width_loop;
|
||||
|
||||
-- Ready to start decode
|
||||
|
||||
ready_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"10")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_run,
|
||||
I1 => Tx_start,
|
||||
I2 => send_character,
|
||||
O => ready_to_start );
|
||||
|
||||
-- Start bit enable
|
||||
|
||||
start_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0190")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_bit,
|
||||
I1 => Tx_stop,
|
||||
I2 => ready_to_start,
|
||||
I3 => Tx_start,
|
||||
O => decode_Tx_start );
|
||||
|
||||
Tx_start_reg: FDE
|
||||
port map ( D => decode_Tx_start,
|
||||
Q => Tx_start,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
|
||||
-- Run bit enable
|
||||
|
||||
run_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"1540")
|
||||
--synthesis translate_on
|
||||
port map( I0 => count_carry(2),
|
||||
I1 => Tx_bit,
|
||||
I2 => Tx_start,
|
||||
I3 => Tx_run,
|
||||
O => decode_Tx_run );
|
||||
|
||||
Tx_run_reg: FDE
|
||||
port map ( D => decode_Tx_run,
|
||||
Q => Tx_run,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Bit rate enable
|
||||
|
||||
hot_state_lut: LUT3
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"94")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_stop,
|
||||
I1 => ready_to_start,
|
||||
I2 => Tx_bit,
|
||||
O => decode_hot_state );
|
||||
|
||||
hot_state_reg: FDE
|
||||
port map ( D => decode_hot_state,
|
||||
Q => hot_state,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
delay14_srl: SRL16E
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0000")
|
||||
--synthesis translate_on
|
||||
port map( D => hot_state,
|
||||
CE => en_16_x_baud,
|
||||
CLK => clk,
|
||||
A0 => '1',
|
||||
A1 => '0',
|
||||
A2 => '1',
|
||||
A3 => '1',
|
||||
Q => hot_delay );
|
||||
|
||||
Tx_bit_reg: FDE
|
||||
port map ( D => hot_delay,
|
||||
Q => Tx_bit,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Stop bit enable
|
||||
|
||||
stop_lut: LUT4
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"0180")
|
||||
--synthesis translate_on
|
||||
port map( I0 => Tx_bit,
|
||||
I1 => Tx_run,
|
||||
I2 => count_carry(2),
|
||||
I3 => Tx_stop,
|
||||
O => decode_Tx_stop );
|
||||
|
||||
Tx_stop_reg: FDE
|
||||
port map ( D => decode_Tx_stop,
|
||||
Q => Tx_stop,
|
||||
CE => en_16_x_baud,
|
||||
C => clk);
|
||||
|
||||
-- Tx_complete strobe
|
||||
|
||||
complete_lut: LUT2
|
||||
--synthesis translate_off
|
||||
generic map (INIT => X"8")
|
||||
--synthesis translate_on
|
||||
port map( I0 => count_carry(2),
|
||||
I1 => en_16_x_baud,
|
||||
O => decode_Tx_complete );
|
||||
|
||||
Tx_complete_reg: FD
|
||||
port map ( D => decode_Tx_complete,
|
||||
Q => Tx_complete,
|
||||
C => clk);
|
||||
|
||||
|
||||
end low_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE KCUART_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,77 @@
|
||||
-- Test Bench for kcpsm3_int_test.vhd
|
||||
--
|
||||
-- Ken Chapman - Xilinx Ltd - June 2003
|
||||
--
|
||||
--
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
ENTITY testbench IS
|
||||
END testbench;
|
||||
|
||||
ARCHITECTURE behavior OF testbench IS
|
||||
|
||||
-- Design to be tested
|
||||
|
||||
COMPONENT kcpsm3_int_test
|
||||
Port ( counter : out std_logic_vector(7 downto 0);
|
||||
waveforms : out std_logic_vector(7 downto 0);
|
||||
interrupt_event : in std_logic;
|
||||
clk : in std_logic);
|
||||
END COMPONENT;
|
||||
|
||||
-- signals to connect kcpsm3_int_test
|
||||
|
||||
SIGNAL counter : std_logic_vector(7 downto 0);
|
||||
SIGNAL waveforms : std_logic_vector(7 downto 0);
|
||||
SIGNAL interrupt_event : std_logic := '0';
|
||||
SIGNAL clk : std_logic := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Define the unit under test
|
||||
|
||||
uut: kcpsm3_int_test
|
||||
port map ( counter => counter,
|
||||
waveforms => waveforms,
|
||||
interrupt_event => interrupt_event,
|
||||
clk => clk);
|
||||
|
||||
|
||||
-- Test Bench begins
|
||||
|
||||
-- Nominal 50MHz clock which also defines number of cycles in simulation
|
||||
test_clock: process
|
||||
variable max_cycles : integer :=400;
|
||||
variable cycle_count : integer := 0;
|
||||
begin
|
||||
-- Define the clock cycles and the clock cycle counter
|
||||
while cycle_count < max_cycles loop
|
||||
clk <= '0';
|
||||
wait for 10 ns;
|
||||
clk <= '1';
|
||||
cycle_count := cycle_count + 1;
|
||||
wait for 10 ns;
|
||||
|
||||
--Now define stimulus relative to a given clock cycle
|
||||
|
||||
case cycle_count is
|
||||
|
||||
when 30 => interrupt_event <= '1';
|
||||
|
||||
when 67 => interrupt_event <= '1';
|
||||
|
||||
when 183 => interrupt_event <= '1';
|
||||
|
||||
when others => interrupt_event <= '0'; -- no interrupt
|
||||
|
||||
end case;
|
||||
|
||||
end loop;
|
||||
|
||||
wait; -- end of simulation.
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,148 @@
|
||||
-- 9-Bit UART Receiver with integral 16 byte FIFO buffer
|
||||
--
|
||||
-- 9 data bits, no parity, 1 stop bit
|
||||
-- or
|
||||
-- 8 data bits, parity, 1 stop bit
|
||||
-- where the value of the parity bit must be checked externally and is provided as data_out(8).
|
||||
--
|
||||
-- Version : 1.00 (derived from uart_rx version 1.00)
|
||||
-- Version Date : 11th February 2005
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART9_RX
|
||||
--
|
||||
entity uart9_rx is
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end uart9_rx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART9_RX
|
||||
--
|
||||
architecture macro_level_definition of uart9_rx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART9_RX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART Receiver
|
||||
--
|
||||
component kcuart9_rx
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
data_strobe : out std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo_16x9
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART9_RX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal uart_data_out : std_logic_vector(8 downto 0);
|
||||
signal fifo_write : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART9_RX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- Constant (K) Compact UART 9-bit Receiver
|
||||
|
||||
receiver: kcuart9_rx
|
||||
port map ( serial_in => serial_in,
|
||||
data_out => uart_data_out,
|
||||
data_strobe => fifo_write,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
clk => clk );
|
||||
|
||||
-- 9-bit 'Bucket Brigade' FIFO
|
||||
|
||||
buf: bbfifo_16x9
|
||||
port map ( data_in => uart_data_out,
|
||||
data_out => data_out,
|
||||
reset => reset_buffer,
|
||||
write => fifo_write,
|
||||
read => read_buffer,
|
||||
full => buffer_full,
|
||||
half_full => buffer_half_full,
|
||||
data_present => buffer_data_present,
|
||||
clk => clk);
|
||||
|
||||
end macro_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART9_RX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,150 @@
|
||||
-- 9-Bit UART Transmitter with integral 16 byte FIFO buffer
|
||||
--
|
||||
-- 9 data bits, no parity, 1 stop bit
|
||||
-- or
|
||||
-- 8 data bits, parity, 1 stop bit
|
||||
-- where the value of the parity bit must be computed externally and provided as data_in(8).
|
||||
--
|
||||
-- Version : 1.00 (derived from uart_tx version 1.00)
|
||||
-- Version Date : 10th February 2005
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART9_TX
|
||||
--
|
||||
entity uart9_tx is
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end uart9_tx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART_TX
|
||||
--
|
||||
architecture macro_level_definition of uart9_tx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART9_TX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART 9-bit Transmitter
|
||||
--
|
||||
component kcuart9_tx
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
send_character : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
tx_complete : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- 9-bit 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo_16x9
|
||||
Port ( data_in : in std_logic_vector(8 downto 0);
|
||||
data_out : out std_logic_vector(8 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART9_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal fifo_data_out : std_logic_vector(8 downto 0);
|
||||
signal fifo_data_present : std_logic;
|
||||
signal fifo_read : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- Constant (K) Compact UART 9-bit Transmitter
|
||||
|
||||
transmitter: kcuart9_tx
|
||||
port map ( data_in => fifo_data_out,
|
||||
send_character => fifo_data_present,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => serial_out,
|
||||
Tx_complete => fifo_read,
|
||||
clk => clk);
|
||||
|
||||
-- 9-bit 'Bucket Brigade' FIFO
|
||||
|
||||
buf: bbfifo_16x9
|
||||
port map ( data_in => data_in,
|
||||
data_out => fifo_data_out,
|
||||
reset => reset_buffer,
|
||||
write => write_buffer,
|
||||
read => fifo_read,
|
||||
full => buffer_full,
|
||||
half_full => buffer_half_full,
|
||||
data_present => fifo_data_present,
|
||||
clk => clk);
|
||||
|
||||
end macro_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,367 @@
|
||||
--
|
||||
-- KCPSM3 reference design - Real Time Clock with UART communications
|
||||
--
|
||||
-- Ken Chapman - Xilinx Ltd - October 2003
|
||||
--
|
||||
-- The design demonstrates the following:-
|
||||
-- Connection of KCPSM3 to Program ROM
|
||||
-- Connection of UART macros supplied with PicoBlaze with
|
||||
-- Baud rate generation
|
||||
-- Definition of input and output ports with
|
||||
-- Minimum decoding
|
||||
-- Pipelining where appropriate
|
||||
-- Interrupt circuit with
|
||||
-- Simple fixed period timer
|
||||
-- Automatic clearing using interrupt acknowledge from KCPSM3
|
||||
--
|
||||
-- The design is set up for a 55MHz system clock and UART communications rate of 38400 baud.
|
||||
-- Please read design documentation to modify to your own requirements.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2003. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Furthermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
Library UNISIM;
|
||||
use UNISIM.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
--
|
||||
entity uart_clock is
|
||||
Port ( sys_TX : out std_logic;
|
||||
sys_RX : in std_logic;
|
||||
sys_alarm : out std_logic;
|
||||
sys_clk_in : in std_logic;
|
||||
sys_rst_in : in std_logic);
|
||||
end uart_clock;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of test architecture
|
||||
--
|
||||
architecture Behavioral of uart_clock is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- declaration of KCPSM3
|
||||
--
|
||||
component kcpsm3
|
||||
Port ( address : out std_logic_vector(9 downto 0);
|
||||
instruction : in std_logic_vector(17 downto 0);
|
||||
port_id : out std_logic_vector(7 downto 0);
|
||||
write_strobe : out std_logic;
|
||||
out_port : out std_logic_vector(7 downto 0);
|
||||
read_strobe : out std_logic;
|
||||
in_port : in std_logic_vector(7 downto 0);
|
||||
interrupt : in std_logic;
|
||||
interrupt_ack : out std_logic;
|
||||
reset : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of program ROM
|
||||
--
|
||||
component uclock
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of UART transmitter with integral 16 byte FIFO buffer
|
||||
--
|
||||
component uart_tx
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of UART Receiver with integral 16 byte FIFO buffer
|
||||
--
|
||||
component uart_rx
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used to connect KCPSM3 to program ROM and I/O logic
|
||||
--
|
||||
signal address : std_logic_vector(9 downto 0);
|
||||
signal instruction : std_logic_vector(17 downto 0);
|
||||
signal port_id : std_logic_vector(7 downto 0);
|
||||
signal out_port : std_logic_vector(7 downto 0);
|
||||
signal in_port : std_logic_vector(7 downto 0);
|
||||
signal write_strobe : std_logic;
|
||||
signal read_strobe : std_logic;
|
||||
signal interrupt : std_logic;
|
||||
signal interrupt_ack : std_logic;
|
||||
signal pico_rst : std_logic;
|
||||
signal clk : std_logic;
|
||||
|
||||
--
|
||||
-- Signals for connection of peripherals
|
||||
--
|
||||
signal uart_status_port : std_logic_vector(7 downto 0);
|
||||
--
|
||||
-- Signals to form an timer generating an interrupt every microsecond
|
||||
--
|
||||
signal timer_count : integer range 0 to 127 :=0;
|
||||
signal timer_pulse : std_logic;
|
||||
--
|
||||
-- Signals for UART connections
|
||||
--
|
||||
signal baud_count : integer range 0 to 255 :=0;
|
||||
signal en_16_x_baud : std_logic;
|
||||
signal write_to_uart : std_logic;
|
||||
signal tx_full : std_logic;
|
||||
signal tx_half_full : std_logic;
|
||||
signal read_from_uart : std_logic;
|
||||
signal rx_data : std_logic_vector(7 downto 0);
|
||||
signal rx_data_present : std_logic;
|
||||
signal rx_full : std_logic;
|
||||
signal rx_half_full : std_logic;
|
||||
|
||||
--
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of circuit description
|
||||
--
|
||||
begin
|
||||
--
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
-- KCPSM3 and the program memory
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
BUFG_inst : BUFG
|
||||
port map (
|
||||
O => clk, -- Clock buffer output
|
||||
I => sys_clk_in -- Clock buffer input
|
||||
);
|
||||
|
||||
pico_rst <= not sys_rst_in;
|
||||
|
||||
processor: kcpsm3
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
port_id => port_id,
|
||||
write_strobe => write_strobe,
|
||||
out_port => out_port,
|
||||
read_strobe => read_strobe,
|
||||
in_port => in_port,
|
||||
interrupt => interrupt,
|
||||
interrupt_ack => interrupt_ack,
|
||||
reset => pico_rst,
|
||||
clk => clk);
|
||||
|
||||
program_rom: uclock
|
||||
port map( address => address,
|
||||
instruction => instruction,
|
||||
clk => clk);
|
||||
|
||||
--
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
-- Interrupt
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
--
|
||||
-- Interrupt is a generated once every 100 clock cycles to provide a 1us reference.
|
||||
-- Interrupt is automatically cleared by interrupt acknowledgment from KCPSM3.
|
||||
--
|
||||
|
||||
Timer: process(clk)
|
||||
begin
|
||||
|
||||
if clk'event and clk='1' then
|
||||
|
||||
if timer_count=99 then
|
||||
timer_count <= 0;
|
||||
timer_pulse <= '1';
|
||||
else
|
||||
timer_count <= timer_count + 1;
|
||||
timer_pulse <= '0';
|
||||
end if;
|
||||
|
||||
if interrupt_ack = '1' then
|
||||
interrupt <= '0';
|
||||
elsif timer_pulse = '1' then
|
||||
interrupt <= '1';
|
||||
else
|
||||
interrupt <= interrupt;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end process Timer;
|
||||
|
||||
|
||||
--
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
-- KCPSM3 input ports
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
--
|
||||
-- UART FIFO status signals to form a bus
|
||||
--
|
||||
|
||||
uart_status_port <= "000" & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
|
||||
|
||||
--
|
||||
-- The inputs connect via a pipelined multiplexer
|
||||
--
|
||||
|
||||
input_ports: process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
|
||||
case port_id(0) is
|
||||
|
||||
|
||||
-- read UART status at address 00 hex
|
||||
when '0' => in_port <= uart_status_port;
|
||||
|
||||
-- read UART receive data at address 01 hex
|
||||
when '1' => in_port <= rx_data;
|
||||
|
||||
-- Don't care used for all other addresses to ensure minimum logic implementation
|
||||
when others => in_port <= "XXXXXXXX";
|
||||
|
||||
end case;
|
||||
|
||||
-- Form read strobe for UART receiver FIFO buffer.
|
||||
-- The fact that the read strobe will occur after the actual data is read by
|
||||
-- the KCPSM3 is acceptable because it is really means 'I have read you'!
|
||||
|
||||
read_from_uart <= read_strobe and port_id(0);
|
||||
|
||||
end if;
|
||||
|
||||
end process input_ports;
|
||||
|
||||
|
||||
--
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
-- KCPSM3 output ports
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
|
||||
-- adding the output registers to the clock processor
|
||||
|
||||
output_ports: process(clk)
|
||||
begin
|
||||
|
||||
if clk'event and clk='1' then
|
||||
if write_strobe='1' then
|
||||
|
||||
-- Alarm register at address 00 hex with data bit0 providing control
|
||||
|
||||
if port_id(0)='0' then
|
||||
sys_alarm <= out_port(0);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end process output_ports;
|
||||
|
||||
--
|
||||
-- write to UART transmitter FIFO buffer at address 01 hex.
|
||||
-- This is a combinatorial decode because the FIFO is the 'port register'.
|
||||
--
|
||||
|
||||
write_to_uart <= write_strobe and port_id(0);
|
||||
|
||||
--
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
-- UART
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
|
||||
-- Each contains an embedded 16-byte FIFO buffer.
|
||||
--
|
||||
|
||||
transmit: uart_tx
|
||||
port map ( data_in => out_port,
|
||||
write_buffer => write_to_uart,
|
||||
reset_buffer => '0',
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => sys_tx,
|
||||
buffer_full => tx_full,
|
||||
buffer_half_full => tx_half_full,
|
||||
clk => clk );
|
||||
|
||||
receive: uart_rx
|
||||
port map ( serial_in => sys_rx,
|
||||
data_out => rx_data,
|
||||
read_buffer => read_from_uart,
|
||||
reset_buffer => '0',
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
buffer_data_present => rx_data_present,
|
||||
buffer_full => rx_full,
|
||||
buffer_half_full => rx_half_full,
|
||||
clk => clk );
|
||||
|
||||
--
|
||||
-- Set baud rate to 38400 for the UART communications
|
||||
-- Requires en_16_x_baud to be 614400Hz which is a single cycle pulse every 163 cycles at 100MHz
|
||||
--
|
||||
-- NOTE : If the highest value for baud_count exceeds 127 you will need to adjust
|
||||
-- the range of integers in the signal declaration for baud_count.
|
||||
--
|
||||
|
||||
baud_timer: process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
if baud_count=162 then
|
||||
baud_count <= 0;
|
||||
en_16_x_baud <= '1';
|
||||
else
|
||||
baud_count <= baud_count + 1;
|
||||
en_16_x_baud <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process baud_timer;
|
||||
|
||||
----------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
end Behavioral;
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE uart_clock.vhd
|
||||
--
|
||||
------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,146 @@
|
||||
-- UART Receiver with integral 16 byte FIFO buffer
|
||||
--
|
||||
-- 8 bit, no parity, 1 stop bit
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 16th October 2002
|
||||
--
|
||||
-- Start of design entry : 16th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART_RX
|
||||
--
|
||||
entity uart_rx is
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end uart_rx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART_RX
|
||||
--
|
||||
architecture macro_level_definition of uart_rx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART_RX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART Receiver
|
||||
--
|
||||
component kcuart_rx
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
data_strobe : out std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo_16x8
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART_RX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal uart_data_out : std_logic_vector(7 downto 0);
|
||||
signal fifo_write : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART_RX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- 8 to 1 multiplexer to convert parallel data to serial
|
||||
|
||||
kcuart: kcuart_rx
|
||||
port map ( serial_in => serial_in,
|
||||
data_out => uart_data_out,
|
||||
data_strobe => fifo_write,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
clk => clk );
|
||||
|
||||
|
||||
buf: bbfifo_16x8
|
||||
port map ( data_in => uart_data_out,
|
||||
data_out => data_out,
|
||||
reset => reset_buffer,
|
||||
write => fifo_write,
|
||||
read => read_buffer,
|
||||
full => buffer_full,
|
||||
half_full => buffer_half_full,
|
||||
data_present => buffer_data_present,
|
||||
clk => clk);
|
||||
|
||||
end macro_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART_RX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
@@ -0,0 +1,148 @@
|
||||
-- UART Transmitter with integral 16 byte FIFO buffer
|
||||
--
|
||||
-- 8 bit, no parity, 1 stop bit
|
||||
--
|
||||
-- Version : 1.00
|
||||
-- Version Date : 14th October 2002
|
||||
--
|
||||
-- Start of design entry : 14th October 2002
|
||||
--
|
||||
-- Ken Chapman
|
||||
-- Xilinx Ltd
|
||||
-- Benchmark House
|
||||
-- 203 Brooklands Road
|
||||
-- Weybridge
|
||||
-- Surrey KT13 ORH
|
||||
-- United Kingdom
|
||||
--
|
||||
-- chapman@xilinx.com
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- NOTICE:
|
||||
--
|
||||
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
|
||||
-- third parties. By providing this core as one possible implementation of a standard,
|
||||
-- Xilinx is making no representation that the provided implementation of this standard
|
||||
-- is free from any claims of infringement by any third party. Xilinx expressly
|
||||
-- disclaims any warranty with respect to the adequacy of the implementation, including
|
||||
-- but not limited to any warranty or representation that the implementation is free
|
||||
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
|
||||
-- courtesy to you and suggests that you contact all third parties to obtain the
|
||||
-- necessary rights to use this implementation.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Library declarations
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Main Entity for UART_TX
|
||||
--
|
||||
entity uart_tx is
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end uart_tx;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of Main Architecture for UART_TX
|
||||
--
|
||||
architecture macro_level_definition of uart_tx is
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Components used in UART_TX and defined in subsequent entities.
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Constant (K) Compact UART Transmitter
|
||||
--
|
||||
component kcuart_tx
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
send_character : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
Tx_complete : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- 'Bucket Brigade' FIFO
|
||||
--
|
||||
component bbfifo_16x8
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
reset : in std_logic;
|
||||
write : in std_logic;
|
||||
read : in std_logic;
|
||||
full : out std_logic;
|
||||
half_full : out std_logic;
|
||||
data_present : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Signals used in UART_TX
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
signal fifo_data_out : std_logic_vector(7 downto 0);
|
||||
signal fifo_data_present : std_logic;
|
||||
signal fifo_read : std_logic;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Start of UART_TX circuit description
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
begin
|
||||
|
||||
-- 8 to 1 multiplexer to convert parallel data to serial
|
||||
|
||||
kcuart: kcuart_tx
|
||||
port map ( data_in => fifo_data_out,
|
||||
send_character => fifo_data_present,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => serial_out,
|
||||
Tx_complete => fifo_read,
|
||||
clk => clk);
|
||||
|
||||
|
||||
buf: bbfifo_16x8
|
||||
port map ( data_in => data_in,
|
||||
data_out => fifo_data_out,
|
||||
reset => reset_buffer,
|
||||
write => write_buffer,
|
||||
read => fifo_read,
|
||||
full => buffer_full,
|
||||
half_full => buffer_half_full,
|
||||
data_present => fifo_data_present,
|
||||
clk => clk);
|
||||
|
||||
end macro_level_definition;
|
||||
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE UART_TX.VHD
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Reference in New Issue
Block a user