jens
2f7ab91e0d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
47 lines
2.6 KiB
Plaintext
47 lines
2.6 KiB
Plaintext
# Copyright (C) 1991-2008 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# The default values for assignments are stored in the file
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# eval_fixed_ja_assignment_defaults.qdf
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# If this file doesn't exist, and for assignments not listed, see file
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# assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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set_global_assignment -name FAMILY "Cyclone III"
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set_global_assignment -name DEVICE EP3C25Q240C8
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set_global_assignment -name TOP_LEVEL_ENTITY eval_fixed_ja
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:27:40 DECEMBER 18, 2008"
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set_global_assignment -name LAST_QUARTUS_VERSION 8.1
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name ASSIGNMENT_GROUP_MEMBER clk -section_id clock
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set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
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set_global_assignment -name SDC_FILE eval_fixed_ja.out.sdc
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set_global_assignment -name VHDL_FILE ../../../lib/fixed/fixed_pkg_c.vhd
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set_global_assignment -name VHDL_FILE ../src/eval_fixed_ja_syn.vhd
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set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON |