jens
d61b3c2e0c
git-svn-id: http://moon:8086/svn/vhdl/trunk@1416 cc03376c-175c-47c8-b038-4cd826a8556b
41 lines
1.4 KiB
Plaintext
41 lines
1.4 KiB
Plaintext
#
|
|
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
|
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
|
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
|
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
|
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
|
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
|
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
|
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
|
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
|
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
|
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
|
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
# FOR A PARTICULAR PURPOSE.
|
|
#
|
|
# (c) Copyright 2005 Xilinx, Inc.
|
|
# All rights reserved.
|
|
#
|
|
|
|
# Bus clock nets
|
|
NET sys_clk_in TNM_NET = "sys_clk_in";
|
|
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
|
|
|
|
NET sys_clk_in LOC = AE14;
|
|
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
|
NET sys_rst_in LOC = D6;
|
|
NET sys_rst_in PULLUP;
|
|
NET sys_rst_in TIG;
|
|
|
|
NET sys_rx LOC = W2;
|
|
NET sys_rx IOSTANDARD = LVCMOS33;
|
|
NET sys_rx TIG;
|
|
NET sys_tx LOC = W1;
|
|
NET sys_tx IOSTANDARD = LVCMOS33;
|
|
NET sys_tx TIG;
|
|
|
|
NET sys_alarm LOC = G5; #GPLED0
|
|
NET sys_alarm TIG;
|
|
NET sys_alarm SLEW = SLOW;
|
|
NET sys_alarm DRIVE = 2;
|