jens 18c24e29f6 - renamed buffers to fb_front and fb_back ...

- fb_front is writable by host only if msten = '0'. fb_back is writable by host every time.
- fb_front and fb_back are changed after complete frame. Controller can issue buffer-change Interrupt
- packed resx, resy and fps into one 32-bit register
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/trunk@650 cc03376c-175c-47c8-b038-4cd826a8556b

2009-11-09 19:14:49 +00:00

..

ac97_ctrl

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

CPUs

Initial version

2009-11-08 13:07:55 +00:00

FIFO

- renamed

2009-01-30 21:22:25 +00:00

filter

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

fix_std

Initial import

2008-08-23 08:20:30 +00:00

fixed

deleted

2009-01-11 15:31:42 +00:00

fixed_ja

Initial import

2008-08-23 08:20:30 +00:00

jasm

Initial import

2008-08-23 08:20:30 +00:00

misc

- minor bugfix (width mismatch)

2009-11-04 19:26:53 +00:00

PCK_FIO-1.16

Initial import

2008-08-23 08:20:30 +00:00

PCK_FIO-2002.7

Initial import

2008-08-23 08:20:30 +00:00

ps2_port

update

2009-11-07 12:01:22 +00:00

radio

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

SDRAM

update

2009-11-04 19:33:11 +00:00

SSRAM

- Using MODELSIM_HOME environment variable

2008-10-23 21:21:24 +00:00

uart

- minor changes

2009-11-08 21:53:11 +00:00

VGA_ctrl

- renamed buffers to fb_front and fb_back

2009-11-09 19:14:49 +00:00