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vhdl/lib/models/memory/sdram/mt48lc4m16a2/runall.do
T
jens 2edaa4d7cb - added models
git-svn-id: http://moon:8086/svn/vhdl/trunk@1290 cc03376c-175c-47c8-b038-4cd826a8556b
2015-06-10 19:27:35 +00:00

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vcom util1164.vhd
vcom stdlogar.vhd
vcom io_utils.vhd
vcom mti_pkg.vhd
vcom vec_gen.vhd
vcom ed_comnd.vhd
vsim vector_generate
run -all
vcom mt48lc4m16a2.vhd
vcom test.vhd
vsim tb
add wave -logic /u1/clk
add wave -logic /u1/cke
add wave -logic /u1/cs_n
add wave -logic /u1/ras_n
add wave -logic /u1/cas_n
add wave -logic /u1/we_n
add wave -literal -dec /u1/addr
add wave -literal -dec /u1/ba
add wave -literal -dec /u1/dq
add wave -literal /u1/dqm
add wave -literal /u1/operation
add wave -literal -dec /u1/mode_reg
add wave -logic /u1/active_enable
add wave -logic /u1/aref_enable
add wave -logic /u1/burst_term
add wave -logic /u1/mode_reg_enable
add wave -logic /u1/prech_enable
add wave -logic /u1/read_enable
add wave -logic /u1/write_enable
add wave -logic /u1/burst_length_1
add wave -logic /u1/burst_length_2
add wave -logic /u1/burst_length_4
add wave -logic /u1/burst_length_8
add wave -logic /u1/cas_latency_2
add wave -logic /u1/cas_latency_3
add wave -literal /u1/pre_chk
add wave -literal /u1/act_chk
add wave -literal /u1/bank_chk
add wave -literal -dec /u1/row_chk
add wave -literal -dec /u1/col_chk
run -all