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trunk
vhdl/projects/eval_dmux/main_top_translate.vhd
T
jens 2f7ab91e0d - added 
git-svn-id: http://moon:8086/svn/vhdl/trunk@1429 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-21 12:04:37 +00:00

3923 lines
89 KiB
VHDL
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-- Xilinx Vhdl netlist produced by netgen application (version G.30)
-- Command : -intstyle ise -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim main_top.ngd main_top_translate.vhd
-- Input file : main_top.ngd
-- Output file : main_top_translate.vhd
-- Design name : main_top
-- # of Entities : 1
-- Xilinx : D:/Xilinx
-- Device : 3s50tq144-5
-- This vhdl netlist is a simulation model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity main_top is
port (
clk : in STD_LOGIC := 'X';
csn : in STD_LOGIC := 'X';
wen : in STD_LOGIC := 'X';
resn : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 31 downto 0 );
d : inout STD_LOGIC_VECTOR ( 31 downto 0 )
);
end main_top;
architecture Structure of main_top is
signal clk_BUFGP : STD_LOGIC;
signal csn_IBUF : STD_LOGIC;
signal wen_IBUF : STD_LOGIC;
signal Q_n0000 : STD_LOGIC;
signal Q_n0001 : STD_LOGIC;
signal Q_n0002 : STD_LOGIC;
signal I3_N174 : STD_LOGIC;
signal a_7_IBUF : STD_LOGIC;
signal a_6_IBUF : STD_LOGIC;
signal a_5_IBUF : STD_LOGIC;
signal a_4_IBUF : STD_LOGIC;
signal N2377 : STD_LOGIC;
signal N2469 : STD_LOGIC;
signal N4609 : STD_LOGIC;
signal N4611 : STD_LOGIC;
signal N4786 : STD_LOGIC;
signal N4768 : STD_LOGIC;
signal N4613 : STD_LOGIC;
signal N4780 : STD_LOGIC;
signal N4615 : STD_LOGIC;
signal N4756 : STD_LOGIC;
signal N4617 : STD_LOGIC;
signal N4619 : STD_LOGIC;
signal N4621 : STD_LOGIC;
signal N4808 : STD_LOGIC;
signal N4736 : STD_LOGIC;
signal N4623 : STD_LOGIC;
signal N4766 : STD_LOGIC;
signal N4625 : STD_LOGIC;
signal N4627 : STD_LOGIC;
signal N4742 : STD_LOGIC;
signal N4814 : STD_LOGIC;
signal N4629 : STD_LOGIC;
signal N4810 : STD_LOGIC;
signal N4711 : STD_LOGIC;
signal N4732 : STD_LOGIC;
signal N4778 : STD_LOGIC;
signal N4738 : STD_LOGIC;
signal N4631 : STD_LOGIC;
signal N4772 : STD_LOGIC;
signal N4633 : STD_LOGIC;
signal N4730 : STD_LOGIC;
signal N4790 : STD_LOGIC;
signal N4784 : STD_LOGIC;
signal N4635 : STD_LOGIC;
signal N4717 : STD_LOGIC;
signal N4705 : STD_LOGIC;
signal N4754 : STD_LOGIC;
signal N4725 : STD_LOGIC;
signal N4796 : STD_LOGIC;
signal N4707 : STD_LOGIC;
signal N4637 : STD_LOGIC;
signal N4723 : STD_LOGIC;
signal N4639 : STD_LOGIC;
signal N4760 : STD_LOGIC;
signal N4641 : STD_LOGIC;
signal N4643 : STD_LOGIC;
signal N4774 : STD_LOGIC;
signal N4645 : STD_LOGIC;
signal N4802 : STD_LOGIC;
signal N4748 : STD_LOGIC;
signal N4816 : STD_LOGIC;
signal N4647 : STD_LOGIC;
signal N4762 : STD_LOGIC;
signal N4649 : STD_LOGIC;
signal N4804 : STD_LOGIC;
signal N4719 : STD_LOGIC;
signal N4651 : STD_LOGIC;
signal N4653 : STD_LOGIC;
signal N4655 : STD_LOGIC;
signal N4792 : STD_LOGIC;
signal N4750 : STD_LOGIC;
signal N4798 : STD_LOGIC;
signal N4713 : STD_LOGIC;
signal N4744 : STD_LOGIC;
signal N4883 : STD_LOGIC;
signal N4881 : STD_LOGIC;
signal N4593 : STD_LOGIC;
signal N4595 : STD_LOGIC;
signal N4597 : STD_LOGIC;
signal N4599 : STD_LOGIC;
signal N4601 : STD_LOGIC;
signal N4603 : STD_LOGIC;
signal N4605 : STD_LOGIC;
signal N4607 : STD_LOGIC;
signal N4821 : STD_LOGIC;
signal N4823 : STD_LOGIC;
signal N4826 : STD_LOGIC;
signal N4828 : STD_LOGIC;
signal N4831 : STD_LOGIC;
signal N4833 : STD_LOGIC;
signal N4836 : STD_LOGIC;
signal N4838 : STD_LOGIC;
signal N4841 : STD_LOGIC;
signal N4843 : STD_LOGIC;
signal N4846 : STD_LOGIC;
signal N4848 : STD_LOGIC;
signal N4851 : STD_LOGIC;
signal N4853 : STD_LOGIC;
signal N4856 : STD_LOGIC;
signal N4858 : STD_LOGIC;
signal N4861 : STD_LOGIC;
signal N4863 : STD_LOGIC;
signal N4866 : STD_LOGIC;
signal N4868 : STD_LOGIC;
signal N4871 : STD_LOGIC;
signal N4873 : STD_LOGIC;
signal N4876 : STD_LOGIC;
signal N4878 : STD_LOGIC;
signal clk_BUFGP_IBUFG : STD_LOGIC;
signal GSR : STD_LOGIC;
signal GTS : STD_LOGIC;
signal d_11_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_12_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_13_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_14_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_15_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_20_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_16_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_21_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_17_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_22_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_18_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_23_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_19_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_24_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_25_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_30_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_26_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_31_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_27_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_28_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_29_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_0_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_1_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_2_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_3_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_4_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_5_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_6_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_7_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_8_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_9_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal d_10_IOBUF_OBUFT_GTS_AND : STD_LOGIC;
signal NlwInverterSignal_reg_a_31_C : STD_LOGIC;
signal GND : STD_LOGIC;
signal NlwInverterSignal_reg_b_31_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_31_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_0_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_1_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_2_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_3_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_4_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_5_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_6_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_7_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_8_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_9_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_10_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_11_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_12_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_13_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_14_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_15_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_16_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_17_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_18_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_19_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_20_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_21_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_22_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_23_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_24_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_25_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_26_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_27_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_28_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_29_C : STD_LOGIC;
signal NlwInverterSignal_reg_c_30_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_0_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_1_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_2_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_3_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_4_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_5_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_6_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_7_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_8_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_9_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_10_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_11_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_12_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_13_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_14_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_15_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_16_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_17_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_18_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_19_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_20_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_21_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_22_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_23_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_24_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_25_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_26_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_27_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_28_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_29_C : STD_LOGIC;
signal NlwInverterSignal_reg_b_30_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_0_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_1_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_2_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_3_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_4_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_5_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_6_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_7_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_8_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_9_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_10_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_11_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_12_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_13_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_14_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_15_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_16_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_17_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_18_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_19_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_20_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_21_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_22_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_23_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_24_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_25_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_26_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_27_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_28_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_29_C : STD_LOGIC;
signal NlwInverterSignal_reg_a_30_C : STD_LOGIC;
signal NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN0 : STD_LOGIC;
signal NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN1 : STD_LOGIC;
signal dmuxo : STD_LOGIC_VECTOR ( 31 downto 0 );
signal reg_c : STD_LOGIC_VECTOR ( 31 downto 0 );
signal reg_a : STD_LOGIC_VECTOR ( 31 downto 0 );
signal reg_b : STD_LOGIC_VECTOR ( 31 downto 0 );
begin
dmuxo_30_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(30),
ADR2 => a_7_IBUF,
O => N4713
);
a_4_IBUF_0 : X_BUF
port map (
I => a(4),
O => a_4_IBUF
);
dmuxo_14_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(14),
O => N4883
);
Q_n00021 : X_LUT3
generic map(
INIT => X"20"
)
port map (
ADR0 => N2469,
ADR1 => a_4_IBUF,
ADR2 => a_5_IBUF,
O => Q_n0002
);
Ker23751 : X_LUT2
generic map(
INIT => X"E"
)
port map (
ADR0 => a_6_IBUF,
ADR1 => a_7_IBUF,
O => N2377
);
Q_n00001 : X_LUT3
generic map(
INIT => X"04"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => N2469,
ADR2 => a_5_IBUF,
O => Q_n0000
);
dmuxo_14_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(14),
ADR3 => reg_a(14),
O => N4881
);
a_5_IBUF_1 : X_BUF
port map (
I => a(5),
O => a_5_IBUF
);
dmuxo_0_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(0),
ADR2 => a_7_IBUF,
O => N4756
);
a_6_IBUF_2 : X_BUF
port map (
I => a(6),
O => a_6_IBUF
);
a_7_IBUF_3 : X_BUF
port map (
I => a(7),
O => a_7_IBUF
);
dmuxo_28_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(28),
O => N4878
);
dmuxo_15_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(15),
ADR2 => a_7_IBUF,
O => N4762
);
reg_a_31 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4627,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_31_C,
O => reg_a(31),
SET => GND,
RST => GSR
);
reg_b_31 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4627,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_31_C,
O => reg_b(31),
SET => GND,
RST => GSR
);
reg_c_31 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4627,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_31_C,
O => reg_c(31),
SET => GND,
RST => GSR
);
wen_IBUF_4 : X_BUF
port map (
I => wen,
O => wen_IBUF
);
dmuxo_26_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(26),
ADR2 => a_7_IBUF,
ADR3 => reg_a(26),
O => N4730
);
dmuxo_13_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4707,
ADR3 => N4705,
O => dmuxo(13)
);
dmuxo_6_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(6),
O => N4873
);
dmuxo_26_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(26),
ADR2 => a_7_IBUF,
O => N4732
);
dmuxo_30_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4713,
ADR3 => N4711,
O => dmuxo(30)
);
dmuxo_1_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(1),
ADR2 => a_7_IBUF,
O => N4744
);
dmuxo_24_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4719,
ADR3 => N4717,
O => dmuxo(24)
);
dmuxo_16_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(16),
ADR2 => a_7_IBUF,
O => N4774
);
csn_IBUF_5 : X_BUF
port map (
I => csn,
O => csn_IBUF
);
dmuxo_14_19 : X_MUX2
port map (
IA => N4881,
IB => N4883,
SEL => a_5_IBUF,
O => dmuxo(14)
);
dmuxo_7_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4798,
ADR3 => N4796,
O => dmuxo(7)
);
dmuxo_27_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(27),
ADR2 => a_7_IBUF,
ADR3 => reg_a(27),
O => N4766
);
dmuxo_25_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(25),
O => N4868
);
dmuxo_13_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(13),
ADR2 => a_7_IBUF,
ADR3 => reg_a(13),
O => N4705
);
dmuxo_27_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(27),
ADR2 => a_7_IBUF,
O => N4768
);
dmuxo_29_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4816,
ADR3 => N4814,
O => dmuxo(29)
);
dmuxo_2_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(2),
ADR2 => a_7_IBUF,
O => N4804
);
dmuxo_22_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4810,
ADR3 => N4808,
O => dmuxo(22)
);
dmuxo_11_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4725,
ADR3 => N4723,
O => dmuxo(11)
);
dmuxo_22_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(22),
ADR2 => a_7_IBUF,
O => N4810
);
reg_c_0 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4635,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_0_C,
O => reg_c(0),
SET => GND,
RST => GSR
);
reg_c_1 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4637,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_1_C,
O => reg_c(1),
SET => GND,
RST => GSR
);
reg_c_2 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4639,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_2_C,
O => reg_c(2),
SET => GND,
RST => GSR
);
reg_c_3 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4641,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_3_C,
O => reg_c(3),
SET => GND,
RST => GSR
);
reg_c_4 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4643,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_4_C,
O => reg_c(4),
SET => GND,
RST => GSR
);
reg_c_5 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4645,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_5_C,
O => reg_c(5),
SET => GND,
RST => GSR
);
reg_c_6 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4647,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_6_C,
O => reg_c(6),
SET => GND,
RST => GSR
);
reg_c_7 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4649,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_7_C,
O => reg_c(7),
SET => GND,
RST => GSR
);
reg_c_8 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4651,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_8_C,
O => reg_c(8),
SET => GND,
RST => GSR
);
reg_c_9 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4653,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_9_C,
O => reg_c(9),
SET => GND,
RST => GSR
);
reg_c_10 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4655,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_10_C,
O => reg_c(10),
SET => GND,
RST => GSR
);
reg_c_11 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4593,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_11_C,
O => reg_c(11),
SET => GND,
RST => GSR
);
reg_c_12 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4595,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_12_C,
O => reg_c(12),
SET => GND,
RST => GSR
);
reg_c_13 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4597,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_13_C,
O => reg_c(13),
SET => GND,
RST => GSR
);
reg_c_14 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4599,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_14_C,
O => reg_c(14),
SET => GND,
RST => GSR
);
reg_c_15 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4601,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_15_C,
O => reg_c(15),
SET => GND,
RST => GSR
);
reg_c_16 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4605,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_16_C,
O => reg_c(16),
SET => GND,
RST => GSR
);
reg_c_17 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4609,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_17_C,
O => reg_c(17),
SET => GND,
RST => GSR
);
reg_c_18 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4613,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_18_C,
O => reg_c(18),
SET => GND,
RST => GSR
);
reg_c_19 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4617,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_19_C,
O => reg_c(19),
SET => GND,
RST => GSR
);
reg_c_20 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4603,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_20_C,
O => reg_c(20),
SET => GND,
RST => GSR
);
reg_c_21 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4607,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_21_C,
O => reg_c(21),
SET => GND,
RST => GSR
);
reg_c_22 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4611,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_22_C,
O => reg_c(22),
SET => GND,
RST => GSR
);
reg_c_23 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4615,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_23_C,
O => reg_c(23),
SET => GND,
RST => GSR
);
reg_c_24 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4619,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_24_C,
O => reg_c(24),
SET => GND,
RST => GSR
);
reg_c_25 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4621,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_25_C,
O => reg_c(25),
SET => GND,
RST => GSR
);
reg_c_26 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4625,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_26_C,
O => reg_c(26),
SET => GND,
RST => GSR
);
reg_c_27 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4629,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_27_C,
O => reg_c(27),
SET => GND,
RST => GSR
);
reg_c_28 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4631,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_28_C,
O => reg_c(28),
SET => GND,
RST => GSR
);
reg_c_29 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4633,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_29_C,
O => reg_c(29),
SET => GND,
RST => GSR
);
reg_c_30 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4623,
CE => Q_n0002,
CLK => NlwInverterSignal_reg_c_30_C,
O => reg_c(30),
SET => GND,
RST => GSR
);
reg_b_0 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4635,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_0_C,
O => reg_b(0),
SET => GND,
RST => GSR
);
reg_b_1 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4637,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_1_C,
O => reg_b(1),
SET => GND,
RST => GSR
);
reg_b_2 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4639,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_2_C,
O => reg_b(2),
SET => GND,
RST => GSR
);
reg_b_3 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4641,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_3_C,
O => reg_b(3),
SET => GND,
RST => GSR
);
reg_b_4 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4643,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_4_C,
O => reg_b(4),
SET => GND,
RST => GSR
);
reg_b_5 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4645,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_5_C,
O => reg_b(5),
SET => GND,
RST => GSR
);
reg_b_6 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4647,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_6_C,
O => reg_b(6),
SET => GND,
RST => GSR
);
reg_b_7 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4649,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_7_C,
O => reg_b(7),
SET => GND,
RST => GSR
);
reg_b_8 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4651,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_8_C,
O => reg_b(8),
SET => GND,
RST => GSR
);
reg_b_9 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4653,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_9_C,
O => reg_b(9),
SET => GND,
RST => GSR
);
reg_b_10 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4655,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_10_C,
O => reg_b(10),
SET => GND,
RST => GSR
);
reg_b_11 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4593,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_11_C,
O => reg_b(11),
SET => GND,
RST => GSR
);
reg_b_12 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4595,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_12_C,
O => reg_b(12),
SET => GND,
RST => GSR
);
reg_b_13 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4597,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_13_C,
O => reg_b(13),
SET => GND,
RST => GSR
);
reg_b_14 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4599,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_14_C,
O => reg_b(14),
SET => GND,
RST => GSR
);
reg_b_15 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4601,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_15_C,
O => reg_b(15),
SET => GND,
RST => GSR
);
reg_b_16 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4605,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_16_C,
O => reg_b(16),
SET => GND,
RST => GSR
);
reg_b_17 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4609,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_17_C,
O => reg_b(17),
SET => GND,
RST => GSR
);
reg_b_18 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4613,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_18_C,
O => reg_b(18),
SET => GND,
RST => GSR
);
reg_b_19 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4617,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_19_C,
O => reg_b(19),
SET => GND,
RST => GSR
);
reg_b_20 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4603,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_20_C,
O => reg_b(20),
SET => GND,
RST => GSR
);
reg_b_21 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4607,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_21_C,
O => reg_b(21),
SET => GND,
RST => GSR
);
reg_b_22 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4611,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_22_C,
O => reg_b(22),
SET => GND,
RST => GSR
);
reg_b_23 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4615,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_23_C,
O => reg_b(23),
SET => GND,
RST => GSR
);
reg_b_24 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4619,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_24_C,
O => reg_b(24),
SET => GND,
RST => GSR
);
reg_b_25 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4621,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_25_C,
O => reg_b(25),
SET => GND,
RST => GSR
);
reg_b_26 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4625,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_26_C,
O => reg_b(26),
SET => GND,
RST => GSR
);
reg_b_27 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4629,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_27_C,
O => reg_b(27),
SET => GND,
RST => GSR
);
reg_b_28 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4631,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_28_C,
O => reg_b(28),
SET => GND,
RST => GSR
);
reg_b_29 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4633,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_29_C,
O => reg_b(29),
SET => GND,
RST => GSR
);
reg_b_30 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4623,
CE => Q_n0001,
CLK => NlwInverterSignal_reg_b_30_C,
O => reg_b(30),
SET => GND,
RST => GSR
);
reg_a_0 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4635,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_0_C,
O => reg_a(0),
SET => GND,
RST => GSR
);
reg_a_1 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4637,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_1_C,
O => reg_a(1),
SET => GND,
RST => GSR
);
reg_a_2 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4639,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_2_C,
O => reg_a(2),
SET => GND,
RST => GSR
);
reg_a_3 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4641,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_3_C,
O => reg_a(3),
SET => GND,
RST => GSR
);
reg_a_4 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4643,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_4_C,
O => reg_a(4),
SET => GND,
RST => GSR
);
reg_a_5 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4645,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_5_C,
O => reg_a(5),
SET => GND,
RST => GSR
);
reg_a_6 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4647,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_6_C,
O => reg_a(6),
SET => GND,
RST => GSR
);
reg_a_7 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4649,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_7_C,
O => reg_a(7),
SET => GND,
RST => GSR
);
reg_a_8 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4651,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_8_C,
O => reg_a(8),
SET => GND,
RST => GSR
);
reg_a_9 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4653,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_9_C,
O => reg_a(9),
SET => GND,
RST => GSR
);
reg_a_10 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4655,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_10_C,
O => reg_a(10),
SET => GND,
RST => GSR
);
reg_a_11 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4593,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_11_C,
O => reg_a(11),
SET => GND,
RST => GSR
);
reg_a_12 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4595,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_12_C,
O => reg_a(12),
SET => GND,
RST => GSR
);
reg_a_13 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4597,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_13_C,
O => reg_a(13),
SET => GND,
RST => GSR
);
reg_a_14 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4599,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_14_C,
O => reg_a(14),
SET => GND,
RST => GSR
);
reg_a_15 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4601,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_15_C,
O => reg_a(15),
SET => GND,
RST => GSR
);
reg_a_16 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4605,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_16_C,
O => reg_a(16),
SET => GND,
RST => GSR
);
reg_a_17 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4609,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_17_C,
O => reg_a(17),
SET => GND,
RST => GSR
);
reg_a_18 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4613,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_18_C,
O => reg_a(18),
SET => GND,
RST => GSR
);
reg_a_19 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4617,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_19_C,
O => reg_a(19),
SET => GND,
RST => GSR
);
reg_a_20 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4603,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_20_C,
O => reg_a(20),
SET => GND,
RST => GSR
);
reg_a_21 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4607,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_21_C,
O => reg_a(21),
SET => GND,
RST => GSR
);
reg_a_22 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4611,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_22_C,
O => reg_a(22),
SET => GND,
RST => GSR
);
reg_a_23 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4615,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_23_C,
O => reg_a(23),
SET => GND,
RST => GSR
);
reg_a_24 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4619,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_24_C,
O => reg_a(24),
SET => GND,
RST => GSR
);
reg_a_25 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4621,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_25_C,
O => reg_a(25),
SET => GND,
RST => GSR
);
reg_a_26 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4625,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_26_C,
O => reg_a(26),
SET => GND,
RST => GSR
);
reg_a_27 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4629,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_27_C,
O => reg_a(27),
SET => GND,
RST => GSR
);
reg_a_28 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4631,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_28_C,
O => reg_a(28),
SET => GND,
RST => GSR
);
reg_a_29 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4633,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_29_C,
O => reg_a(29),
SET => GND,
RST => GSR
);
reg_a_30 : X_FF
generic map(
INIT => '0'
)
port map (
I => N4623,
CE => Q_n0000,
CLK => NlwInverterSignal_reg_a_30_C,
O => reg_a(30),
SET => GND,
RST => GSR
);
I3_EnableTr_INV1 : X_LUT2
generic map(
INIT => X"D"
)
port map (
ADR0 => wen_IBUF,
ADR1 => csn_IBUF,
O => I3_N174
);
Q_n00011 : X_LUT3
generic map(
INIT => X"20"
)
port map (
ADR0 => N2469,
ADR1 => a_5_IBUF,
ADR2 => a_4_IBUF,
O => Q_n0001
);
dmuxo_5_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(5),
O => N4863
);
dmuxo_26_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4732,
ADR3 => N4730,
O => dmuxo(26)
);
dmuxo_22_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(22),
ADR2 => a_7_IBUF,
ADR3 => reg_a(22),
O => N4808
);
dmuxo_21_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(21),
O => N4858
);
dmuxo_17_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4738,
ADR3 => N4736,
O => dmuxo(17)
);
dmuxo_0_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(0),
ADR2 => a_7_IBUF,
ADR3 => reg_a(0),
O => N4754
);
dmuxo_29_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(29),
ADR2 => a_7_IBUF,
ADR3 => reg_a(29),
O => N4814
);
dmuxo_1_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(1),
ADR2 => a_7_IBUF,
ADR3 => reg_a(1),
O => N4742
);
dmuxo_4_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(4),
O => N4853
);
dmuxo_8_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(8),
ADR2 => a_7_IBUF,
O => N4780
);
dmuxo_31_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(31),
ADR2 => a_7_IBUF,
ADR3 => reg_a(31),
O => N4784
);
dmuxo_11_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(11),
ADR2 => a_7_IBUF,
ADR3 => reg_a(11),
O => N4723
);
dmuxo_7_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(7),
ADR2 => a_7_IBUF,
O => N4798
);
dmuxo_29_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(29),
ADR2 => a_7_IBUF,
O => N4816
);
dmuxo_23_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(23),
ADR2 => a_7_IBUF,
ADR3 => reg_a(23),
O => N4790
);
dmuxo_19_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(19),
ADR2 => a_7_IBUF,
O => N4750
);
dmuxo_12_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(12),
O => N4848
);
dmuxo_24_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(24),
ADR2 => a_7_IBUF,
O => N4719
);
dmuxo_13_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(13),
ADR2 => a_7_IBUF,
O => N4707
);
dmuxo_17_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(17),
ADR2 => a_7_IBUF,
O => N4738
);
dmuxo_1_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4744,
ADR3 => N4742,
O => dmuxo(1)
);
dmuxo_18_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(18),
O => N4843
);
dmuxo_19_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4750,
ADR3 => N4748,
O => dmuxo(19)
);
dmuxo_0_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4756,
ADR3 => N4754,
O => dmuxo(0)
);
dmuxo_17_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(17),
ADR2 => a_7_IBUF,
ADR3 => reg_a(17),
O => N4736
);
dmuxo_31_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(31),
ADR2 => a_7_IBUF,
O => N4786
);
dmuxo_3_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(3),
O => N4838
);
dmuxo_19_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(19),
ADR2 => a_7_IBUF,
ADR3 => reg_a(19),
O => N4748
);
dmuxo_15_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4762,
ADR3 => N4760,
O => dmuxo(15)
);
dmuxo_8_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(8),
ADR2 => a_7_IBUF,
ADR3 => reg_a(8),
O => N4778
);
dmuxo_20_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(20),
O => N4833
);
dmuxo_27_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4768,
ADR3 => N4766,
O => dmuxo(27)
);
dmuxo_11_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(11),
ADR2 => a_7_IBUF,
O => N4725
);
dmuxo_2_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4804,
ADR3 => N4802,
O => dmuxo(2)
);
dmuxo_16_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4774,
ADR3 => N4772,
O => dmuxo(16)
);
dmuxo_2_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(2),
ADR2 => a_7_IBUF,
ADR3 => reg_a(2),
O => N4802
);
dmuxo_30_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(30),
ADR2 => a_7_IBUF,
ADR3 => reg_a(30),
O => N4711
);
dmuxo_9_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(9),
O => N4828
);
dmuxo_7_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(7),
ADR2 => a_7_IBUF,
ADR3 => reg_a(7),
O => N4796
);
dmuxo_16_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(16),
ADR2 => a_7_IBUF,
ADR3 => reg_a(16),
O => N4772
);
dmuxo_8_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4780,
ADR3 => N4778,
O => dmuxo(8)
);
dmuxo_31_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4786,
ADR3 => N4784,
O => dmuxo(31)
);
dmuxo_23_34 : X_LUT4
generic map(
INIT => X"0213"
)
port map (
ADR0 => a_5_IBUF,
ADR1 => a_6_IBUF,
ADR2 => N4792,
ADR3 => N4790,
O => dmuxo(23)
);
dmuxo_10_19_G : X_LUT3
generic map(
INIT => X"FE"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_c(10),
O => N4823
);
dmuxo_15_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(15),
ADR2 => a_7_IBUF,
ADR3 => reg_a(15),
O => N4760
);
dmuxo_23_34_SW1 : X_LUT3
generic map(
INIT => X"FB"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_c(23),
ADR2 => a_7_IBUF,
O => N4792
);
dmuxo_24_34_SW0 : X_LUT4
generic map(
INIT => X"F2F7"
)
port map (
ADR0 => a_4_IBUF,
ADR1 => reg_b(24),
ADR2 => a_7_IBUF,
ADR3 => reg_a(24),
O => N4717
);
Ker24671 : X_LUT4
generic map(
INIT => X"0001"
)
port map (
ADR0 => a_6_IBUF,
ADR1 => a_7_IBUF,
ADR2 => csn_IBUF,
ADR3 => wen_IBUF,
O => N2469
);
dmuxo_10_19 : X_MUX2
port map (
IA => N4821,
IB => N4823,
SEL => a_5_IBUF,
O => dmuxo(10)
);
dmuxo_10_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(10),
ADR3 => reg_a(10),
O => N4821
);
dmuxo_9_19 : X_MUX2
port map (
IA => N4826,
IB => N4828,
SEL => a_5_IBUF,
O => dmuxo(9)
);
dmuxo_9_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(9),
ADR3 => reg_a(9),
O => N4826
);
dmuxo_20_19 : X_MUX2
port map (
IA => N4831,
IB => N4833,
SEL => a_5_IBUF,
O => dmuxo(20)
);
dmuxo_20_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(20),
ADR3 => reg_a(20),
O => N4831
);
dmuxo_3_19 : X_MUX2
port map (
IA => N4836,
IB => N4838,
SEL => a_5_IBUF,
O => dmuxo(3)
);
dmuxo_3_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(3),
ADR3 => reg_a(3),
O => N4836
);
dmuxo_18_19 : X_MUX2
port map (
IA => N4841,
IB => N4843,
SEL => a_5_IBUF,
O => dmuxo(18)
);
dmuxo_18_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(18),
ADR3 => reg_a(18),
O => N4841
);
dmuxo_12_19 : X_MUX2
port map (
IA => N4846,
IB => N4848,
SEL => a_5_IBUF,
O => dmuxo(12)
);
dmuxo_12_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(12),
ADR3 => reg_a(12),
O => N4846
);
dmuxo_4_19 : X_MUX2
port map (
IA => N4851,
IB => N4853,
SEL => a_5_IBUF,
O => dmuxo(4)
);
dmuxo_4_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(4),
ADR3 => reg_a(4),
O => N4851
);
dmuxo_21_19 : X_MUX2
port map (
IA => N4856,
IB => N4858,
SEL => a_5_IBUF,
O => dmuxo(21)
);
dmuxo_21_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(21),
ADR3 => reg_a(21),
O => N4856
);
dmuxo_5_19 : X_MUX2
port map (
IA => N4861,
IB => N4863,
SEL => a_5_IBUF,
O => dmuxo(5)
);
dmuxo_5_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(5),
ADR3 => reg_a(5),
O => N4861
);
dmuxo_25_19 : X_MUX2
port map (
IA => N4866,
IB => N4868,
SEL => a_5_IBUF,
O => dmuxo(25)
);
dmuxo_25_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(25),
ADR3 => reg_a(25),
O => N4866
);
dmuxo_6_19 : X_MUX2
port map (
IA => N4871,
IB => N4873,
SEL => a_5_IBUF,
O => dmuxo(6)
);
dmuxo_6_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(6),
ADR3 => reg_a(6),
O => N4871
);
dmuxo_28_19 : X_MUX2
port map (
IA => N4876,
IB => N4878,
SEL => a_5_IBUF,
O => dmuxo(28)
);
dmuxo_28_19_F : X_LUT4
generic map(
INIT => X"FBEA"
)
port map (
ADR0 => N2377,
ADR1 => a_4_IBUF,
ADR2 => reg_b(28),
ADR3 => reg_a(28),
O => N4876
);
d_30_IOBUF_OBUFT : X_TRI
port map (
CTL => d_30_IOBUF_OBUFT_GTS_AND,
I => dmuxo(30),
O => d(30)
);
d_30_IOBUF_IBUF : X_BUF
port map (
I => d(30),
O => N4623
);
d_29_IOBUF_OBUFT : X_TRI
port map (
CTL => d_29_IOBUF_OBUFT_GTS_AND,
I => dmuxo(29),
O => d(29)
);
d_29_IOBUF_IBUF : X_BUF
port map (
I => d(29),
O => N4633
);
d_28_IOBUF_OBUFT : X_TRI
port map (
CTL => d_28_IOBUF_OBUFT_GTS_AND,
I => dmuxo(28),
O => d(28)
);
d_28_IOBUF_IBUF : X_BUF
port map (
I => d(28),
O => N4631
);
d_22_IOBUF_OBUFT : X_TRI
port map (
CTL => d_22_IOBUF_OBUFT_GTS_AND,
I => dmuxo(22),
O => d(22)
);
d_22_IOBUF_IBUF : X_BUF
port map (
I => d(22),
O => N4611
);
d_21_IOBUF_OBUFT : X_TRI
port map (
CTL => d_21_IOBUF_OBUFT_GTS_AND,
I => dmuxo(21),
O => d(21)
);
d_21_IOBUF_IBUF : X_BUF
port map (
I => d(21),
O => N4607
);
d_24_IOBUF_OBUFT : X_TRI
port map (
CTL => d_24_IOBUF_OBUFT_GTS_AND,
I => dmuxo(24),
O => d(24)
);
d_24_IOBUF_IBUF : X_BUF
port map (
I => d(24),
O => N4619
);
d_27_IOBUF_OBUFT : X_TRI
port map (
CTL => d_27_IOBUF_OBUFT_GTS_AND,
I => dmuxo(27),
O => d(27)
);
d_27_IOBUF_IBUF : X_BUF
port map (
I => d(27),
O => N4629
);
d_26_IOBUF_OBUFT : X_TRI
port map (
CTL => d_26_IOBUF_OBUFT_GTS_AND,
I => dmuxo(26),
O => d(26)
);
d_26_IOBUF_IBUF : X_BUF
port map (
I => d(26),
O => N4625
);
d_25_IOBUF_OBUFT : X_TRI
port map (
CTL => d_25_IOBUF_OBUFT_GTS_AND,
I => dmuxo(25),
O => d(25)
);
d_25_IOBUF_IBUF : X_BUF
port map (
I => d(25),
O => N4621
);
d_19_IOBUF_OBUFT : X_TRI
port map (
CTL => d_19_IOBUF_OBUFT_GTS_AND,
I => dmuxo(19),
O => d(19)
);
d_19_IOBUF_IBUF : X_BUF
port map (
I => d(19),
O => N4617
);
d_31_IOBUF_OBUFT : X_TRI
port map (
CTL => d_31_IOBUF_OBUFT_GTS_AND,
I => dmuxo(31),
O => d(31)
);
d_31_IOBUF_IBUF : X_BUF
port map (
I => d(31),
O => N4627
);
clk_BUFGP_BUFG : X_CKBUF
port map (
I => clk_BUFGP_IBUFG,
O => clk_BUFGP
);
clk_BUFGP_IBUFG_9 : X_CKBUF
port map (
I => clk,
O => clk_BUFGP_IBUFG
);
d_23_IOBUF_OBUFT : X_TRI
port map (
CTL => d_23_IOBUF_OBUFT_GTS_AND,
I => dmuxo(23),
O => d(23)
);
d_23_IOBUF_IBUF : X_BUF
port map (
I => d(23),
O => N4615
);
d_20_IOBUF_OBUFT : X_TRI
port map (
CTL => d_20_IOBUF_OBUFT_GTS_AND,
I => dmuxo(20),
O => d(20)
);
d_20_IOBUF_IBUF : X_BUF
port map (
I => d(20),
O => N4603
);
d_0_IOBUF_OBUFT : X_TRI
port map (
CTL => d_0_IOBUF_OBUFT_GTS_AND,
I => dmuxo(0),
O => d(0)
);
d_0_IOBUF_IBUF : X_BUF
port map (
I => d(0),
O => N4635
);
d_1_IOBUF_OBUFT : X_TRI
port map (
CTL => d_1_IOBUF_OBUFT_GTS_AND,
I => dmuxo(1),
O => d(1)
);
d_1_IOBUF_IBUF : X_BUF
port map (
I => d(1),
O => N4637
);
d_2_IOBUF_OBUFT : X_TRI
port map (
CTL => d_2_IOBUF_OBUFT_GTS_AND,
I => dmuxo(2),
O => d(2)
);
d_2_IOBUF_IBUF : X_BUF
port map (
I => d(2),
O => N4639
);
d_3_IOBUF_OBUFT : X_TRI
port map (
CTL => d_3_IOBUF_OBUFT_GTS_AND,
I => dmuxo(3),
O => d(3)
);
d_3_IOBUF_IBUF : X_BUF
port map (
I => d(3),
O => N4641
);
d_4_IOBUF_OBUFT : X_TRI
port map (
CTL => d_4_IOBUF_OBUFT_GTS_AND,
I => dmuxo(4),
O => d(4)
);
d_4_IOBUF_IBUF : X_BUF
port map (
I => d(4),
O => N4643
);
d_5_IOBUF_OBUFT : X_TRI
port map (
CTL => d_5_IOBUF_OBUFT_GTS_AND,
I => dmuxo(5),
O => d(5)
);
d_5_IOBUF_IBUF : X_BUF
port map (
I => d(5),
O => N4645
);
d_6_IOBUF_OBUFT : X_TRI
port map (
CTL => d_6_IOBUF_OBUFT_GTS_AND,
I => dmuxo(6),
O => d(6)
);
d_6_IOBUF_IBUF : X_BUF
port map (
I => d(6),
O => N4647
);
d_7_IOBUF_OBUFT : X_TRI
port map (
CTL => d_7_IOBUF_OBUFT_GTS_AND,
I => dmuxo(7),
O => d(7)
);
d_7_IOBUF_IBUF : X_BUF
port map (
I => d(7),
O => N4649
);
d_8_IOBUF_OBUFT : X_TRI
port map (
CTL => d_8_IOBUF_OBUFT_GTS_AND,
I => dmuxo(8),
O => d(8)
);
d_8_IOBUF_IBUF : X_BUF
port map (
I => d(8),
O => N4651
);
d_9_IOBUF_OBUFT : X_TRI
port map (
CTL => d_9_IOBUF_OBUFT_GTS_AND,
I => dmuxo(9),
O => d(9)
);
d_9_IOBUF_IBUF : X_BUF
port map (
I => d(9),
O => N4653
);
d_10_IOBUF_OBUFT : X_TRI
port map (
CTL => d_10_IOBUF_OBUFT_GTS_AND,
I => dmuxo(10),
O => d(10)
);
d_10_IOBUF_IBUF : X_BUF
port map (
I => d(10),
O => N4655
);
d_11_IOBUF_OBUFT : X_TRI
port map (
CTL => d_11_IOBUF_OBUFT_GTS_AND,
I => dmuxo(11),
O => d(11)
);
d_11_IOBUF_IBUF : X_BUF
port map (
I => d(11),
O => N4593
);
d_12_IOBUF_OBUFT : X_TRI
port map (
CTL => d_12_IOBUF_OBUFT_GTS_AND,
I => dmuxo(12),
O => d(12)
);
d_12_IOBUF_IBUF : X_BUF
port map (
I => d(12),
O => N4595
);
d_13_IOBUF_OBUFT : X_TRI
port map (
CTL => d_13_IOBUF_OBUFT_GTS_AND,
I => dmuxo(13),
O => d(13)
);
d_13_IOBUF_IBUF : X_BUF
port map (
I => d(13),
O => N4597
);
d_14_IOBUF_OBUFT : X_TRI
port map (
CTL => d_14_IOBUF_OBUFT_GTS_AND,
I => dmuxo(14),
O => d(14)
);
d_14_IOBUF_IBUF : X_BUF
port map (
I => d(14),
O => N4599
);
d_15_IOBUF_OBUFT : X_TRI
port map (
CTL => d_15_IOBUF_OBUFT_GTS_AND,
I => dmuxo(15),
O => d(15)
);
d_15_IOBUF_IBUF : X_BUF
port map (
I => d(15),
O => N4601
);
d_16_IOBUF_OBUFT : X_TRI
port map (
CTL => d_16_IOBUF_OBUFT_GTS_AND,
I => dmuxo(16),
O => d(16)
);
d_16_IOBUF_IBUF : X_BUF
port map (
I => d(16),
O => N4605
);
d_17_IOBUF_OBUFT : X_TRI
port map (
CTL => d_17_IOBUF_OBUFT_GTS_AND,
I => dmuxo(17),
O => d(17)
);
d_17_IOBUF_IBUF : X_BUF
port map (
I => d(17),
O => N4609
);
d_18_IOBUF_OBUFT : X_TRI
port map (
CTL => d_18_IOBUF_OBUFT_GTS_AND,
I => dmuxo(18),
O => d(18)
);
d_18_IOBUF_IBUF : X_BUF
port map (
I => d(18),
O => N4613
);
d_11_IOBUF_OBUFT_GTS_AND_10 : X_AND2
port map (
I0 => NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN1,
O => d_11_IOBUF_OBUFT_GTS_AND
);
d_12_IOBUF_OBUFT_GTS_AND_11 : X_AND2
port map (
I0 => NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN1,
O => d_12_IOBUF_OBUFT_GTS_AND
);
d_13_IOBUF_OBUFT_GTS_AND_12 : X_AND2
port map (
I0 => NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN1,
O => d_13_IOBUF_OBUFT_GTS_AND
);
d_14_IOBUF_OBUFT_GTS_AND_13 : X_AND2
port map (
I0 => NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN1,
O => d_14_IOBUF_OBUFT_GTS_AND
);
d_15_IOBUF_OBUFT_GTS_AND_14 : X_AND2
port map (
I0 => NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN1,
O => d_15_IOBUF_OBUFT_GTS_AND
);
d_20_IOBUF_OBUFT_GTS_AND_15 : X_AND2
port map (
I0 => NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN1,
O => d_20_IOBUF_OBUFT_GTS_AND
);
d_16_IOBUF_OBUFT_GTS_AND_16 : X_AND2
port map (
I0 => NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN1,
O => d_16_IOBUF_OBUFT_GTS_AND
);
d_21_IOBUF_OBUFT_GTS_AND_17 : X_AND2
port map (
I0 => NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN1,
O => d_21_IOBUF_OBUFT_GTS_AND
);
d_17_IOBUF_OBUFT_GTS_AND_18 : X_AND2
port map (
I0 => NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN1,
O => d_17_IOBUF_OBUFT_GTS_AND
);
d_22_IOBUF_OBUFT_GTS_AND_19 : X_AND2
port map (
I0 => NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN1,
O => d_22_IOBUF_OBUFT_GTS_AND
);
d_18_IOBUF_OBUFT_GTS_AND_20 : X_AND2
port map (
I0 => NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN1,
O => d_18_IOBUF_OBUFT_GTS_AND
);
d_23_IOBUF_OBUFT_GTS_AND_21 : X_AND2
port map (
I0 => NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN1,
O => d_23_IOBUF_OBUFT_GTS_AND
);
d_19_IOBUF_OBUFT_GTS_AND_22 : X_AND2
port map (
I0 => NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN1,
O => d_19_IOBUF_OBUFT_GTS_AND
);
d_24_IOBUF_OBUFT_GTS_AND_23 : X_AND2
port map (
I0 => NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN1,
O => d_24_IOBUF_OBUFT_GTS_AND
);
d_25_IOBUF_OBUFT_GTS_AND_24 : X_AND2
port map (
I0 => NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN1,
O => d_25_IOBUF_OBUFT_GTS_AND
);
d_30_IOBUF_OBUFT_GTS_AND_25 : X_AND2
port map (
I0 => NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN1,
O => d_30_IOBUF_OBUFT_GTS_AND
);
d_26_IOBUF_OBUFT_GTS_AND_26 : X_AND2
port map (
I0 => NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN1,
O => d_26_IOBUF_OBUFT_GTS_AND
);
d_31_IOBUF_OBUFT_GTS_AND_27 : X_AND2
port map (
I0 => NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN1,
O => d_31_IOBUF_OBUFT_GTS_AND
);
d_27_IOBUF_OBUFT_GTS_AND_28 : X_AND2
port map (
I0 => NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN1,
O => d_27_IOBUF_OBUFT_GTS_AND
);
d_28_IOBUF_OBUFT_GTS_AND_29 : X_AND2
port map (
I0 => NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN1,
O => d_28_IOBUF_OBUFT_GTS_AND
);
d_29_IOBUF_OBUFT_GTS_AND_30 : X_AND2
port map (
I0 => NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN1,
O => d_29_IOBUF_OBUFT_GTS_AND
);
d_0_IOBUF_OBUFT_GTS_AND_31 : X_AND2
port map (
I0 => NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN1,
O => d_0_IOBUF_OBUFT_GTS_AND
);
d_1_IOBUF_OBUFT_GTS_AND_32 : X_AND2
port map (
I0 => NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN1,
O => d_1_IOBUF_OBUFT_GTS_AND
);
d_2_IOBUF_OBUFT_GTS_AND_33 : X_AND2
port map (
I0 => NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN1,
O => d_2_IOBUF_OBUFT_GTS_AND
);
d_3_IOBUF_OBUFT_GTS_AND_34 : X_AND2
port map (
I0 => NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN1,
O => d_3_IOBUF_OBUFT_GTS_AND
);
d_4_IOBUF_OBUFT_GTS_AND_35 : X_AND2
port map (
I0 => NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN1,
O => d_4_IOBUF_OBUFT_GTS_AND
);
d_5_IOBUF_OBUFT_GTS_AND_36 : X_AND2
port map (
I0 => NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN1,
O => d_5_IOBUF_OBUFT_GTS_AND
);
d_6_IOBUF_OBUFT_GTS_AND_37 : X_AND2
port map (
I0 => NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN1,
O => d_6_IOBUF_OBUFT_GTS_AND
);
d_7_IOBUF_OBUFT_GTS_AND_38 : X_AND2
port map (
I0 => NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN1,
O => d_7_IOBUF_OBUFT_GTS_AND
);
d_8_IOBUF_OBUFT_GTS_AND_39 : X_AND2
port map (
I0 => NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN1,
O => d_8_IOBUF_OBUFT_GTS_AND
);
d_9_IOBUF_OBUFT_GTS_AND_40 : X_AND2
port map (
I0 => NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN1,
O => d_9_IOBUF_OBUFT_GTS_AND
);
d_10_IOBUF_OBUFT_GTS_AND_41 : X_AND2
port map (
I0 => NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN0,
I1 => NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN1,
O => d_10_IOBUF_OBUFT_GTS_AND
);
NlwInverterBlock_reg_a_31_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_31_C
);
NlwBlock_main_top_GND : X_ZERO
port map (
O => GND
);
NlwInverterBlock_reg_b_31_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_31_C
);
NlwInverterBlock_reg_c_31_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_31_C
);
NlwInverterBlock_reg_c_0_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_0_C
);
NlwInverterBlock_reg_c_1_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_1_C
);
NlwInverterBlock_reg_c_2_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_2_C
);
NlwInverterBlock_reg_c_3_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_3_C
);
NlwInverterBlock_reg_c_4_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_4_C
);
NlwInverterBlock_reg_c_5_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_5_C
);
NlwInverterBlock_reg_c_6_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_6_C
);
NlwInverterBlock_reg_c_7_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_7_C
);
NlwInverterBlock_reg_c_8_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_8_C
);
NlwInverterBlock_reg_c_9_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_9_C
);
NlwInverterBlock_reg_c_10_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_10_C
);
NlwInverterBlock_reg_c_11_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_11_C
);
NlwInverterBlock_reg_c_12_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_12_C
);
NlwInverterBlock_reg_c_13_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_13_C
);
NlwInverterBlock_reg_c_14_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_14_C
);
NlwInverterBlock_reg_c_15_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_15_C
);
NlwInverterBlock_reg_c_16_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_16_C
);
NlwInverterBlock_reg_c_17_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_17_C
);
NlwInverterBlock_reg_c_18_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_18_C
);
NlwInverterBlock_reg_c_19_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_19_C
);
NlwInverterBlock_reg_c_20_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_20_C
);
NlwInverterBlock_reg_c_21_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_21_C
);
NlwInverterBlock_reg_c_22_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_22_C
);
NlwInverterBlock_reg_c_23_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_23_C
);
NlwInverterBlock_reg_c_24_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_24_C
);
NlwInverterBlock_reg_c_25_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_25_C
);
NlwInverterBlock_reg_c_26_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_26_C
);
NlwInverterBlock_reg_c_27_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_27_C
);
NlwInverterBlock_reg_c_28_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_28_C
);
NlwInverterBlock_reg_c_29_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_29_C
);
NlwInverterBlock_reg_c_30_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_c_30_C
);
NlwInverterBlock_reg_b_0_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_0_C
);
NlwInverterBlock_reg_b_1_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_1_C
);
NlwInverterBlock_reg_b_2_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_2_C
);
NlwInverterBlock_reg_b_3_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_3_C
);
NlwInverterBlock_reg_b_4_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_4_C
);
NlwInverterBlock_reg_b_5_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_5_C
);
NlwInverterBlock_reg_b_6_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_6_C
);
NlwInverterBlock_reg_b_7_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_7_C
);
NlwInverterBlock_reg_b_8_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_8_C
);
NlwInverterBlock_reg_b_9_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_9_C
);
NlwInverterBlock_reg_b_10_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_10_C
);
NlwInverterBlock_reg_b_11_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_11_C
);
NlwInverterBlock_reg_b_12_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_12_C
);
NlwInverterBlock_reg_b_13_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_13_C
);
NlwInverterBlock_reg_b_14_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_14_C
);
NlwInverterBlock_reg_b_15_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_15_C
);
NlwInverterBlock_reg_b_16_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_16_C
);
NlwInverterBlock_reg_b_17_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_17_C
);
NlwInverterBlock_reg_b_18_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_18_C
);
NlwInverterBlock_reg_b_19_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_19_C
);
NlwInverterBlock_reg_b_20_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_20_C
);
NlwInverterBlock_reg_b_21_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_21_C
);
NlwInverterBlock_reg_b_22_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_22_C
);
NlwInverterBlock_reg_b_23_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_23_C
);
NlwInverterBlock_reg_b_24_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_24_C
);
NlwInverterBlock_reg_b_25_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_25_C
);
NlwInverterBlock_reg_b_26_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_26_C
);
NlwInverterBlock_reg_b_27_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_27_C
);
NlwInverterBlock_reg_b_28_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_28_C
);
NlwInverterBlock_reg_b_29_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_29_C
);
NlwInverterBlock_reg_b_30_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_b_30_C
);
NlwInverterBlock_reg_a_0_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_0_C
);
NlwInverterBlock_reg_a_1_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_1_C
);
NlwInverterBlock_reg_a_2_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_2_C
);
NlwInverterBlock_reg_a_3_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_3_C
);
NlwInverterBlock_reg_a_4_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_4_C
);
NlwInverterBlock_reg_a_5_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_5_C
);
NlwInverterBlock_reg_a_6_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_6_C
);
NlwInverterBlock_reg_a_7_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_7_C
);
NlwInverterBlock_reg_a_8_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_8_C
);
NlwInverterBlock_reg_a_9_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_9_C
);
NlwInverterBlock_reg_a_10_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_10_C
);
NlwInverterBlock_reg_a_11_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_11_C
);
NlwInverterBlock_reg_a_12_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_12_C
);
NlwInverterBlock_reg_a_13_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_13_C
);
NlwInverterBlock_reg_a_14_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_14_C
);
NlwInverterBlock_reg_a_15_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_15_C
);
NlwInverterBlock_reg_a_16_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_16_C
);
NlwInverterBlock_reg_a_17_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_17_C
);
NlwInverterBlock_reg_a_18_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_18_C
);
NlwInverterBlock_reg_a_19_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_19_C
);
NlwInverterBlock_reg_a_20_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_20_C
);
NlwInverterBlock_reg_a_21_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_21_C
);
NlwInverterBlock_reg_a_22_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_22_C
);
NlwInverterBlock_reg_a_23_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_23_C
);
NlwInverterBlock_reg_a_24_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_24_C
);
NlwInverterBlock_reg_a_25_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_25_C
);
NlwInverterBlock_reg_a_26_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_26_C
);
NlwInverterBlock_reg_a_27_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_27_C
);
NlwInverterBlock_reg_a_28_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_28_C
);
NlwInverterBlock_reg_a_29_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_29_C
);
NlwInverterBlock_reg_a_30_C : X_INV
port map (
I => clk_BUFGP,
O => NlwInverterSignal_reg_a_30_C
);
NlwInverterBlock_d_11_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_11_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_11_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_12_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_12_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_12_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_13_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_13_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_13_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_14_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_14_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_14_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_15_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_15_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_15_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_20_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_20_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_20_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_16_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_16_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_16_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_21_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_21_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_21_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_17_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_17_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_17_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_22_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_22_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_22_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_18_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_18_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_18_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_23_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_23_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_23_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_19_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_19_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_19_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_24_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_24_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_24_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_25_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_25_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_25_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_30_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_30_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_30_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_26_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_26_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_26_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_31_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_31_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_31_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_27_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_27_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_27_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_28_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_28_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_28_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_29_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_29_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_29_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_0_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_0_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_0_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_1_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_1_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_1_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_2_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_2_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_2_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_3_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_3_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_3_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_4_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_4_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_4_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_5_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_5_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_5_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_6_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_6_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_6_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_7_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_7_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_7_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_8_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_8_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_8_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_9_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_9_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_9_IOBUF_OBUFT_GTS_AND_IN1
);
NlwInverterBlock_d_10_IOBUF_OBUFT_GTS_AND_IN0 : X_INV
port map (
I => I3_N174,
O => NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN0
);
NlwInverterBlock_d_10_IOBUF_OBUFT_GTS_AND_IN1 : X_INV
port map (
I => GTS,
O => NlwInverterSignal_d_10_IOBUF_OBUFT_GTS_AND_IN1
);
NlwBlockROC : X_ROC
generic map (ROC_WIDTH => 100 ns)
port map (O => GSR);
NlwBlockTOC : X_TOC
port map (O => GTS);
end Structure;
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