Logo
Explore Help
Register Sign In
jens/vhdl
Watch 1
Star 0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Files
master
vhdl/lib/CPUs/MIPS/syn/ise101/project
T
History
jens ac878a877d - fixed paths
2022-07-01 18:15:13 +02:00
..
mips_top.lso
Moved
2015-05-21 06:41:43 +00:00
mips_top.prj
- fixed synth project after fifo refactoring
2021-03-31 09:55:49 +00:00
mips_top.ucf
- use make/ise.mk
2021-03-30 09:17:21 +00:00
mips_top.xcf
- try to add clock buffer constraint
2021-04-02 12:42:01 +00:00
mips_top.xst
- fixed paths
2022-07-01 18:15:13 +02:00
Powered by Gitea Version: 1.27.0 Page: 47ms Template: 5ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API