Compare commits
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 jens
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9c165b1c71 |
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vlib simprim
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set XILINX C:/Programme/Xilinx101/ISE
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vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents_mti.vhd
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vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage_mti.vhd
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vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_SMODEL_mti.vhd
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vcom -93 -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL_mti.vhd
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vlib unisim
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set XILINX C:/Programme/Xilinx101/ISE
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vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vpkg.vhd
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vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vcomp.vhd
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vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_smodel.vhd
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vcom -93 -work unisim $XILINX/vhdl/src/unisims/unisim_vital.vhd
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#
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# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
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# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
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# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
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# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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# FOR A PARTICULAR PURPOSE.
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#
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# (c) Copyright 2005 Xilinx, Inc.
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# All rights reserved.
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#
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# Bus clock nets
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NET "sys_clk" TNM_NET = "sys_clk";
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NET "tft_clk" TNM_NET = "tft_clk";
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NET sys_clk_in TNM_NET = "sys_clk_in";
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TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
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NET sys_clk_in LOC = AE14;
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NET sys_clk_in IOSTANDARD = LVCMOS33;
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NET sys_rst_in LOC = D6;
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NET sys_rst_in PULLUP;
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NET sys_rst_in TIG;
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NET uart_RX LOC = W2;
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NET uart_RX IOSTANDARD = LVCMOS33;
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NET uart_RX TIG;
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NET uart_TX LOC = W1;
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NET uart_TX IOSTANDARD = LVCMOS33;
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NET uart_TX TIG;
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NET ext_irq TIG;
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# Reset timing ignore - treat as async paths
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NET sys_rst TIG;
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NET opb_v20_0_OPB_Rst TIG;
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NET lmb_v10_1_OPB_Rst TIG;
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NET lmb_v10_0_OPB_Rst TIG;
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NET opb_v20_0_Debug_SYS_Rst TIG;
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NET Debug_Rst TIG;
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NET plb_v34_0_PLB_Rst TIG;
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NET dcm_locked TIG;
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# Locate DCM/BUFG - Tools can probably figure them out automatically
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# but just LOC them down to be safe
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INST dcm_0/dcm_0/DCM_ADV_INST LOC = DCM_ADV_X0Y2;
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INST dcm_1/dcm_1/DCM_ADV_INST LOC = DCM_ADV_X0Y4;
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INST dcm_2/dcm_2/DCM_ADV_INST LOC = DCM_ADV_X0Y1;
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INST dcm_0/dcm_0/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y0;
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INST dcm_0/dcm_0/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y1;
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INST dcm_0/dcm_0/CLKDV_BUFG_INST LOC = BUFGCTRL_X0Y2;
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INST dcm_1/dcm_1/CLK0_BUFG_INST LOC = BUFGCTRL_X0Y31;
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INST dcm_1/dcm_1/CLK90_BUFG_INST LOC = BUFGCTRL_X0Y30;
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////////////////////////////////////////////////////////////////////////////
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// Buttons, LEDs, and DIP Switches
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////////////////////////////////////////////////////////////////////////////
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# GPLED 0-3
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NET gpio<0> LOC = G5; #GPLED0
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NET gpio<1> LOC = G6; #GPLED1
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NET gpio<2> LOC = A11; #GPLED2
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NET gpio<3> LOC = A12; #GPLED3
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# North-East-South-West-Center LEDs
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NET gpio<4> LOC = C6; # C LED
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NET gpio<5> LOC = F9; # W LED
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NET gpio<6> LOC = A5; # S LED
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NET gpio<7> LOC = E10; # E LED
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NET gpio<8> LOC = E2; # N LED
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# North-East-South-West-Center Buttons
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NET gpio<9> LOC = B6; # C Button
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NET gpio<10> LOC = E9; # W Button
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NET gpio<11> LOC = A6; # S Button
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NET gpio<12> LOC = F10; # E Button
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NET gpio<13> LOC = E7; # N Button
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# Dip Switches 1-8
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NET gpio<14> LOC = U24; # DIP SW 8
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NET gpio<15> LOC = U25; # DIP SW 7
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NET gpio<16> LOC = V23; # DIP SW 6
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NET gpio<17> LOC = U23; # DIP SW 5
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NET gpio<18> LOC = U26; # DIP SW 4
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NET gpio<19> LOC = T26; # DIP SW 3
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NET gpio<20> LOC = R19; # DIP SW 2
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NET gpio<21> LOC = R20; # DIP SW 1
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NET gpio<14> IOSTANDARD = LVCMOS33;
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NET gpio<15> IOSTANDARD = LVCMOS33;
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NET gpio<16> IOSTANDARD = LVCMOS33;
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NET gpio<17> IOSTANDARD = LVCMOS33;
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NET gpio<18> IOSTANDARD = LVCMOS33;
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NET gpio<19> IOSTANDARD = LVCMOS33;
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NET gpio<20> IOSTANDARD = LVCMOS33;
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NET gpio<21> IOSTANDARD = LVCMOS33;
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#SMA Connectors
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NET gpio<22> LOC = C12; # SMA_IN_N
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NET gpio<23> LOC = C13; # SMA_IN_P
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NET gpio<24> LOC = D7; # SMA_OUT_N
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NET gpio<25> LOC = D8; # SMA_OUT_P
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NET gpio<26> LOC = AD12;# USERCLK
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NET gpio<26> IOSTANDARD = LVCMOS33;
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NET "gpio<*>" PULLDOWN;
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NET "gpio<*>" TIG;
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NET "gpio<*>" SLEW = SLOW;
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NET "gpio<*>" DRIVE = 2;
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NET "gpio<22>" SLEW = FAST;
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NET "gpio<22>" DRIVE = 12;
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NET "gpio<23>" SLEW = FAST;
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NET "gpio<23>" DRIVE = 12;
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NET "gpio<24>" SLEW = FAST;
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NET "gpio<24>" DRIVE = 12;
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NET "gpio<25>" SLEW = FAST;
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NET "gpio<25>" DRIVE = 12;
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NET "gpio2_d_out<*>" TIG;
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NET "gpio2_t_out<*>" TIG;
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NET "gpio2_in<*>" TIG;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for PS/2 Ports
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#------------------------------------------------------------------------------
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#Keyboard
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NET ps2_keyb_clk LOC = D2;
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NET ps2_keyb_clk SLEW = SLOW;
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NET ps2_keyb_clk DRIVE = 2;
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NET ps2_keyb_clk TIG;
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NET ps2_keyb_data LOC = G9;
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NET ps2_keyb_data SLEW = SLOW;
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NET ps2_keyb_data DRIVE = 2;
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NET ps2_keyb_data TIG;
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#Mouse
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NET ps2_mouse_clk LOC = B14;
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NET ps2_mouse_clk SLEW = SLOW;
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NET ps2_mouse_clk DRIVE = 2;
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NET ps2_mouse_clk TIG;
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NET ps2_mouse_data LOC = C14;
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NET ps2_mouse_data SLEW = SLOW;
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NET ps2_mouse_data DRIVE = 2;
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NET ps2_mouse_data TIG;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for IIC Controller
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#------------------------------------------------------------------------------
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NET iic_scl LOC = A17;
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NET iic_sda LOC = B17;
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NET iic_scl SLEW = SLOW;
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NET iic_scl DRIVE = 6;
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NET iic_scl TIG;
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NET iic_sda SLEW = SLOW;
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NET iic_sda DRIVE = 6;
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NET iic_sda TIG;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for AC97 Sound Controller
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#------------------------------------------------------------------------------
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NET ac97_bit_clk LOC = AE10;
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NET ac97_bit_clk IOSTANDARD = LVCMOS33;
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NET ac97_bit_clk PERIOD = 80;
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NET ac97_sdata_in LOC = AD16;
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NET ac97_sdata_in IOSTANDARD = LVCMOS33;
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NET ac97_reset_n LOC = AD10;
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NET ac97_reset_n IOSTANDARD = LVCMOS33;
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NET ac97_reset_n TIG;
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NET ac97_sdata_out LOC = C8;
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NET ac97_sync LOC = D9;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for System ACE MPU / USB
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#------------------------------------------------------------------------------
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NET sysace_clk_in LOC = AF11;
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NET sysace_clk_in IOSTANDARD = LVCMOS33;
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NET sysace_clk_in TNM_NET = "sysace_clk_in";
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# Leave 1 ns margin
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TIMESPEC "TSSYSACE" = PERIOD "sysace_clk_in" 29 ns;
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NET sace_usb_a<0> LOC = U22;
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NET sace_usb_a<1> LOC = Y10;
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NET sace_usb_a<2> LOC = AA10;
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NET sace_usb_a<3> LOC = AC7;
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NET sace_usb_a<4> LOC = Y7;
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NET sace_usb_a<5> LOC = AA9;
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NET sace_usb_a<6> LOC = Y9;
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NET sace_usb_a<*> IOSTANDARD = LVCMOS33;
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NET sace_usb_a<*> SLEW = FAST;
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NET sace_usb_a<*> DRIVE = 8;
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NET sace_mpce LOC = AD5;
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NET sace_mpce IOSTANDARD = LVCMOS33;
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NET sace_mpce SLEW = FAST;
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NET sace_mpce DRIVE = 8;
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NET sace_usb_d<0> LOC = AB7;
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NET sace_usb_d<1> LOC = AC9;
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NET sace_usb_d<2> LOC = AB9;
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NET sace_usb_d<3> LOC = AE6;
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NET sace_usb_d<4> LOC = AD6;
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NET sace_usb_d<5> LOC = AF9;
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NET sace_usb_d<6> LOC = AE9;
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NET sace_usb_d<7> LOC = AD8;
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NET sace_usb_d<8> LOC = AC8;
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NET sace_usb_d<9> LOC = AF4;
|
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NET sace_usb_d<10> LOC = AE4;
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NET sace_usb_d<11> LOC = AD3;
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NET sace_usb_d<12> LOC = AC3;
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NET sace_usb_d<13> LOC = AF6;
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NET sace_usb_d<14> LOC = AF5;
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NET sace_usb_d<15> LOC = AA7;
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NET sace_usb_d<*> IOSTANDARD = LVCMOS33;
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NET sace_usb_d<*> SLEW = FAST;
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NET sace_usb_d<*> DRIVE = 8;
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NET sace_usb_d<*> PULLDOWN;
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NET sace_usb_oen LOC = AA8;
|
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NET sace_usb_oen IOSTANDARD = LVCMOS33;
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NET sace_usb_oen SLEW = FAST;
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NET sace_usb_oen DRIVE = 8;
|
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NET sace_usb_wen LOC = Y8;
|
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NET sace_usb_wen IOSTANDARD = LVCMOS33;
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NET sace_usb_wen SLEW = FAST;
|
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|
NET sace_usb_wen DRIVE = 8;
|
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|
NET sysace_mpirq LOC = AD4;
|
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|
NET sysace_mpirq IOSTANDARD = LVCMOS33;
|
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|
NET sysace_mpirq TIG;
|
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|
NET sysace_mpirq PULLDOWN;
|
||||||
|
|
||||||
|
NET usb_csn LOC = AF10;
|
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|
NET usb_csn IOSTANDARD = LVCMOS33;
|
||||||
|
NET usb_csn SLEW = FAST;
|
||||||
|
NET usb_csn DRIVE = 8;
|
||||||
|
NET usb_hpi_reset_n LOC = A7;
|
||||||
|
NET usb_hpi_reset_n IOSTANDARD = LVCMOS25;
|
||||||
|
NET usb_hpi_reset_n TIG;
|
||||||
|
NET usb_hpi_int LOC = V5;
|
||||||
|
NET usb_hpi_int IOSTANDARD = LVCMOS33;
|
||||||
|
NET usb_hpi_int TIG;
|
||||||
|
NET usb_hpi_int PULLDOWN;
|
||||||
|
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
# IO Pad Location Constraints / Properties for DDR Controllers
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
NET ddr_ad<0> LOC = C26; # DDR_A0
|
||||||
|
NET ddr_ad<1> LOC = E17; # DDR_A1
|
||||||
|
NET ddr_ad<2> LOC = D18; # DDR_A2
|
||||||
|
NET ddr_ad<3> LOC = C19; # DDR_A3
|
||||||
|
NET ddr_ad<4> LOC = F17; # DDR_A4
|
||||||
|
NET ddr_ad<5> LOC = B18; # DDR_A5
|
||||||
|
NET ddr_ad<6> LOC = B20; # DDR_A6
|
||||||
|
NET ddr_ad<7> LOC = C20; # DDR_A7
|
||||||
|
NET ddr_ad<8> LOC = D20; # DDR_A8
|
||||||
|
NET ddr_ad<9> LOC = C21; # DDR_A9
|
||||||
|
NET ddr_ad<10> LOC = A18; # DDR_A10
|
||||||
|
NET ddr_ad<11> LOC = B21; # DDR_A11
|
||||||
|
NET ddr_ad<12> LOC = A24; # DDR_A12
|
||||||
|
NET ddr_ba<0> LOC = B12; # DDR_BA0
|
||||||
|
NET ddr_ba<1> LOC = A16; # DDR_BA1
|
||||||
|
NET ddr_casb LOC = F23; # DDR_CAS_N
|
||||||
|
NET ddr_cke LOC = G22; # DDR_CKE
|
||||||
|
NET ddr_csb LOC = G21; # DDR_CS_N
|
||||||
|
NET ddr_rasb LOC = F24; # DDR_RAS_N
|
||||||
|
NET ddr_web LOC = A23; # DDR_WE_N
|
||||||
|
|
||||||
|
NET ddr_clk LOC = A10; # DDR_CK1_P
|
||||||
|
NET ddr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||||
|
NET ddr_clkb LOC = B10; # DDR_CK1_N
|
||||||
|
|
||||||
|
NET ddr_dm<0> LOC = G19; # DDR_DM0
|
||||||
|
NET ddr_dm<1> LOC = G24; # DDR_DM1
|
||||||
|
NET ddr_dm<2> LOC = G20; # DDR_DM2
|
||||||
|
NET ddr_dm<3> LOC = C22; # DDR_DM3
|
||||||
|
|
||||||
|
NET ddr_dqs<0> LOC = D25; # DDR_DQS0
|
||||||
|
NET ddr_dqs<1> LOC = G18; # DDR_DQS1
|
||||||
|
NET ddr_dqs<2> LOC = G17; # DDR_DQS2
|
||||||
|
NET ddr_dqs<3> LOC = D26; # DDR_DQS3
|
||||||
|
|
||||||
|
NET ddr_dq<0> LOC = H20; # DDR_D0
|
||||||
|
NET ddr_dq<1> LOC = E23; # DDR_D1
|
||||||
|
NET ddr_dq<2> LOC = H26; # DDR_D2
|
||||||
|
NET ddr_dq<3> LOC = H22; # DDR_D3
|
||||||
|
NET ddr_dq<4> LOC = E25; # DDR_D4
|
||||||
|
NET ddr_dq<5> LOC = E26; # DDR_D5
|
||||||
|
NET ddr_dq<6> LOC = F26; # DDR_D6
|
||||||
|
NET ddr_dq<7> LOC = E24; # DDR_D7
|
||||||
|
NET ddr_dq<8> LOC = E20; # DDR_D8
|
||||||
|
NET ddr_dq<9> LOC = A22; # DDR_D9
|
||||||
|
NET ddr_dq<10> LOC = C23; # DDR_D10
|
||||||
|
NET ddr_dq<11> LOC = C24; # DDR_D11
|
||||||
|
NET ddr_dq<12> LOC = A20; # DDR_D12
|
||||||
|
NET ddr_dq<13> LOC = A21; # DDR_D13
|
||||||
|
NET ddr_dq<14> LOC = D24; # DDR_D14
|
||||||
|
NET ddr_dq<15> LOC = E18; # DDR_D15
|
||||||
|
NET ddr_dq<16> LOC = F18; # DDR_D16
|
||||||
|
NET ddr_dq<17> LOC = A19; # DDR_D17
|
||||||
|
NET ddr_dq<18> LOC = F19; # DDR_D18
|
||||||
|
NET ddr_dq<19> LOC = B23; # DDR_D19
|
||||||
|
NET ddr_dq<20> LOC = E21; # DDR_D20
|
||||||
|
NET ddr_dq<21> LOC = D22; # DDR_D21
|
||||||
|
NET ddr_dq<22> LOC = D23; # DDR_D22
|
||||||
|
NET ddr_dq<23> LOC = B24; # DDR_D23
|
||||||
|
NET ddr_dq<24> LOC = E22; # DDR_D24
|
||||||
|
NET ddr_dq<25> LOC = F20; # DDR_D25
|
||||||
|
NET ddr_dq<26> LOC = H23; # DDR_D26
|
||||||
|
NET ddr_dq<27> LOC = G25; # DDR_D27
|
||||||
|
NET ddr_dq<28> LOC = G26; # DDR_D28
|
||||||
|
NET ddr_dq<29> LOC = H25; # DDR_D29
|
||||||
|
NET ddr_dq<30> LOC = H24; # DDR_D30
|
||||||
|
NET ddr_dq<31> LOC = H21; # DDR_D31
|
||||||
|
|
||||||
|
NET ddr_ad<*> IOSTANDARD = SSTL2_I;
|
||||||
|
NET ddr_ba<*> IOSTANDARD = SSTL2_I;
|
||||||
|
NET ddr_casb IOSTANDARD = SSTL2_I;
|
||||||
|
NET ddr_cke IOSTANDARD = SSTL2_I;
|
||||||
|
NET ddr_clk IOSTANDARD = SSTL2_I;
|
||||||
|
NET ddr_clk_fb IOSTANDARD = LVCMOS25;
|
||||||
|
NET ddr_clkb IOSTANDARD = SSTL2_I;
|
||||||
|
NET ddr_casb IOSTANDARD = SSTL2_I;
|
||||||
|
NET ddr_csb IOSTANDARD = SSTL2_I;
|
||||||
|
NET ddr_rasb IOSTANDARD = SSTL2_I;
|
||||||
|
NET ddr_web IOSTANDARD = SSTL2_I;
|
||||||
|
|
||||||
|
NET ddr_dqs<*> IOSTANDARD = SSTL2_II;
|
||||||
|
NET ddr_dm<*> IOSTANDARD = SSTL2_II;
|
||||||
|
NET ddr_dq<*> IOSTANDARD = SSTL2_II;
|
||||||
|
|
||||||
|
// Timing Constraint for DDR Feedback Clock
|
||||||
|
NET "ddr_clk_fb" TNM_NET = "ddr_clk_fb";
|
||||||
|
TIMESPEC "TSDDR_FB" = PERIOD "ddr_clk_fb" 9.9 ns;
|
||||||
|
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
# IO Pad Location Constraints / Properties for TFT VGA LCD Controller
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
NET tft_lcd_b<0> LOC = L26; # VGA_B2
|
||||||
|
NET tft_lcd_b<0> IOSTANDARD = LVCMOS33;
|
||||||
|
NET tft_lcd_b<1> LOC = C5; # VGA_B3
|
||||||
|
NET tft_lcd_b<2> LOC = C7; # VGA_B4
|
||||||
|
NET tft_lcd_b<3> LOC = B7; # VGA_B5
|
||||||
|
NET tft_lcd_b<4> LOC = G8; # VGA_B6
|
||||||
|
NET tft_lcd_b<5> LOC = F8; # VGA_B7
|
||||||
|
NET tft_lcd_b<*> SLEW = FAST;
|
||||||
|
NET tft_lcd_b<*> DRIVE = 8;
|
||||||
|
|
||||||
|
NET tft_lcd_clk LOC = AF8;
|
||||||
|
NET tft_lcd_clk IOSTANDARD = LVDCI_33;
|
||||||
|
NET tft_lcd_clk SLEW = FAST;
|
||||||
|
NET tft_lcd_clk DRIVE = 8;
|
||||||
|
|
||||||
|
NET tft_lcd_g<0> LOC = M20; # VGA_G2
|
||||||
|
NET tft_lcd_g<0> IOSTANDARD = LVCMOS33;
|
||||||
|
NET tft_lcd_g<1> LOC = E4; # VGA_G3
|
||||||
|
NET tft_lcd_g<2> LOC = D3; # VGA_G4
|
||||||
|
NET tft_lcd_g<3> LOC = H7; # VGA_G5
|
||||||
|
NET tft_lcd_g<4> LOC = H8; # VGA_G6
|
||||||
|
NET tft_lcd_g<5> LOC = C1; # VGA_G7
|
||||||
|
NET tft_lcd_g<*> SLEW = FAST;
|
||||||
|
NET tft_lcd_g<*> DRIVE = 8;
|
||||||
|
|
||||||
|
NET tft_lcd_hsync LOC = C10;
|
||||||
|
NET tft_lcd_hsync SLEW = FAST;
|
||||||
|
NET tft_lcd_hsync DRIVE = 8;
|
||||||
|
|
||||||
|
NET tft_lcd_r<0> LOC = N25; #VGA_R2
|
||||||
|
NET tft_lcd_r<0> IOSTANDARD = LVCMOS33;
|
||||||
|
NET tft_lcd_r<1> LOC = C2; #VGA_R3
|
||||||
|
NET tft_lcd_r<2> LOC = G7; #VGA_R4
|
||||||
|
NET tft_lcd_r<3> LOC = F7; #VGA_R5
|
||||||
|
NET tft_lcd_r<4> LOC = E5; #VGA_R6
|
||||||
|
NET tft_lcd_r<5> LOC = E6; #VGA_R7
|
||||||
|
NET tft_lcd_r<*> SLEW = FAST;
|
||||||
|
NET tft_lcd_r<*> DRIVE = 8;
|
||||||
|
|
||||||
|
NET tft_lcd_vsync LOC = A8;
|
||||||
|
NET tft_lcd_vsync SLEW = FAST;
|
||||||
|
NET tft_lcd_vsync DRIVE = 8;
|
||||||
|
|
||||||
|
TIMESPEC "TSPLB_TFT" = FROM "sys_clk" TO "tft_clk" TIG;
|
||||||
|
TIMESPEC "TSTFT_PLB" = FROM "tft_clk" TO "sys_clk" TIG;
|
||||||
|
|
||||||
|
////////////////////////////////////////////////////////////////////////////
|
||||||
|
// Misc Board Signals
|
||||||
|
////////////////////////////////////////////////////////////////////////////
|
||||||
|
|
||||||
|
NET plb_error LOC = L24;
|
||||||
|
NET plb_error IOSTANDARD = LVCMOS33;
|
||||||
|
NET plb_error TIG;
|
||||||
|
NET opb_error LOC = V6;
|
||||||
|
NET opb_error IOSTANDARD = LVCMOS33;
|
||||||
|
NET opb_error TIG;
|
||||||
|
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
# IO Pad Location Constraints / Properties for Ethernet
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
NET phy_col LOC = E3;
|
||||||
|
NET phy_crs LOC = D5;
|
||||||
|
NET phy_dv LOC = A9;
|
||||||
|
NET phy_rx_clk LOC = B15;
|
||||||
|
NET phy_rx_data<3> LOC = C4;
|
||||||
|
NET phy_rx_data<2> LOC = D4;
|
||||||
|
NET phy_rx_data<1> LOC = E1;
|
||||||
|
NET phy_rx_data<0> LOC = F1;
|
||||||
|
|
||||||
|
NET phy_rx_er LOC = B9;
|
||||||
|
NET phy_tx_clk LOC = C15;
|
||||||
|
NET phy_mii_clk LOC = D1;
|
||||||
|
NET phy_mii_int_n LOC = H4;
|
||||||
|
NET phy_rst_n LOC = D10;
|
||||||
|
NET phy_tx_data<3> LOC = G1;
|
||||||
|
NET phy_tx_data<2> LOC = H3;
|
||||||
|
NET phy_tx_data<1> LOC = H2;
|
||||||
|
NET phy_tx_data<0> LOC = H1;
|
||||||
|
NET phy_tx_en LOC = F4;
|
||||||
|
NET phy_tx_er LOC = F3;
|
||||||
|
NET phy_mii_data LOC = G4;
|
||||||
|
|
||||||
|
NET phy_mii_int_n PULLUP;
|
||||||
|
|
||||||
|
NET phy_mii_int_n TIG;
|
||||||
|
NET phy_rst_n TIG;
|
||||||
|
|
||||||
|
# Timing Constraints (these are recommended in documentation and
|
||||||
|
# are unaltered except for the TIG)
|
||||||
|
NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
|
||||||
|
NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
|
||||||
|
TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
|
||||||
|
TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
|
||||||
|
|
||||||
|
NET "phy_tx_clk" MAXSKEW= 1.0 ns;
|
||||||
|
NET "phy_rx_clk" MAXSKEW= 1.0 ns;
|
||||||
|
NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
|
||||||
|
NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
|
||||||
|
|
||||||
|
NET "phy_rx_data<3>" IOBDELAY=NONE;
|
||||||
|
NET "phy_rx_data<2>" IOBDELAY=NONE;
|
||||||
|
NET "phy_rx_data<1>" IOBDELAY=NONE;
|
||||||
|
NET "phy_rx_data<0>" IOBDELAY=NONE;
|
||||||
|
NET "phy_dv" IOBDELAY=NONE;
|
||||||
|
NET "phy_rx_er" IOBDELAY=NONE;
|
||||||
|
NET "phy_crs" IOBDELAY=NONE;
|
||||||
|
NET "phy_col" IOBDELAY=NONE;
|
||||||
|
|
||||||
|
# Workaround to help meet "phy_rx_clk MAXSKEW= 1.0 ns" constraint
|
||||||
|
INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I0" IOB=FALSE;
|
||||||
|
INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I1" IOB=FALSE;
|
||||||
|
INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I2" IOB=FALSE;
|
||||||
|
INST "opb_ethernet_0/opb_ethernet_0/RX_FF_I3" IOB=FALSE;
|
||||||
|
INST "opb_ethernet_0/opb_ethernet_0/DVD_FF" IOB=FALSE;
|
||||||
|
INST "opb_ethernet_0/opb_ethernet_0/RER_FF" IOB=FALSE;
|
||||||
|
|
||||||
|
# Timing ignores (to specify unconstrained paths)
|
||||||
|
TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG;
|
||||||
|
TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG;
|
||||||
|
TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG;
|
||||||
|
TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG;
|
||||||
|
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
# IO Pad Location Constraints / Properties for SRAM/FLASH
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
NET sram_clk LOC = AF7;
|
||||||
|
NET sram_clk_fb LOC = AD17;
|
||||||
|
NET flash_a23 LOC = T21;
|
||||||
|
NET sram_flash_addr<22> LOC = U20;
|
||||||
|
NET sram_flash_addr<21> LOC = T19;
|
||||||
|
NET sram_flash_addr<20> LOC = AC5;
|
||||||
|
NET sram_flash_addr<19> LOC = AB5;
|
||||||
|
NET sram_flash_addr<18> LOC = AC4;
|
||||||
|
NET sram_flash_addr<17> LOC = AB4;
|
||||||
|
|
||||||
|
NET sram_flash_addr<16> LOC = AB3;
|
||||||
|
NET sram_flash_addr<15> LOC = AA4;
|
||||||
|
NET sram_flash_addr<14> LOC = AA3;
|
||||||
|
NET sram_flash_addr<13> LOC = W5;
|
||||||
|
NET sram_flash_addr<12> LOC = W6;
|
||||||
|
NET sram_flash_addr<11> LOC = W3;
|
||||||
|
NET sram_flash_addr<10> LOC = AF3;
|
||||||
|
NET sram_flash_addr<9> LOC = AE3;
|
||||||
|
NET sram_flash_addr<8> LOC = AD2;
|
||||||
|
NET sram_flash_addr<7> LOC = AD1;
|
||||||
|
NET sram_flash_addr<6> LOC = AC2;
|
||||||
|
NET sram_flash_addr<5> LOC = AC1;
|
||||||
|
NET sram_flash_addr<4> LOC = AB2;
|
||||||
|
NET sram_flash_addr<3> LOC = AB1;
|
||||||
|
NET sram_flash_addr<2> LOC = AA1;
|
||||||
|
NET sram_flash_addr<1> LOC = Y2;
|
||||||
|
NET sram_flash_addr<0> LOC = Y1;
|
||||||
|
NET sram_flash_data<31> LOC = F14;
|
||||||
|
NET sram_flash_data<30> LOC = F13;
|
||||||
|
NET sram_flash_data<29> LOC = F12;
|
||||||
|
NET sram_flash_data<28> LOC = F11;
|
||||||
|
NET sram_flash_data<27> LOC = F16;
|
||||||
|
NET sram_flash_data<26> LOC = F15;
|
||||||
|
NET sram_flash_data<25> LOC = D14;
|
||||||
|
NET sram_flash_data<24> LOC = D13;
|
||||||
|
NET sram_flash_data<23> LOC = D15;
|
||||||
|
NET sram_flash_data<22> LOC = E14;
|
||||||
|
NET sram_flash_data<21> LOC = C11;
|
||||||
|
NET sram_flash_data<20> LOC = D11;
|
||||||
|
NET sram_flash_data<19> LOC = D16;
|
||||||
|
NET sram_flash_data<18> LOC = C16;
|
||||||
|
NET sram_flash_data<17> LOC = E13;
|
||||||
|
NET sram_flash_data<16> LOC = D12;
|
||||||
|
NET sram_flash_data<15> LOC = AA14;
|
||||||
|
NET sram_flash_data<14> LOC = AB14;
|
||||||
|
NET sram_flash_data<13> LOC = AC12;
|
||||||
|
NET sram_flash_data<12> LOC = AC11;
|
||||||
|
NET sram_flash_data<11> LOC = AA16;
|
||||||
|
NET sram_flash_data<10> LOC = AA15;
|
||||||
|
NET sram_flash_data<9> LOC = AB13;
|
||||||
|
NET sram_flash_data<8> LOC = AA13;
|
||||||
|
NET sram_flash_data<7> LOC = AC14;
|
||||||
|
NET sram_flash_data<6> LOC = AD14;
|
||||||
|
NET sram_flash_data<5> LOC = AA12;
|
||||||
|
NET sram_flash_data<4> LOC = AA11;
|
||||||
|
NET sram_flash_data<3> LOC = AC16;
|
||||||
|
NET sram_flash_data<2> LOC = AC15;
|
||||||
|
NET sram_flash_data<1> LOC = AC13;
|
||||||
|
NET sram_flash_data<0> LOC = AD13;
|
||||||
|
NET sram_cen LOC = V7;
|
||||||
|
NET sram_flash_oe_n LOC = AC6;
|
||||||
|
NET sram_flash_we_n LOC = AB6;
|
||||||
|
NET sram_bw<3> LOC = Y3; #Y4;
|
||||||
|
NET sram_bw<2> LOC = Y4; #Y3;
|
||||||
|
NET sram_bw<1> LOC = Y5; #Y6;
|
||||||
|
NET sram_bw<0> LOC = Y6; #Y5;
|
||||||
|
NET flash_ce LOC = W7;
|
||||||
|
NET sram_adv_ld_n LOC = W4;
|
||||||
|
NET sram_mode LOC = V26;
|
||||||
|
|
||||||
|
NET sram_clk IOSTANDARD = LVCMOS33;
|
||||||
|
NET sram_clk DRIVE = 16;
|
||||||
|
NET sram_clk SLEW = FAST;
|
||||||
|
NET sram_clk_fb IOSTANDARD = LVCMOS33;
|
||||||
|
|
||||||
|
NET flash_a23 IOSTANDARD = LVDCI_33;
|
||||||
|
NET flash_a23 SLEW = FAST;
|
||||||
|
NET flash_a23 DRIVE = 8;
|
||||||
|
|
||||||
|
NET sram_mode IOSTANDARD = LVDCI_33;
|
||||||
|
NET sram_mode SLEW = FAST;
|
||||||
|
NET sram_mode DRIVE = 8;
|
||||||
|
|
||||||
|
NET sram_flash_addr<*> IOSTANDARD = LVDCI_33;
|
||||||
|
NET sram_flash_addr<*> SLEW = FAST;
|
||||||
|
NET sram_flash_addr<*> DRIVE = 8;
|
||||||
|
|
||||||
|
NET sram_flash_data<*> IOSTANDARD = LVCMOS33;
|
||||||
|
NET sram_flash_data<*> DRIVE = 12;
|
||||||
|
NET sram_flash_data<*> SLEW = FAST;
|
||||||
|
NET sram_flash_data<*> PULLDOWN;
|
||||||
|
|
||||||
|
NET sram_flash_oe_n IOSTANDARD = LVDCI_33;
|
||||||
|
NET sram_flash_oe_n SLEW = FAST;
|
||||||
|
NET sram_flash_oe_n DRIVE = 8;
|
||||||
|
|
||||||
|
NET sram_flash_we_n IOSTANDARD = LVDCI_33;
|
||||||
|
NET sram_flash_we_n SLEW = FAST;
|
||||||
|
NET sram_flash_we_n DRIVE = 8;
|
||||||
|
|
||||||
|
NET sram_bw<*> IOSTANDARD = LVDCI_33;
|
||||||
|
NET sram_bw<*> SLEW = FAST;
|
||||||
|
NET sram_bw<*> DRIVE = 8;
|
||||||
|
|
||||||
|
NET flash_ce IOSTANDARD = LVDCI_33;
|
||||||
|
NET flash_ce SLEW = FAST;
|
||||||
|
NET flash_ce DRIVE = 8;
|
||||||
|
|
||||||
|
NET sram_cen IOSTANDARD = LVDCI_33;
|
||||||
|
NET sram_cen SLEW = FAST;
|
||||||
|
NET sram_cen DRIVE = 8;
|
||||||
|
|
||||||
|
NET sram_adv_ld_n IOSTANDARD = LVDCI_33;
|
||||||
|
NET sram_adv_ld_n SLEW = FAST;
|
||||||
|
NET sram_adv_ld_n DRIVE = 8;
|
||||||
|
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
# IO Pad Location Constraints / Properties for Expansion Header GPIO
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
NET gpio_exp_hdr1<31> LOC = AF24; # HDR1_64
|
||||||
|
NET gpio_exp_hdr1<30> LOC = AE24; # HDR1_62
|
||||||
|
NET gpio_exp_hdr1<29> LOC = AD22; # HDR1_8
|
||||||
|
NET gpio_exp_hdr1<28> LOC = AB21; # HDR1_58
|
||||||
|
NET gpio_exp_hdr1<27> LOC = W20; # HDR1_44
|
||||||
|
NET gpio_exp_hdr1<26> LOC = W21; # HDR1_48
|
||||||
|
NET gpio_exp_hdr1<25> LOC = AB22; # HDR1_14
|
||||||
|
NET gpio_exp_hdr1<24> LOC = AD25; # HDR1_20
|
||||||
|
NET gpio_exp_hdr1<23> LOC = W22; # HDR1_46
|
||||||
|
NET gpio_exp_hdr1<22> LOC = V21; # HDR1_56
|
||||||
|
NET gpio_exp_hdr1<21> LOC = V22; # HDR1_54
|
||||||
|
NET gpio_exp_hdr1<20> LOC = AC22; # HDR1_16
|
||||||
|
NET gpio_exp_hdr1<19> LOC = AD26; # HDR1_18
|
||||||
|
NET gpio_exp_hdr1<18> LOC = AC26; # HDR1_34
|
||||||
|
NET gpio_exp_hdr1<17> LOC = AD23; # HDR1_6
|
||||||
|
NET gpio_exp_hdr1<16> LOC = AB25; # HDR1_30
|
||||||
|
NET gpio_exp_hdr1<15> LOC = AC23; # HDR1_4
|
||||||
|
NET gpio_exp_hdr1<14> LOC = AB26; # HDR1_24
|
||||||
|
NET gpio_exp_hdr1<13> LOC = AC21; # HDR1_60
|
||||||
|
NET gpio_exp_hdr1<12> LOC = AA23; # HDR1_10
|
||||||
|
NET gpio_exp_hdr1<11> LOC = AA26; # HDR1_22
|
||||||
|
NET gpio_exp_hdr1<10> LOC = Y25; # HDR1_40
|
||||||
|
NET gpio_exp_hdr1<9> LOC = Y26; # HDR1_38
|
||||||
|
NET gpio_exp_hdr1<8> LOC = W26; # HDR1_50
|
||||||
|
NET gpio_exp_hdr1<7> LOC = AB23; # HDR1_12
|
||||||
|
NET gpio_exp_hdr1<6> LOC = Y24; # HDR1_26
|
||||||
|
NET gpio_exp_hdr1<5> LOC = AB24; # HDR1_32
|
||||||
|
NET gpio_exp_hdr1<4> LOC = W25; # HDR1_52
|
||||||
|
NET gpio_exp_hdr1<3> LOC = AC24; # HDR1_2
|
||||||
|
NET gpio_exp_hdr1<2> LOC = AC25; # HDR1_36
|
||||||
|
NET gpio_exp_hdr1<1> LOC = V20; # HDR1_42
|
||||||
|
NET gpio_exp_hdr1<0> LOC = AA24; # HDR1_28
|
||||||
|
NET gpio_exp_hdr1<*> TIG;
|
||||||
|
NET gpio_exp_hdr1<*> PULLDOWN;
|
||||||
|
|
||||||
|
NET gpio_exp_hdr2<31> LOC = AF18; # HDR2_40
|
||||||
|
NET gpio_exp_hdr2<30> LOC = AE18; # HDR2_38
|
||||||
|
NET gpio_exp_hdr2<29> LOC = AF19; # HDR2_32
|
||||||
|
NET gpio_exp_hdr2<28> LOC = AF20; # HDR2_30
|
||||||
|
NET gpio_exp_hdr2<27> LOC = AF21; # HDR2_44
|
||||||
|
NET gpio_exp_hdr2<26> LOC = AF22; # HDR2_42
|
||||||
|
NET gpio_exp_hdr2<25> LOC = AF23; # HDR2_24
|
||||||
|
NET gpio_exp_hdr2<24> LOC = AE23; # HDR2_22
|
||||||
|
NET gpio_exp_hdr2<23> LOC = AC18; # HDR2_48
|
||||||
|
NET gpio_exp_hdr2<22> LOC = AB18; # HDR2_46
|
||||||
|
NET gpio_exp_hdr2<21> LOC = AD19; # HDR2_64
|
||||||
|
NET gpio_exp_hdr2<20> LOC = AC19; # HDR2_62
|
||||||
|
NET gpio_exp_hdr2<19> LOC = AE20; # HDR2_16
|
||||||
|
NET gpio_exp_hdr2<18> LOC = AD20; # HDR2_14
|
||||||
|
NET gpio_exp_hdr2<17> LOC = AE21; # HDR2_36
|
||||||
|
NET gpio_exp_hdr2<16> LOC = AD21; # HDR2_34
|
||||||
|
NET gpio_exp_hdr2<15> LOC = AB20; # HDR2_52
|
||||||
|
NET gpio_exp_hdr2<14> LOC = AC20; # HDR2_50
|
||||||
|
NET gpio_exp_hdr2<13> LOC = Y17; # HDR2_56
|
||||||
|
NET gpio_exp_hdr2<12> LOC = AA17; # HDR2_54
|
||||||
|
NET gpio_exp_hdr2<11> LOC = AA19; # HDR2_60
|
||||||
|
NET gpio_exp_hdr2<10> LOC = AA20; # HDR2_58
|
||||||
|
NET gpio_exp_hdr2<9> LOC = Y22; # HDR2_8
|
||||||
|
NET gpio_exp_hdr2<8> LOC = Y23; # HDR2_6
|
||||||
|
NET gpio_exp_hdr2<7> LOC = W23; # HDR2_12
|
||||||
|
NET gpio_exp_hdr2<6> LOC = W24; # HDR2_10
|
||||||
|
NET gpio_exp_hdr2<5> LOC = Y20; # HDR2_20
|
||||||
|
NET gpio_exp_hdr2<4> LOC = Y21; # HDR2_18
|
||||||
|
NET gpio_exp_hdr2<3> LOC = Y19; # HDR2_28
|
||||||
|
NET gpio_exp_hdr2<2> LOC = W19; # HDR2_26
|
||||||
|
NET gpio_exp_hdr2<1> LOC = AA18; # HDR2_4
|
||||||
|
NET gpio_exp_hdr2<0> LOC = Y18; # HDR2_2
|
||||||
|
NET gpio_exp_hdr2<*> TIG;
|
||||||
|
NET gpio_exp_hdr2<*> PULLDOWN;
|
||||||
|
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
# IO Pad Location Constraints / Properties for Character LCD GPIO
|
||||||
|
#------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
NET gpio_char_lcd<6> LOC = AE13; # LCD_E
|
||||||
|
NET gpio_char_lcd<5> LOC = AC17; # LCD_RS
|
||||||
|
NET gpio_char_lcd<4> LOC = AB17; # LCD_RW
|
||||||
|
NET gpio_char_lcd<3> LOC = AF12; # LCD_DB7
|
||||||
|
NET gpio_char_lcd<2> LOC = AE12; # LCD_DB6
|
||||||
|
NET gpio_char_lcd<1> LOC = AC10; # LCD_DB5
|
||||||
|
NET gpio_char_lcd<0> LOC = AB10; # LCD_DB4
|
||||||
|
NET gpio_char_lcd<*> IOSTANDARD = LVCMOS33;
|
||||||
|
NET gpio_char_lcd<*> TIG;
|
||||||
|
NET gpio_char_lcd<*> PULLDOWN;
|
||||||
@@ -4,7 +4,7 @@ TOOLS_DIR=../../../tools
|
|||||||
CFLAGS=-Os -I. -I../ -msoft-float -march=r3000
|
CFLAGS=-Os -I. -I../ -msoft-float -march=r3000
|
||||||
LFLAGS=-M -T bootloader.ld
|
LFLAGS=-M -T bootloader.ld
|
||||||
LIB_DIRS=-L /usr/local/mipsel-elf/lib -L /usr/local/lib/gcc/mipsel-elf/4.3.2
|
LIB_DIRS=-L /usr/local/mipsel-elf/lib -L /usr/local/lib/gcc/mipsel-elf/4.3.2
|
||||||
LIBS=-lc -lgcc
|
LIBS=-lc -lm -lgcc
|
||||||
|
|
||||||
CC=mipsel-elf-gcc
|
CC=mipsel-elf-gcc
|
||||||
LD=mipsel-elf-ld
|
LD=mipsel-elf-ld
|
||||||
|
|||||||
@@ -145,9 +145,13 @@ void Exec_at(void *pEntry)
|
|||||||
|
|
||||||
__asm
|
__asm
|
||||||
(
|
(
|
||||||
"lw $v0, 16($sp)\n"
|
"jr %[pEntry]\n" // jump entry
|
||||||
"nop\n"
|
:
|
||||||
"jr $v0\n" // jump entry
|
: [pEntry] "r" (pEntry)
|
||||||
|
);
|
||||||
|
|
||||||
|
__asm
|
||||||
|
(
|
||||||
"rfe\n"
|
"rfe\n"
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -156,6 +160,7 @@ void Exec_at(void *pEntry)
|
|||||||
".set reorder\n"
|
".set reorder\n"
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
|
|
||||||
void PrintCPUinfo(void)
|
void PrintCPUinfo(void)
|
||||||
{
|
{
|
||||||
int result, rev_id;
|
int result, rev_id;
|
||||||
|
|||||||
@@ -1,6 +1,7 @@
|
|||||||
MEMORY
|
MEMORY
|
||||||
{
|
{
|
||||||
rom : ORIGIN = 0xBFC00000, LENGTH = 0x00002000 /* 8K */
|
rom : ORIGIN = 0xBFC00000, LENGTH = 0x00002000 /* 8K */
|
||||||
|
sram : ORIGIN = 0x40000000, LENGTH = 0x02000000 /* 32M */
|
||||||
}
|
}
|
||||||
|
|
||||||
stack_ptr = 0x7FFFFFF0;
|
stack_ptr = 0x7FFFFFF0;
|
||||||
@@ -39,4 +40,8 @@ SECTIONS
|
|||||||
*(.rodata*)
|
*(.rodata*)
|
||||||
} > rom
|
} > rom
|
||||||
|
|
||||||
|
.data ORIGIN(rom) :
|
||||||
|
{
|
||||||
|
*(.data)
|
||||||
|
} > rom
|
||||||
}
|
}
|
||||||
|
|||||||
Vendored
+1
-1
@@ -2,7 +2,7 @@
|
|||||||
|
|
||||||
PROJECT="mips_top"
|
PROJECT="mips_top"
|
||||||
DIST_FILE="./files.dist"
|
DIST_FILE="./files.dist"
|
||||||
DIST_DIR="./release/mips.r10a"
|
DIST_DIR="./release/mips.r10"
|
||||||
|
|
||||||
# ---------------------------------------------------------------
|
# ---------------------------------------------------------------
|
||||||
mkdir -p $DIST_DIR/src
|
mkdir -p $DIST_DIR/src
|
||||||
|
|||||||
@@ -31,11 +31,9 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a
|
|||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
|
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d
|
||||||
add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
|
add wave -noupdate -format Logic /tb_mips_top/flash_cs_n
|
||||||
add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
|
add wave -noupdate -format Logic /tb_mips_top/flash_oe_n
|
||||||
add wave -noupdate -format Literal /tb_mips_top/flash_be_n
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
|
add wave -noupdate -format Logic /tb_mips_top/sram_cs_n
|
||||||
add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
|
add wave -noupdate -format Literal /tb_mips_top/sram_wr_n
|
||||||
add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
|
add wave -noupdate -format Logic /tb_mips_top/sram_oe_n
|
||||||
add wave -noupdate -format Literal /tb_mips_top/sram_be_n
|
|
||||||
add wave -noupdate -divider ALU
|
add wave -noupdate -divider ALU
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
|
add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu
|
||||||
@@ -51,13 +49,8 @@ add wave -noupdate -format Logic /tb_mips_top/clk
|
|||||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
|
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage
|
||||||
add wave -noupdate -format Logic /tb_mips_top/clk
|
add wave -noupdate -format Logic /tb_mips_top/clk
|
||||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
|
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage
|
||||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_rst
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run
|
|
||||||
add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/run_en
|
|
||||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem
|
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 1} {1375665640 ps} 0}
|
WaveRestoreCursors {{Cursor 1} {1199854590 ps} 0}
|
||||||
configure wave -namecolwidth 188
|
configure wave -namecolwidth 188
|
||||||
configure wave -valuecolwidth 100
|
configure wave -valuecolwidth 100
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@@ -71,4 +64,4 @@ configure wave -gridperiod 100
|
|||||||
configure wave -griddelta 40
|
configure wave -griddelta 40
|
||||||
configure wave -timeline 1
|
configure wave -timeline 1
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {0 ps} {1680 us}
|
WaveRestoreZoom {0 ps} {1260 us}
|
||||||
|
|||||||
@@ -40,7 +40,6 @@ package async_defs is
|
|||||||
pol_cs => '0',
|
pol_cs => '0',
|
||||||
pol_oe => '0',
|
pol_oe => '0',
|
||||||
pol_we => '0',
|
pol_we => '0',
|
||||||
pol_be => '0',
|
|
||||||
pol_rst => '0'
|
pol_rst => '0'
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -55,7 +54,6 @@ package async_defs is
|
|||||||
pol_cs => '0',
|
pol_cs => '0',
|
||||||
pol_oe => '0',
|
pol_oe => '0',
|
||||||
pol_we => '0',
|
pol_we => '0',
|
||||||
pol_be => '0',
|
|
||||||
pol_rst => '0'
|
pol_rst => '0'
|
||||||
);
|
);
|
||||||
|
|
||||||
|
|||||||
@@ -147,7 +147,6 @@ architecture behavior of biu is
|
|||||||
signal DAT_I_dmem_rd : word_t;
|
signal DAT_I_dmem_rd : word_t;
|
||||||
signal DAT_O_dmem_wr : word_t;
|
signal DAT_O_dmem_wr : word_t;
|
||||||
signal SEL_O_dmem_wr : unsigned(3 downto 0);
|
signal SEL_O_dmem_wr : unsigned(3 downto 0);
|
||||||
signal SEL_O_dmem_rd : unsigned(3 downto 0);
|
|
||||||
signal dcached : std_logic;
|
signal dcached : std_logic;
|
||||||
signal dcache_en : std_logic;
|
signal dcache_en : std_logic;
|
||||||
signal uncached_access : std_logic;
|
signal uncached_access : std_logic;
|
||||||
@@ -309,9 +308,7 @@ inst_bout_fifo: entity work.fifo_sync_dist
|
|||||||
ADDR_O_dcache when dcache_mem_gnt = '1' else
|
ADDR_O_dcache when dcache_mem_gnt = '1' else
|
||||||
ADDR_O_icache when icache_mem_gnt = '1' else (others => '-');
|
ADDR_O_icache when icache_mem_gnt = '1' else (others => '-');
|
||||||
|
|
||||||
bout_fifo_sel_in <= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else
|
bout_fifo_sel_in <= SEL_O_dmem_wr when dmem_mem_wr_gnt = '1' else (others => '0');
|
||||||
SEL_O_dmem_rd when dmem_mem_rd_gnt = '1' else (others => '1');
|
|
||||||
|
|
||||||
bout_fifo_we_in <= '1' when dmem_mem_wr_gnt = '1' else '0';
|
bout_fifo_we_in <= '1' when dmem_mem_wr_gnt = '1' else '0';
|
||||||
|
|
||||||
-- Instantiate synchronous FIFO
|
-- Instantiate synchronous FIFO
|
||||||
@@ -385,7 +382,6 @@ dmem_rd_regs:
|
|||||||
if rising_edge(CLK_I) then
|
if rising_edge(CLK_I) then
|
||||||
if cpu_dmem_en = '1' and busy = '0' then
|
if cpu_dmem_en = '1' and busy = '0' then
|
||||||
ADDR_O_dmem_rd <= cpu_dmem_addr;
|
ADDR_O_dmem_rd <= cpu_dmem_addr;
|
||||||
SEL_O_dmem_rd <= cpu_dmem_be;
|
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|||||||
@@ -625,7 +625,7 @@ proc_stage_DMEM_ADDR:
|
|||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp) after 1 ns;
|
dmem_be <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns;
|
||||||
dmem_we <= EX_stage.ctrl.dmem_we;
|
dmem_we <= EX_stage.ctrl.dmem_we;
|
||||||
dmem_dout <= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
|
dmem_dout <= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
|
||||||
dmem_addr <= EX_stage.va;
|
dmem_addr <= EX_stage.va;
|
||||||
@@ -867,9 +867,7 @@ proc_stage_WB_p:
|
|||||||
if rising_edge(clk_1) then
|
if rising_edge(clk_1) then
|
||||||
if rst = '1' then
|
if rst = '1' then
|
||||||
WB_stage.op <= NOP;
|
WB_stage.op <= NOP;
|
||||||
WB_stage.wreg_we <= '1';
|
WB_stage.wreg_we <= '0';
|
||||||
WB_stage.reg_wptr <= (others => '0');
|
|
||||||
WB_stage.data <= (others => '0');
|
|
||||||
elsif sdu.WB_stall = '0' then
|
elsif sdu.WB_stall = '0' then
|
||||||
WB_stage.op <= MEM_stage.op;
|
WB_stage.op <= MEM_stage.op;
|
||||||
WB_stage.wreg_we <= MEM_stage.wreg_we;
|
WB_stage.wreg_we <= MEM_stage.wreg_we;
|
||||||
|
|||||||
@@ -51,7 +51,16 @@ architecture Behavioral of reg_dual is
|
|||||||
constant depth : integer := 2**addr_width;
|
constant depth : integer := 2**addr_width;
|
||||||
type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);
|
||||||
|
|
||||||
signal reg_mem : mem_t;
|
function mem_clear(depth : natural) return mem_t is
|
||||||
|
variable result : mem_t;
|
||||||
|
begin
|
||||||
|
for i in 0 to depth-1 loop
|
||||||
|
result(i) := (others => '0');
|
||||||
|
end loop;
|
||||||
|
return result;
|
||||||
|
end mem_clear;
|
||||||
|
|
||||||
|
signal reg_mem : mem_t := mem_clear(depth);
|
||||||
|
|
||||||
begin
|
begin
|
||||||
|
|
||||||
|
|||||||
@@ -86,10 +86,8 @@ ARCHITECTURE behavior OF tb_mips_top IS
|
|||||||
|
|
||||||
signal flash_cs_n : std_logic;
|
signal flash_cs_n : std_logic;
|
||||||
signal flash_oe_n : std_logic;
|
signal flash_oe_n : std_logic;
|
||||||
signal flash_be_n : unsigned(3 downto 0);
|
|
||||||
signal sram_cs_n : std_logic;
|
signal sram_cs_n : std_logic;
|
||||||
signal sram_be_n : unsigned(3 downto 0);
|
signal sram_wr_n : unsigned(3 downto 0);
|
||||||
signal sram_wr_n : std_logic;
|
|
||||||
signal sram_oe_n : std_logic;
|
signal sram_oe_n : std_logic;
|
||||||
signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
|
signal sram_a : unsigned(SRAM_ADDR_WIDTH-1 downto 0);
|
||||||
signal sram_d : unsigned(31 downto 0);
|
signal sram_d : unsigned(31 downto 0);
|
||||||
@@ -256,7 +254,7 @@ inst_flash_port : entity work.async_port_wb
|
|||||||
(
|
(
|
||||||
addr_width => FLASH_ADDR_WIDTH,
|
addr_width => FLASH_ADDR_WIDTH,
|
||||||
data_width => 32,
|
data_width => 32,
|
||||||
byte_sel_width => 4,
|
byte_sel_width => 1,
|
||||||
async_timespec => ts_flash
|
async_timespec => ts_flash
|
||||||
)
|
)
|
||||||
PORT MAP
|
PORT MAP
|
||||||
@@ -278,7 +276,6 @@ inst_flash_port : entity work.async_port_wb
|
|||||||
async_cs => flash_cs_n,
|
async_cs => flash_cs_n,
|
||||||
async_wr => open,
|
async_wr => open,
|
||||||
async_rd => flash_oe_n,
|
async_rd => flash_oe_n,
|
||||||
async_be => flash_be_n,
|
|
||||||
async_rst => open
|
async_rst => open
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -309,7 +306,6 @@ inst_sram_port : entity work.async_port_wb
|
|||||||
async_cs => sram_cs_n,
|
async_cs => sram_cs_n,
|
||||||
async_wr => sram_wr_n,
|
async_wr => sram_wr_n,
|
||||||
async_rd => sram_oe_n,
|
async_rd => sram_oe_n,
|
||||||
async_be => sram_be_n,
|
|
||||||
async_rst => open
|
async_rst => open
|
||||||
);
|
);
|
||||||
|
|
||||||
@@ -336,44 +332,37 @@ inst_uart : entity work.uart_wb
|
|||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
SRAM_READ:
|
SRAM_READ:
|
||||||
process(sram_a, sram_cs_n, sram_oe_n, sram_be_n)
|
process(sram_a, sram_cs_n, sram_oe_n)
|
||||||
begin
|
begin
|
||||||
sram_d <= (others => 'Z') after 10 ns;
|
sram_d <= (others => 'Z');
|
||||||
if sram_oe_n = '0' then
|
if sram_oe_n = '0' then
|
||||||
if sram_cs_n = '0' then
|
if sram_cs_n = '0' then
|
||||||
if sram_be_n(0) = '0' then
|
sram_d <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)));
|
||||||
sram_d(7 downto 0) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) after 10 ns;
|
|
||||||
end if;
|
|
||||||
if sram_be_n(1) = '0' then
|
|
||||||
sram_d(15 downto 8) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) after 10 ns;
|
|
||||||
end if;
|
|
||||||
if sram_be_n(2) = '0' then
|
|
||||||
sram_d(23 downto 16) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) after 10 ns;
|
|
||||||
end if;
|
|
||||||
if sram_be_n(3) = '0' then
|
|
||||||
sram_d(31 downto 24) <= sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) after 10 ns;
|
|
||||||
end if;
|
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
SRAM_WRITE:
|
SRAM_WRITE:
|
||||||
process(sram_wr_n)
|
process(sram_a, sram_cs_n, sram_wr_n)
|
||||||
begin
|
begin
|
||||||
if rising_edge(sram_wr_n) then
|
if rising_edge(sram_wr_n(0)) then
|
||||||
if sram_cs_n = '0' then
|
if sram_cs_n = '0' then
|
||||||
if sram_be_n(0) = '0' then
|
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
|
||||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(7 downto 0) <= sram_d(7 downto 0);
|
end if;
|
||||||
end if;
|
end if;
|
||||||
if sram_be_n(1) = '0' then
|
if rising_edge(sram_wr_n(1)) then
|
||||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
|
if sram_cs_n = '0' then
|
||||||
end if;
|
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(15 downto 8) <= sram_d(15 downto 8);
|
||||||
if sram_be_n(2) = '0' then
|
end if;
|
||||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
|
end if;
|
||||||
end if;
|
if rising_edge(sram_wr_n(2)) then
|
||||||
if sram_be_n(3) = '0' then
|
if sram_cs_n = '0' then
|
||||||
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
|
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(23 downto 16) <= sram_d(23 downto 16);
|
||||||
end if;
|
end if;
|
||||||
|
end if;
|
||||||
|
if rising_edge(sram_wr_n(3)) then
|
||||||
|
if sram_cs_n = '0' then
|
||||||
|
sram_data(to_integer(sram_a(SRAM_ADDR_WIDTH-1 downto 2)))(31 downto 24) <= sram_d(31 downto 24);
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
@@ -397,22 +386,9 @@ FLASH_READ:
|
|||||||
end loop;
|
end loop;
|
||||||
else
|
else
|
||||||
flash_d <= (others => 'Z') after 10 ns;
|
flash_d <= (others => 'Z') after 10 ns;
|
||||||
index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
|
if flash_oe_n = '0' and flash_cs_n = '0' then
|
||||||
if flash_oe_n = '0' then
|
index := to_integer(flash_a(FLASH_ADDR_WIDTH-1 downto 2));
|
||||||
if flash_cs_n = '0' then
|
flash_d <= flash_data(index) after 10 ns;
|
||||||
if flash_be_n(0) = '0' then
|
|
||||||
flash_d(7 downto 0) <= flash_data(index)(7 downto 0) after 10 ns;
|
|
||||||
end if;
|
|
||||||
if flash_be_n(1) = '0' then
|
|
||||||
flash_d(15 downto 8) <= flash_data(index)(15 downto 8) after 10 ns;
|
|
||||||
end if;
|
|
||||||
if flash_be_n(2) = '0' then
|
|
||||||
flash_d(23 downto 16) <= flash_data(index)(23 downto 16) after 10 ns;
|
|
||||||
end if;
|
|
||||||
if flash_be_n(3) = '0' then
|
|
||||||
flash_d(31 downto 24) <= flash_data(index)(31 downto 24) after 10 ns;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|||||||
@@ -269,8 +269,7 @@ int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pE
|
|||||||
char binstr_addr[33];
|
char binstr_addr[33];
|
||||||
char binstr_data[33];
|
char binstr_data[33];
|
||||||
|
|
||||||
char tpl[] =
|
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
|
||||||
{"# ---------------------------------------------------------------------\n# For Chipscope 10.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\nsource $env(CS_PATH)\\\\csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
|
|
||||||
|
|
||||||
pFileIn = fopen(pFilenameIn, "rb");
|
pFileIn = fopen(pFilenameIn, "rb");
|
||||||
if (!pFileIn)
|
if (!pFileIn)
|
||||||
|
|||||||
@@ -1,5 +1,5 @@
|
|||||||
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
||||||
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.5 2009-02-08 17:34:18 Jens Exp $
|
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.4 2009-01-18 21:44:57 Jens Exp $
|
||||||
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
|
||||||
library IEEE;
|
library IEEE;
|
||||||
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
@@ -32,9 +32,8 @@ entity async_port_wb is
|
|||||||
async_a : out unsigned(addr_width-1 downto 0);
|
async_a : out unsigned(addr_width-1 downto 0);
|
||||||
async_d : inout unsigned(data_width-1 downto 0);
|
async_d : inout unsigned(data_width-1 downto 0);
|
||||||
async_cs : out std_logic;
|
async_cs : out std_logic;
|
||||||
async_wr : out std_logic;
|
async_wr : out unsigned(byte_sel_width-1 downto 0);
|
||||||
async_rd : out std_logic;
|
async_rd : out std_logic;
|
||||||
async_be : out unsigned(byte_sel_width-1 downto 0);
|
|
||||||
async_rst : out std_logic
|
async_rst : out std_logic
|
||||||
);
|
);
|
||||||
end async_port_wb;
|
end async_port_wb;
|
||||||
@@ -210,8 +209,7 @@ architecture Behavioral of async_port_wb is
|
|||||||
begin
|
begin
|
||||||
if rising_edge(CLK_I) then
|
if rising_edge(CLK_I) then
|
||||||
async_cs <= (not async_timespec.pol_cs) xor as.cs;
|
async_cs <= (not async_timespec.pol_cs) xor as.cs;
|
||||||
async_be <= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and byte_en);
|
async_wr <= ((byte_sel_width-1 downto 0 => as.wr) and byte_en) xor (byte_sel_width-1 downto 0 => not async_timespec.pol_we);
|
||||||
async_wr <= (not async_timespec.pol_we) xor as.wr;
|
|
||||||
async_rd <= (not async_timespec.pol_oe) xor as.rd;
|
async_rd <= (not async_timespec.pol_oe) xor as.rd;
|
||||||
async_rst <= (not async_timespec.pol_rst) xor as.rst;
|
async_rst <= (not async_timespec.pol_rst) xor as.rst;
|
||||||
end if;
|
end if;
|
||||||
|
|||||||
@@ -37,7 +37,6 @@ package async_types is
|
|||||||
pol_cs : std_logic;
|
pol_cs : std_logic;
|
||||||
pol_oe : std_logic;
|
pol_oe : std_logic;
|
||||||
pol_we : std_logic;
|
pol_we : std_logic;
|
||||||
pol_be : std_logic;
|
|
||||||
pol_rst : std_logic;
|
pol_rst : std_logic;
|
||||||
end record;
|
end record;
|
||||||
|
|
||||||
|
|||||||
Reference in New Issue
Block a user