Compare commits
1
Commits
MIPS_PRE_R14
...
MIPS_R10
| Author | SHA1 | Date | |
|---|---|---|---|
 jens
|
9c165b1c71 |
@@ -1,48 +0,0 @@
|
||||
vhdl work "../../src/sdram_config.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
|
||||
vhdl work "../../../../lib/misc/utils_pkg.vhd"
|
||||
vhdl work "../../../../lib/misc/singleshot.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_rx.vhd"
|
||||
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_async_ctrl.vhd"
|
||||
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_out.vhd"
|
||||
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_in.vhd"
|
||||
vhdl work "../../src/ram_ld.vhd"
|
||||
vhdl work "../../src/bootloader.ROM_ld.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_rx.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
|
||||
vhdl work "../../../../lib/misc/async_types.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
|
||||
vhdl work "../../../../lib/ac97_ctrl/src/core/ac_io.vhd"
|
||||
vhdl work "../../src/async_defs.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_wb.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/rom_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/ram_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/lcd_port.vhd"
|
||||
vhdl work "../../../../lib/misc/gpio_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
|
||||
vhdl work "../../../../lib/misc/async_port_wb.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
|
||||
vhdl work "../../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
|
||||
vhdl work "../../src/mips_sys.vhd"
|
||||
@@ -1,48 +0,0 @@
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\singleshot.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
|
||||
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\async_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
|
||||
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_io.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\async_defs.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac97_wb.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
|
||||
@@ -1,503 +0,0 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
CONFIG STEPPING = "ES";
|
||||
|
||||
# Bus clock nets
|
||||
NET "clk" TNM_NET = "clk";
|
||||
TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
|
||||
|
||||
NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
|
||||
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
|
||||
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
|
||||
|
||||
NET "sys_clk_in" LOC = "AE14";
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET "sys_rst_n_in" LOC = "D6";
|
||||
NET sys_rst_n_in PULLUP;
|
||||
NET "sys_rst_n_in" TIG;
|
||||
NET "rst" TIG;
|
||||
|
||||
# Locate DCM/BUFG - Tools can probably figure them out automatically
|
||||
# but just LOC them down to be safe
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Misc Board Signals
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
NET sys_error<0> LOC = V6;
|
||||
NET sys_error<1> LOC = L24;
|
||||
NET sys_error<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_error<*> DRIVE = 2;
|
||||
NET sys_error<*> TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// RS-232
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_rx LOC = W2;
|
||||
NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET "sys_tx" LOC = "W1";
|
||||
NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET "sys_tx" TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Buttons, LEDs, and DIP Switches
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
# GPLED 0-3
|
||||
NET "sys_led<0>" LOC = "G5"; #GPLED0
|
||||
NET "sys_led<1>" LOC = "G6"; #GPLED1
|
||||
NET "sys_led<2>" LOC = "A11"; #GPLED2
|
||||
NET "sys_led<3>" LOC = "A12"; #GPLED3
|
||||
# North-East-South-West-Center LEDs
|
||||
NET "sys_led<4>" LOC = "F9"; # W LED
|
||||
NET "sys_led<5>" LOC = "E2"; # N LED
|
||||
NET "sys_led<6>" LOC = "E10"; # E LED
|
||||
NET "sys_led<7>" LOC = "A5"; # S LED
|
||||
NET "sys_led<8>" LOC = "C6"; # C LED
|
||||
NET "sys_led<*>" TIG;
|
||||
NET "sys_led<*>" SLEW = SLOW;
|
||||
NET "sys_led<*>" DRIVE = 2;
|
||||
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
|
||||
# North-East-South-West-Center Buttons
|
||||
NET "sys_btn<0>" LOC = "E9"; # W Button
|
||||
NET "sys_btn<1>" LOC = "E7"; # N Button
|
||||
NET "sys_btn<2>" LOC = "F10"; # E Button
|
||||
NET "sys_btn<3>" LOC = "A6"; # S Button
|
||||
NET "sys_btn<4>" LOC = "B6"; # C Button
|
||||
NET "sys_btn<*>" TIG;
|
||||
NET "sys_btn<*>" PULLDOWN;
|
||||
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
|
||||
# Dip Switches 1-8
|
||||
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
|
||||
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
|
||||
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
|
||||
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
|
||||
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
|
||||
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
|
||||
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
|
||||
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
|
||||
NET "sys_dip<*>" PULLDOWN;
|
||||
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
|
||||
NET "sys_dip<*>" TIG;
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// LCD
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_lcd_e LOC = AE13; # LCD_E
|
||||
NET sys_lcd_e IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_e SLEW = SLOW;
|
||||
NET sys_lcd_e DRIVE = 2;
|
||||
NET sys_lcd_e TIG;
|
||||
NET sys_lcd_rs LOC = AC17; # LCD_RS
|
||||
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rs SLEW = SLOW;
|
||||
NET sys_lcd_rs DRIVE = 2;
|
||||
NET sys_lcd_rs TIG;
|
||||
NET sys_lcd_rw LOC = AB17; # LCD_RW
|
||||
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rw SLEW = SLOW;
|
||||
NET sys_lcd_rw DRIVE = 2;
|
||||
NET sys_lcd_rw TIG;
|
||||
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
|
||||
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
|
||||
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
|
||||
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
|
||||
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_d<*> SLEW = SLOW;
|
||||
NET sys_lcd_d<*> DRIVE = 2;
|
||||
NET sys_lcd_d<*> PULLDOWN;
|
||||
NET sys_lcd_d<*> TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for DDR Controllers
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
|
||||
NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
|
||||
NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
|
||||
NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
|
||||
NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
|
||||
NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
|
||||
NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
|
||||
NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
|
||||
NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
|
||||
NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
|
||||
NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
|
||||
NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
|
||||
NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
|
||||
NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
|
||||
NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
|
||||
NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
|
||||
NET sys_sdr_cke_q LOC = G22; # DDR_CKE
|
||||
NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
|
||||
NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
|
||||
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
|
||||
|
||||
NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
|
||||
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
|
||||
|
||||
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
|
||||
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
|
||||
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
|
||||
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
|
||||
|
||||
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
|
||||
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
|
||||
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
|
||||
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
|
||||
|
||||
NET sys_sdr_data<0> LOC = H20; # DDR_D0
|
||||
NET sys_sdr_data<1> LOC = E23; # DDR_D1
|
||||
NET sys_sdr_data<2> LOC = H26; # DDR_D2
|
||||
NET sys_sdr_data<3> LOC = H22; # DDR_D3
|
||||
NET sys_sdr_data<4> LOC = E25; # DDR_D4
|
||||
NET sys_sdr_data<5> LOC = E26; # DDR_D5
|
||||
NET sys_sdr_data<6> LOC = F26; # DDR_D6
|
||||
NET sys_sdr_data<7> LOC = E24; # DDR_D7
|
||||
NET sys_sdr_data<8> LOC = E20; # DDR_D8
|
||||
NET sys_sdr_data<9> LOC = A22; # DDR_D9
|
||||
NET sys_sdr_data<10> LOC = C23; # DDR_D10
|
||||
NET sys_sdr_data<11> LOC = C24; # DDR_D11
|
||||
NET sys_sdr_data<12> LOC = A20; # DDR_D12
|
||||
NET sys_sdr_data<13> LOC = A21; # DDR_D13
|
||||
NET sys_sdr_data<14> LOC = D24; # DDR_D14
|
||||
NET sys_sdr_data<15> LOC = E18; # DDR_D15
|
||||
NET sys_sdr_data<16> LOC = F18; # DDR_D16
|
||||
NET sys_sdr_data<17> LOC = A19; # DDR_D17
|
||||
NET sys_sdr_data<18> LOC = F19; # DDR_D18
|
||||
NET sys_sdr_data<19> LOC = B23; # DDR_D19
|
||||
NET sys_sdr_data<20> LOC = E21; # DDR_D20
|
||||
NET sys_sdr_data<21> LOC = D22; # DDR_D21
|
||||
NET sys_sdr_data<22> LOC = D23; # DDR_D22
|
||||
NET sys_sdr_data<23> LOC = B24; # DDR_D23
|
||||
NET sys_sdr_data<24> LOC = E22; # DDR_D24
|
||||
NET sys_sdr_data<25> LOC = F20; # DDR_D25
|
||||
NET sys_sdr_data<26> LOC = H23; # DDR_D26
|
||||
NET sys_sdr_data<27> LOC = G25; # DDR_D27
|
||||
NET sys_sdr_data<28> LOC = G26; # DDR_D28
|
||||
NET sys_sdr_data<29> LOC = H25; # DDR_D29
|
||||
NET sys_sdr_data<30> LOC = H24; # DDR_D30
|
||||
NET sys_sdr_data<31> LOC = H21; # DDR_D31
|
||||
|
||||
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_a_q<*> FAST;
|
||||
|
||||
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ba_q<*> FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cke_q FAST;
|
||||
|
||||
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_p FAST;
|
||||
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
|
||||
NET sys_sdr_clk_fb IOBDELAY = NONE;
|
||||
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_n FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cs_qn FAST;
|
||||
|
||||
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ras_qn FAST;
|
||||
|
||||
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_we_qn FAST;
|
||||
|
||||
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dqs_q<*> FAST;
|
||||
|
||||
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dm_q<*> FAST;
|
||||
|
||||
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_data<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_data<*> FAST;
|
||||
|
||||
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
|
||||
|
||||
NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
|
||||
NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
|
||||
|
||||
# Timing Constraint for DDR Feedback Clock
|
||||
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
|
||||
|
||||
# USB
|
||||
NET sys_usb_a<0> LOC = Y10;
|
||||
NET sys_usb_a<1> LOC = AA10;
|
||||
NET sys_usb_a<*> IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_usb_d<0> LOC = AB7;
|
||||
NET sys_usb_d<1> LOC = AC9;
|
||||
NET sys_usb_d<2> LOC = AB9;
|
||||
NET sys_usb_d<3> LOC = AE6;
|
||||
NET sys_usb_d<4> LOC = AD6;
|
||||
NET sys_usb_d<5> LOC = AF9;
|
||||
NET sys_usb_d<6> LOC = AE9;
|
||||
NET sys_usb_d<7> LOC = AD8;
|
||||
NET sys_usb_d<8> LOC = AC8;
|
||||
NET sys_usb_d<9> LOC = AF4;
|
||||
NET sys_usb_d<10> LOC = AE4;
|
||||
NET sys_usb_d<11> LOC = AD3;
|
||||
NET sys_usb_d<12> LOC = AC3;
|
||||
NET sys_usb_d<13> LOC = AF6;
|
||||
NET sys_usb_d<14> LOC = AF5;
|
||||
NET sys_usb_d<15> LOC = AA7;
|
||||
NET sys_usb_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_d<*> SLEW = FAST;
|
||||
NET sys_usb_d<*> DRIVE = 8;
|
||||
NET sys_usb_d<*> PULLDOWN;
|
||||
|
||||
NET sys_usb_rdn LOC = AA8;
|
||||
NET sys_usb_rdn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_rdn SLEW = FAST;
|
||||
NET sys_usb_rdn DRIVE = 8;
|
||||
|
||||
NET sys_usb_wrn LOC = Y8;
|
||||
NET sys_usb_wrn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_wrn SLEW = FAST;
|
||||
NET sys_usb_wrn DRIVE = 8;
|
||||
|
||||
NET sys_usb_csn LOC = AF10;
|
||||
NET sys_usb_csn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_csn SLEW = FAST;
|
||||
NET sys_usb_csn DRIVE = 8;
|
||||
|
||||
NET sys_usb_rstn LOC = A7;
|
||||
NET sys_usb_rstn IOSTANDARD = LVCMOS25;
|
||||
NET sys_usb_rstn TIG;
|
||||
|
||||
NET sys_usb_int LOC = V5;
|
||||
NET sys_usb_int IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_int PULLDOWN;
|
||||
NET sys_usb_int TIG;
|
||||
|
||||
# FLASH
|
||||
NET sys_flash_ssram_a<24> LOC = T21;
|
||||
NET sys_flash_ssram_a<23> LOC = U20;
|
||||
NET sys_flash_ssram_a<22> LOC = T19;
|
||||
NET sys_flash_ssram_a<21> LOC = AC5;
|
||||
NET sys_flash_ssram_a<20> LOC = AB5;
|
||||
NET sys_flash_ssram_a<19> LOC = AC4;
|
||||
NET sys_flash_ssram_a<18> LOC = AB4;
|
||||
NET sys_flash_ssram_a<17> LOC = AB3;
|
||||
NET sys_flash_ssram_a<16> LOC = AA4;
|
||||
NET sys_flash_ssram_a<15> LOC = AA3;
|
||||
NET sys_flash_ssram_a<14> LOC = W5;
|
||||
NET sys_flash_ssram_a<13> LOC = W6;
|
||||
NET sys_flash_ssram_a<12> LOC = W3;
|
||||
NET sys_flash_ssram_a<11> LOC = AF3;
|
||||
NET sys_flash_ssram_a<10> LOC = AE3;
|
||||
NET sys_flash_ssram_a<9> LOC = AD2;
|
||||
NET sys_flash_ssram_a<8> LOC = AD1;
|
||||
NET sys_flash_ssram_a<7> LOC = AC2;
|
||||
NET sys_flash_ssram_a<6> LOC = AC1;
|
||||
NET sys_flash_ssram_a<5> LOC = AB2;
|
||||
NET sys_flash_ssram_a<4> LOC = AB1;
|
||||
NET sys_flash_ssram_a<3> LOC = AA1;
|
||||
NET sys_flash_ssram_a<2> LOC = Y2;
|
||||
NET sys_flash_ssram_a<1> LOC = Y1;
|
||||
NET sys_flash_ssram_a<0> LOC = T20;
|
||||
NET sys_flash_ssram_a<*> IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ssram_a<*> SLEW = FAST;
|
||||
NET sys_flash_ssram_a<*> DRIVE = 8;
|
||||
|
||||
|
||||
NET sys_flash_ssram_d<31> LOC = F14;
|
||||
NET sys_flash_ssram_d<30> LOC = F13;
|
||||
NET sys_flash_ssram_d<29> LOC = F12;
|
||||
NET sys_flash_ssram_d<28> LOC = F11;
|
||||
NET sys_flash_ssram_d<27> LOC = F16;
|
||||
NET sys_flash_ssram_d<26> LOC = F15;
|
||||
NET sys_flash_ssram_d<25> LOC = D14;
|
||||
NET sys_flash_ssram_d<24> LOC = D13;
|
||||
NET sys_flash_ssram_d<23> LOC = D15;
|
||||
NET sys_flash_ssram_d<22> LOC = E14;
|
||||
NET sys_flash_ssram_d<21> LOC = C11;
|
||||
NET sys_flash_ssram_d<20> LOC = D11;
|
||||
NET sys_flash_ssram_d<19> LOC = D16;
|
||||
NET sys_flash_ssram_d<18> LOC = C16;
|
||||
NET sys_flash_ssram_d<17> LOC = E13;
|
||||
NET sys_flash_ssram_d<16> LOC = D12;
|
||||
NET sys_flash_ssram_d<15> LOC = AA14;
|
||||
NET sys_flash_ssram_d<14> LOC = AB14;
|
||||
NET sys_flash_ssram_d<13> LOC = AC12;
|
||||
NET sys_flash_ssram_d<12> LOC = AC11;
|
||||
NET sys_flash_ssram_d<11> LOC = AA16;
|
||||
NET sys_flash_ssram_d<10> LOC = AA15;
|
||||
NET sys_flash_ssram_d<9> LOC = AB13;
|
||||
NET sys_flash_ssram_d<8> LOC = AA13;
|
||||
NET sys_flash_ssram_d<7> LOC = AC14;
|
||||
NET sys_flash_ssram_d<6> LOC = AD14;
|
||||
NET sys_flash_ssram_d<5> LOC = AA12;
|
||||
NET sys_flash_ssram_d<4> LOC = AA11;
|
||||
NET sys_flash_ssram_d<3> LOC = AC16;
|
||||
NET sys_flash_ssram_d<2> LOC = AC15;
|
||||
NET sys_flash_ssram_d<1> LOC = AC13;
|
||||
NET sys_flash_ssram_d<0> LOC = AD13;
|
||||
NET sys_flash_ssram_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_ssram_d<*> DRIVE = 12;
|
||||
NET sys_flash_ssram_d<*> SLEW = FAST;
|
||||
NET sys_flash_ssram_d<*> PULLDOWN;
|
||||
|
||||
NET sys_flash_ssram_oe_n LOC = AC6;
|
||||
NET sys_flash_ssram_oe_n IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ssram_oe_n SLEW = FAST;
|
||||
NET sys_flash_ssram_oe_n DRIVE = 8;
|
||||
|
||||
NET sys_flash_ssram_we_n LOC = AB6;
|
||||
NET sys_flash_ssram_we_n IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ssram_we_n SLEW = FAST;
|
||||
NET sys_flash_ssram_we_n DRIVE = 8;
|
||||
|
||||
NET sys_flash_ce LOC = W7;
|
||||
NET sys_flash_ce IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ce SLEW = FAST;
|
||||
NET sys_flash_ce DRIVE = 8;
|
||||
|
||||
NET sys_flash_rstn LOC = AD10;
|
||||
NET sys_flash_rstn IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_rstn DRIVE = 8;
|
||||
NET sys_flash_rstn SLEW = FAST;
|
||||
NET sys_flash_rstn TIG;
|
||||
|
||||
NET sys_flash_byten LOC = N22;
|
||||
NET sys_flash_byten IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_byten DRIVE = 8;
|
||||
NET sys_flash_byten SLEW = FAST;
|
||||
NET sys_flash_byten TIG;
|
||||
|
||||
# SSRAM
|
||||
NET sys_ssram_clk LOC = AF7;
|
||||
NET sys_ssram_clk IOSTANDARD = LVCMOS33;
|
||||
NET sys_ssram_clk DRIVE = 16;
|
||||
NET sys_ssram_clk SLEW = FAST;
|
||||
|
||||
NET "sys_ssram_clk" TNM_NET = "ssram_clk";
|
||||
#TIMESPEC "TS_ssram_clk" = PERIOD "ssram_clk" 9.95 ns HIGH 50 %;
|
||||
|
||||
|
||||
NET sys_ssram_clk_fb LOC = AD17;
|
||||
NET sys_ssram_clk_fb IOSTANDARD = LVCMOS33;
|
||||
|
||||
# Timing Constraint for Feedback Clock
|
||||
NET sys_ssram_clk_fb FEEDBACK = 1 ns NET sys_ssram_clk;
|
||||
|
||||
NET sys_ssram_ce_n LOC = V7;
|
||||
NET sys_ssram_ce_n IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_ce_n SLEW = FAST;
|
||||
NET sys_ssram_ce_n DRIVE = 8;
|
||||
|
||||
NET sys_ssram_bw_n<3> LOC = Y3; #Y4;
|
||||
NET sys_ssram_bw_n<2> LOC = Y4; #Y3;
|
||||
NET sys_ssram_bw_n<1> LOC = Y5; #Y6;
|
||||
NET sys_ssram_bw_n<0> LOC = Y6; #Y5;
|
||||
NET sys_ssram_bw_n<*> IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_bw_n<*> SLEW = FAST;
|
||||
NET sys_ssram_bw_n<*> DRIVE = 8;
|
||||
|
||||
NET sys_ssram_adv LOC = W4;
|
||||
NET sys_ssram_adv IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_adv SLEW = FAST;
|
||||
NET sys_ssram_adv DRIVE = 8;
|
||||
|
||||
NET sys_ssram_mode LOC = V26;
|
||||
NET sys_ssram_mode IOSTANDARD = LVDCI_33;
|
||||
NET sys_ssram_mode SLEW = FAST;
|
||||
NET sys_ssram_mode DRIVE = 8;
|
||||
|
||||
|
||||
# VGA
|
||||
NET sys_vga_blue<0> LOC = M21; # VGA_B0
|
||||
NET sys_vga_blue<1> LOC = M26; # VGA_B1
|
||||
NET sys_vga_blue<2> LOC = L26; # VGA_B2
|
||||
NET sys_vga_blue<3> LOC = C5; # VGA_B3
|
||||
NET sys_vga_blue<4> LOC = C7; # VGA_B4
|
||||
NET sys_vga_blue<5> LOC = B7; # VGA_B5
|
||||
NET sys_vga_blue<6> LOC = G8; # VGA_B6
|
||||
NET sys_vga_blue<7> LOC = F8; # VGA_B7
|
||||
NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<*> SLEW = FAST;
|
||||
NET sys_vga_blue<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_clk LOC = AF8;
|
||||
NET sys_vga_clk IOSTANDARD = LVDCI_33;
|
||||
NET sys_vga_clk SLEW = FAST;
|
||||
NET sys_vga_clk DRIVE = 8;
|
||||
|
||||
NET sys_vga_green<0> LOC = M22; # VGA_G0
|
||||
NET sys_vga_green<1> LOC = M23; # VGA_G1
|
||||
NET sys_vga_green<2> LOC = M20; # VGA_G2
|
||||
NET sys_vga_green<3> LOC = E4; # VGA_G3
|
||||
NET sys_vga_green<4> LOC = D3; # VGA_G4
|
||||
NET sys_vga_green<5> LOC = H7; # VGA_G5
|
||||
NET sys_vga_green<6> LOC = H8; # VGA_G6
|
||||
NET sys_vga_green<7> LOC = C1; # VGA_G7
|
||||
NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<*> SLEW = FAST;
|
||||
NET sys_vga_green<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_hsync LOC = C10;
|
||||
NET sys_vga_hsync SLEW = FAST;
|
||||
NET sys_vga_hsync DRIVE = 8;
|
||||
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_red<0> LOC = N23; #VGA_R0
|
||||
NET sys_vga_red<1> LOC = N24; #VGA_R1
|
||||
NET sys_vga_red<2> LOC = N25; #VGA_R2
|
||||
NET sys_vga_red<3> LOC = C2; #VGA_R3
|
||||
NET sys_vga_red<4> LOC = G7; #VGA_R4
|
||||
NET sys_vga_red<5> LOC = F7; #VGA_R5
|
||||
NET sys_vga_red<6> LOC = E5; #VGA_R6
|
||||
NET sys_vga_red<7> LOC = E6; #VGA_R7
|
||||
NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<*> SLEW = FAST;
|
||||
NET sys_vga_red<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_vsync LOC = A8;
|
||||
NET sys_vga_vsync SLEW = FAST;
|
||||
NET sys_vga_vsync DRIVE = 8;
|
||||
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_blank_n LOC = M24;
|
||||
NET sys_vga_blank_n SLEW = FAST;
|
||||
NET sys_vga_blank_n DRIVE = 8;
|
||||
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_sync_n LOC = L23;
|
||||
NET sys_vga_sync_n SLEW = FAST;
|
||||
NET sys_vga_sync_n DRIVE = 8;
|
||||
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
|
||||
@@ -1,500 +0,0 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
CONFIG STEPPING = "ES";
|
||||
|
||||
# Bus clock nets
|
||||
NET "clk" TNM_NET = "clk";
|
||||
TIMESPEC "TS_clk" = PERIOD "clk" 9.9 ns HIGH 50 %;
|
||||
|
||||
NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
|
||||
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
|
||||
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
|
||||
|
||||
NET "sys_clk_in" LOC = "AE14";
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET "sys_rst_n_in" LOC = "D6";
|
||||
NET sys_rst_n_in PULLUP;
|
||||
NET "sys_rst_n_in" TIG;
|
||||
NET "rst" TIG;
|
||||
|
||||
NET "sys_clk_in" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
PIN "inst_clockgen/inst_DCM_BASE_0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
NET "sys_sdr_clk_fb" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
PIN "inst_clockgen/inst_DCM_BASE_0.CLKFB" CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
|
||||
# Locate DCM/BUFG - Tools can probably figure them out automatically
|
||||
# but just LOC them down to be safe
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
|
||||
|
||||
INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
|
||||
# GOOD 1
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
|
||||
|
||||
# GOOD 2 (smaller)
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y69:SLICE_X39Y0 ;
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y8, RAMB16_X1Y0:RAMB16_X1Y8, RAMB16_X2Y0:RAMB16_X2Y8, RAMB16_X3Y0:RAMB16_X3Y8 ;
|
||||
|
||||
# GOOD 3 (even smaller)
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y61:SLICE_X39Y0 ;
|
||||
#AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y7, RAMB16_X1Y0:RAMB16_X1Y7, RAMB16_X2Y0:RAMB16_X2Y7, RAMB16_X3Y0:RAMB16_X3Y7 ;
|
||||
|
||||
# GOOD 4 (even more smaller)
|
||||
AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y53:SLICE_X39Y0 ;
|
||||
AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y6, RAMB16_X1Y0:RAMB16_X1Y6, RAMB16_X2Y0:RAMB16_X2Y6, RAMB16_X3Y0:RAMB16_X3Y6 ;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Misc Board Signals
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
NET sys_error<0> LOC = V6;
|
||||
NET sys_error<1> LOC = L24;
|
||||
NET sys_error<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_error<*> DRIVE = 2;
|
||||
NET sys_error<*> TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// RS-232
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_rx LOC = W2;
|
||||
NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET "sys_tx" LOC = "W1";
|
||||
NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET "sys_tx" TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Buttons, LEDs, and DIP Switches
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
# GPLED 0-3
|
||||
NET "sys_led<0>" LOC = "G5"; #GPLED0
|
||||
NET "sys_led<1>" LOC = "G6"; #GPLED1
|
||||
NET "sys_led<2>" LOC = "A11"; #GPLED2
|
||||
NET "sys_led<3>" LOC = "A12"; #GPLED3
|
||||
# North-East-South-West-Center LEDs
|
||||
NET "sys_led<4>" LOC = "F9"; # W LED
|
||||
NET "sys_led<5>" LOC = "E2"; # N LED
|
||||
NET "sys_led<6>" LOC = "E10"; # E LED
|
||||
NET "sys_led<7>" LOC = "A5"; # S LED
|
||||
NET "sys_led<8>" LOC = "C6"; # C LED
|
||||
NET "sys_led<*>" TIG;
|
||||
NET "sys_led<*>" SLEW = SLOW;
|
||||
NET "sys_led<*>" DRIVE = 2;
|
||||
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
|
||||
# North-East-South-West-Center Buttons
|
||||
NET "sys_btn<0>" LOC = "E9"; # W Button
|
||||
NET "sys_btn<1>" LOC = "E7"; # N Button
|
||||
NET "sys_btn<2>" LOC = "F10"; # E Button
|
||||
NET "sys_btn<3>" LOC = "A6"; # S Button
|
||||
NET "sys_btn<4>" LOC = "B6"; # C Button
|
||||
NET "sys_btn<*>" TIG;
|
||||
NET "sys_btn<*>" PULLDOWN;
|
||||
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
|
||||
# Dip Switches 1-8
|
||||
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
|
||||
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
|
||||
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
|
||||
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
|
||||
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
|
||||
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
|
||||
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
|
||||
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
|
||||
NET "sys_dip<*>" PULLDOWN;
|
||||
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
|
||||
NET "sys_dip<*>" TIG;
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// LCD
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_lcd_e LOC = AE13; # LCD_E
|
||||
NET sys_lcd_e IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_e SLEW = SLOW;
|
||||
NET sys_lcd_e DRIVE = 2;
|
||||
NET sys_lcd_e TIG;
|
||||
NET sys_lcd_rs LOC = AC17; # LCD_RS
|
||||
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rs SLEW = SLOW;
|
||||
NET sys_lcd_rs DRIVE = 2;
|
||||
NET sys_lcd_rs TIG;
|
||||
NET sys_lcd_rw LOC = AB17; # LCD_RW
|
||||
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rw SLEW = SLOW;
|
||||
NET sys_lcd_rw DRIVE = 2;
|
||||
NET sys_lcd_rw TIG;
|
||||
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
|
||||
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
|
||||
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
|
||||
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
|
||||
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_d<*> SLEW = SLOW;
|
||||
NET sys_lcd_d<*> DRIVE = 2;
|
||||
NET sys_lcd_d<*> PULLDOWN;
|
||||
NET sys_lcd_d<*> TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for DDR Controllers
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
|
||||
NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
|
||||
NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
|
||||
NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
|
||||
NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
|
||||
NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
|
||||
NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
|
||||
NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
|
||||
NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
|
||||
NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
|
||||
NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
|
||||
NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
|
||||
NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
|
||||
NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
|
||||
NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
|
||||
NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
|
||||
NET sys_sdr_cke_q LOC = G22; # DDR_CKE
|
||||
NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
|
||||
NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
|
||||
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
|
||||
|
||||
NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
|
||||
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
|
||||
|
||||
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
|
||||
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
|
||||
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
|
||||
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
|
||||
|
||||
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
|
||||
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
|
||||
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
|
||||
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
|
||||
|
||||
NET sys_sdr_data<0> LOC = H20; # DDR_D0
|
||||
NET sys_sdr_data<1> LOC = E23; # DDR_D1
|
||||
NET sys_sdr_data<2> LOC = H26; # DDR_D2
|
||||
NET sys_sdr_data<3> LOC = H22; # DDR_D3
|
||||
NET sys_sdr_data<4> LOC = E25; # DDR_D4
|
||||
NET sys_sdr_data<5> LOC = E26; # DDR_D5
|
||||
NET sys_sdr_data<6> LOC = F26; # DDR_D6
|
||||
NET sys_sdr_data<7> LOC = E24; # DDR_D7
|
||||
NET sys_sdr_data<8> LOC = E20; # DDR_D8
|
||||
NET sys_sdr_data<9> LOC = A22; # DDR_D9
|
||||
NET sys_sdr_data<10> LOC = C23; # DDR_D10
|
||||
NET sys_sdr_data<11> LOC = C24; # DDR_D11
|
||||
NET sys_sdr_data<12> LOC = A20; # DDR_D12
|
||||
NET sys_sdr_data<13> LOC = A21; # DDR_D13
|
||||
NET sys_sdr_data<14> LOC = D24; # DDR_D14
|
||||
NET sys_sdr_data<15> LOC = E18; # DDR_D15
|
||||
NET sys_sdr_data<16> LOC = F18; # DDR_D16
|
||||
NET sys_sdr_data<17> LOC = A19; # DDR_D17
|
||||
NET sys_sdr_data<18> LOC = F19; # DDR_D18
|
||||
NET sys_sdr_data<19> LOC = B23; # DDR_D19
|
||||
NET sys_sdr_data<20> LOC = E21; # DDR_D20
|
||||
NET sys_sdr_data<21> LOC = D22; # DDR_D21
|
||||
NET sys_sdr_data<22> LOC = D23; # DDR_D22
|
||||
NET sys_sdr_data<23> LOC = B24; # DDR_D23
|
||||
NET sys_sdr_data<24> LOC = E22; # DDR_D24
|
||||
NET sys_sdr_data<25> LOC = F20; # DDR_D25
|
||||
NET sys_sdr_data<26> LOC = H23; # DDR_D26
|
||||
NET sys_sdr_data<27> LOC = G25; # DDR_D27
|
||||
NET sys_sdr_data<28> LOC = G26; # DDR_D28
|
||||
NET sys_sdr_data<29> LOC = H25; # DDR_D29
|
||||
NET sys_sdr_data<30> LOC = H24; # DDR_D30
|
||||
NET sys_sdr_data<31> LOC = H21; # DDR_D31
|
||||
|
||||
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_a_q<*> FAST;
|
||||
|
||||
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ba_q<*> FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cke_q FAST;
|
||||
|
||||
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_p FAST;
|
||||
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
|
||||
NET sys_sdr_clk_fb IOBDELAY = NONE;
|
||||
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_n FAST;
|
||||
|
||||
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cs_qn FAST;
|
||||
|
||||
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ras_qn FAST;
|
||||
|
||||
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_we_qn FAST;
|
||||
|
||||
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dqs_q<*> FAST;
|
||||
|
||||
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dm_q<*> FAST;
|
||||
|
||||
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_data<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_data<*> FAST;
|
||||
|
||||
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
|
||||
|
||||
NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
|
||||
NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
|
||||
|
||||
# Timing Constraint for DDR Feedback Clock
|
||||
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
|
||||
|
||||
# USB
|
||||
NET sys_usb_a<0> LOC = Y10;
|
||||
NET sys_usb_a<1> LOC = AA10;
|
||||
NET sys_usb_a<*> IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_usb_d<0> LOC = AB7;
|
||||
NET sys_usb_d<1> LOC = AC9;
|
||||
NET sys_usb_d<2> LOC = AB9;
|
||||
NET sys_usb_d<3> LOC = AE6;
|
||||
NET sys_usb_d<4> LOC = AD6;
|
||||
NET sys_usb_d<5> LOC = AF9;
|
||||
NET sys_usb_d<6> LOC = AE9;
|
||||
NET sys_usb_d<7> LOC = AD8;
|
||||
NET sys_usb_d<8> LOC = AC8;
|
||||
NET sys_usb_d<9> LOC = AF4;
|
||||
NET sys_usb_d<10> LOC = AE4;
|
||||
NET sys_usb_d<11> LOC = AD3;
|
||||
NET sys_usb_d<12> LOC = AC3;
|
||||
NET sys_usb_d<13> LOC = AF6;
|
||||
NET sys_usb_d<14> LOC = AF5;
|
||||
NET sys_usb_d<15> LOC = AA7;
|
||||
NET sys_usb_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_d<*> SLEW = FAST;
|
||||
NET sys_usb_d<*> DRIVE = 8;
|
||||
NET sys_usb_d<*> PULLDOWN;
|
||||
|
||||
NET sys_usb_rdn LOC = AA8;
|
||||
NET sys_usb_rdn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_rdn SLEW = FAST;
|
||||
NET sys_usb_rdn DRIVE = 8;
|
||||
|
||||
NET sys_usb_wrn LOC = Y8;
|
||||
NET sys_usb_wrn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_wrn SLEW = FAST;
|
||||
NET sys_usb_wrn DRIVE = 8;
|
||||
|
||||
NET sys_usb_csn LOC = AF10;
|
||||
NET sys_usb_csn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_csn SLEW = FAST;
|
||||
NET sys_usb_csn DRIVE = 8;
|
||||
|
||||
NET sys_usb_rstn LOC = A7;
|
||||
NET sys_usb_rstn IOSTANDARD = LVCMOS25;
|
||||
NET sys_usb_rstn TIG;
|
||||
|
||||
NET sys_usb_int LOC = V5;
|
||||
NET sys_usb_int IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_int PULLDOWN;
|
||||
NET sys_usb_int TIG;
|
||||
|
||||
# FLASH
|
||||
NET sys_flash_a<24> LOC = T21;
|
||||
NET sys_flash_a<23> LOC = U20;
|
||||
NET sys_flash_a<22> LOC = T19;
|
||||
NET sys_flash_a<21> LOC = AC5;
|
||||
NET sys_flash_a<20> LOC = AB5;
|
||||
NET sys_flash_a<19> LOC = AC4;
|
||||
NET sys_flash_a<18> LOC = AB4;
|
||||
NET sys_flash_a<17> LOC = AB3;
|
||||
NET sys_flash_a<16> LOC = AA4;
|
||||
NET sys_flash_a<15> LOC = AA3;
|
||||
NET sys_flash_a<14> LOC = W5;
|
||||
NET sys_flash_a<13> LOC = W6;
|
||||
NET sys_flash_a<12> LOC = W3;
|
||||
NET sys_flash_a<11> LOC = AF3;
|
||||
NET sys_flash_a<10> LOC = AE3;
|
||||
NET sys_flash_a<9> LOC = AD2;
|
||||
NET sys_flash_a<8> LOC = AD1;
|
||||
NET sys_flash_a<7> LOC = AC2;
|
||||
NET sys_flash_a<6> LOC = AC1;
|
||||
NET sys_flash_a<5> LOC = AB2;
|
||||
NET sys_flash_a<4> LOC = AB1;
|
||||
NET sys_flash_a<3> LOC = AA1;
|
||||
NET sys_flash_a<2> LOC = Y2;
|
||||
NET sys_flash_a<1> LOC = Y1;
|
||||
NET sys_flash_a<0> LOC = T20;
|
||||
|
||||
NET sys_flash_d<31> LOC = F14;
|
||||
NET sys_flash_d<30> LOC = F13;
|
||||
NET sys_flash_d<29> LOC = F12;
|
||||
NET sys_flash_d<28> LOC = F11;
|
||||
NET sys_flash_d<27> LOC = F16;
|
||||
NET sys_flash_d<26> LOC = F15;
|
||||
NET sys_flash_d<25> LOC = D14;
|
||||
NET sys_flash_d<24> LOC = D13;
|
||||
NET sys_flash_d<23> LOC = D15;
|
||||
NET sys_flash_d<22> LOC = E14;
|
||||
NET sys_flash_d<21> LOC = C11;
|
||||
NET sys_flash_d<20> LOC = D11;
|
||||
NET sys_flash_d<19> LOC = D16;
|
||||
NET sys_flash_d<18> LOC = C16;
|
||||
NET sys_flash_d<17> LOC = E13;
|
||||
NET sys_flash_d<16> LOC = D12;
|
||||
NET sys_flash_d<15> LOC = AA14;
|
||||
NET sys_flash_d<14> LOC = AB14;
|
||||
NET sys_flash_d<13> LOC = AC12;
|
||||
NET sys_flash_d<12> LOC = AC11;
|
||||
NET sys_flash_d<11> LOC = AA16;
|
||||
NET sys_flash_d<10> LOC = AA15;
|
||||
NET sys_flash_d<9> LOC = AB13;
|
||||
NET sys_flash_d<8> LOC = AA13;
|
||||
NET sys_flash_d<7> LOC = AC14;
|
||||
NET sys_flash_d<6> LOC = AD14;
|
||||
NET sys_flash_d<5> LOC = AA12;
|
||||
NET sys_flash_d<4> LOC = AA11;
|
||||
NET sys_flash_d<3> LOC = AC16;
|
||||
NET sys_flash_d<2> LOC = AC15;
|
||||
NET sys_flash_d<1> LOC = AC13;
|
||||
NET sys_flash_d<0> LOC = AD13;
|
||||
NET sys_flash_rdn LOC = AC6;
|
||||
NET sys_flash_wrn LOC = AB6;
|
||||
NET sys_flash_ce LOC = W7;
|
||||
NET sys_flash_ac97_rstn LOC = AD10;
|
||||
NET sys_flash_byten LOC = N22;
|
||||
|
||||
NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_a<*> SLEW = FAST;
|
||||
NET sys_flash_a<*> DRIVE = 8;
|
||||
|
||||
NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_d<*> DRIVE = 12;
|
||||
NET sys_flash_d<*> SLEW = FAST;
|
||||
NET sys_flash_d<*> PULLDOWN;
|
||||
|
||||
NET sys_flash_rdn IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_rdn SLEW = FAST;
|
||||
NET sys_flash_rdn DRIVE = 8;
|
||||
|
||||
NET sys_flash_wrn IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_wrn SLEW = FAST;
|
||||
NET sys_flash_wrn DRIVE = 8;
|
||||
|
||||
NET sys_flash_ce IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ce SLEW = FAST;
|
||||
NET sys_flash_ce DRIVE = 8;
|
||||
|
||||
NET sys_flash_ac97_rstn IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_ac97_rstn DRIVE = 8;
|
||||
NET sys_flash_ac97_rstn SLEW = FAST;
|
||||
NET sys_flash_ac97_rstn TIG;
|
||||
|
||||
NET sys_flash_byten IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_byten DRIVE = 8;
|
||||
NET sys_flash_byten SLEW = FAST;
|
||||
NET sys_flash_byten TIG;
|
||||
|
||||
# VGA
|
||||
NET sys_vga_blue<0> LOC = M21; # VGA_B0
|
||||
NET sys_vga_blue<1> LOC = M26; # VGA_B1
|
||||
NET sys_vga_blue<2> LOC = L26; # VGA_B2
|
||||
NET sys_vga_blue<3> LOC = C5; # VGA_B3
|
||||
NET sys_vga_blue<4> LOC = C7; # VGA_B4
|
||||
NET sys_vga_blue<5> LOC = B7; # VGA_B5
|
||||
NET sys_vga_blue<6> LOC = G8; # VGA_B6
|
||||
NET sys_vga_blue<7> LOC = F8; # VGA_B7
|
||||
NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<*> SLEW = FAST;
|
||||
NET sys_vga_blue<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_clk LOC = AF8;
|
||||
NET sys_vga_clk IOSTANDARD = LVDCI_33;
|
||||
NET sys_vga_clk SLEW = FAST;
|
||||
NET sys_vga_clk DRIVE = 8;
|
||||
|
||||
NET sys_vga_green<0> LOC = M22; # VGA_G0
|
||||
NET sys_vga_green<1> LOC = M23; # VGA_G1
|
||||
NET sys_vga_green<2> LOC = M20; # VGA_G2
|
||||
NET sys_vga_green<3> LOC = E4; # VGA_G3
|
||||
NET sys_vga_green<4> LOC = D3; # VGA_G4
|
||||
NET sys_vga_green<5> LOC = H7; # VGA_G5
|
||||
NET sys_vga_green<6> LOC = H8; # VGA_G6
|
||||
NET sys_vga_green<7> LOC = C1; # VGA_G7
|
||||
NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<*> SLEW = FAST;
|
||||
NET sys_vga_green<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_hsync LOC = C10;
|
||||
NET sys_vga_hsync SLEW = FAST;
|
||||
NET sys_vga_hsync DRIVE = 8;
|
||||
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_red<0> LOC = N23; #VGA_R0
|
||||
NET sys_vga_red<1> LOC = N24; #VGA_R1
|
||||
NET sys_vga_red<2> LOC = N25; #VGA_R2
|
||||
NET sys_vga_red<3> LOC = C2; #VGA_R3
|
||||
NET sys_vga_red<4> LOC = G7; #VGA_R4
|
||||
NET sys_vga_red<5> LOC = F7; #VGA_R5
|
||||
NET sys_vga_red<6> LOC = E5; #VGA_R6
|
||||
NET sys_vga_red<7> LOC = E6; #VGA_R7
|
||||
NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<*> SLEW = FAST;
|
||||
NET sys_vga_red<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_vsync LOC = A8;
|
||||
NET sys_vga_vsync SLEW = FAST;
|
||||
NET sys_vga_vsync DRIVE = 8;
|
||||
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_blank_n LOC = M24;
|
||||
NET sys_vga_blank_n SLEW = FAST;
|
||||
NET sys_vga_blank_n DRIVE = 8;
|
||||
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_sync_n LOC = L23;
|
||||
NET sys_vga_sync_n SLEW = FAST;
|
||||
NET sys_vga_sync_n DRIVE = 8;
|
||||
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for AC97 Sound Controller
|
||||
#------------------------------------------------------------------------------
|
||||
NET "sys_ac97_bit_clk" TNM_NET = "ac97_clk";
|
||||
TIMESPEC "TSACBITCLK" = PERIOD "ac97_clk" 80 ns HIGH 50 %;
|
||||
|
||||
NET sys_ac97_bit_clk LOC = AE10;
|
||||
NET sys_ac97_bit_clk IOSTANDARD = LVCMOS33;
|
||||
NET sys_ac97_bit_clk PERIOD = 80;
|
||||
NET sys_ac97_sdata_in LOC = AD16;
|
||||
NET sys_ac97_sdata_in IOSTANDARD = LVCMOS33;
|
||||
NET sys_ac97_sdata_out LOC = C8;
|
||||
NET sys_ac97_sdata_out SLEW = FAST;
|
||||
NET sys_ac97_ssync LOC = D9;
|
||||
NET sys_ac97_ssync SLEW = FAST;
|
||||
@@ -1,43 +0,0 @@
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vhdl work "../../src/sdram_config.vhd"
|
||||
vhdl work "../../../../lib/misc/utils_pkg.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/kcuart_rx.vhd"
|
||||
vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
|
||||
vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
|
||||
vhdl work "../../src/sys_types.vhd"
|
||||
vhdl work "../../src/ram_ld.vhd"
|
||||
vhdl work "../../src/bootloader.ROM_ld.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_tx.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_rx.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
|
||||
vhdl work "../../../../lib/FIFO/src/fifo_async.vhd"
|
||||
vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
|
||||
vhdl work "../../../../lib/uart/uart_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/rom_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/ram_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/lcd_port.vhd"
|
||||
vhdl work "../../../../lib/misc/gpio_wb.vhd"
|
||||
vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
|
||||
vhdl work "../../../../lib/misc/async_port_wb.vhd"
|
||||
vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
|
||||
vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
|
||||
vhdl work "../../src/mips_sys.vhd"
|
||||
@@ -1,43 +0,0 @@
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
|
||||
vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
|
||||
vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
|
||||
vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
|
||||
vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
|
||||
vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
|
||||
vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
|
||||
vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
|
||||
@@ -1,469 +0,0 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
CONFIG STEPPING = "ES";
|
||||
|
||||
# Bus clock nets
|
||||
NET "clk" TNM_NET = "clk";
|
||||
TIMESPEC "TS_clk" = PERIOD "clk" 9.95 ns HIGH 50 %;
|
||||
|
||||
NET "inst_vga_frontend/inst_vga_backend/inst_clkgen/vga_clk0" TNM_NET = "vga_clk";
|
||||
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
|
||||
TIMESPEC TS_unrelate = FROM clk TO vga_clk TIG;
|
||||
|
||||
NET "sys_clk_in" LOC = "AE14";
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET "sys_rst_n_in" LOC = "D6";
|
||||
NET sys_rst_n_in PULLUP;
|
||||
NET "sys_rst_n_in" TIG;
|
||||
NET "rst" TIG;
|
||||
|
||||
# Locate DCM/BUFG - Tools can probably figure them out automatically
|
||||
# but just LOC them down to be safe
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_0 LOC = DCM_ADV_X0Y2;
|
||||
#INST inst_ddr_sdr/ctrl.inst_DCM_BASE_1 LOC = DCM_ADV_X0Y1;
|
||||
|
||||
# GOOD
|
||||
INST "inst_mips_top" AREA_GROUP = "AG_inst_mips_top" ;
|
||||
AREA_GROUP "AG_inst_mips_top" RANGE = SLICE_X0Y85:SLICE_X39Y0 ;
|
||||
AREA_GROUP "AG_inst_mips_top" RANGE = RAMB16_X0Y0:RAMB16_X0Y10, RAMB16_X1Y0:RAMB16_X1Y10, RAMB16_X2Y0:RAMB16_X2Y10, RAMB16_X3Y0:RAMB16_X3Y10 ;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Misc Board Signals
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
NET sys_error<0> LOC = V6;
|
||||
NET sys_error<1> LOC = L24;
|
||||
NET sys_error<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_error<*> DRIVE = 2;
|
||||
NET sys_error<*> TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// RS-232
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_rx LOC = W2;
|
||||
NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET "sys_tx" LOC = "W1";
|
||||
NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET "sys_tx" TIG;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// Buttons, LEDs, and DIP Switches
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
# GPLED 0-3
|
||||
NET "sys_led<0>" LOC = "G5"; #GPLED0
|
||||
NET "sys_led<1>" LOC = "G6"; #GPLED1
|
||||
NET "sys_led<2>" LOC = "A11"; #GPLED2
|
||||
NET "sys_led<3>" LOC = "A12"; #GPLED3
|
||||
# North-East-South-West-Center LEDs
|
||||
NET "sys_led<4>" LOC = "F9"; # W LED
|
||||
NET "sys_led<5>" LOC = "E2"; # N LED
|
||||
NET "sys_led<6>" LOC = "E10"; # E LED
|
||||
NET "sys_led<7>" LOC = "A5"; # S LED
|
||||
NET "sys_led<8>" LOC = "C6"; # C LED
|
||||
NET "sys_led<*>" TIG;
|
||||
NET "sys_led<*>" SLEW = SLOW;
|
||||
NET "sys_led<*>" DRIVE = 2;
|
||||
#NET "sys_led<*>" IOSTANDARD = LVCMOS33;
|
||||
# North-East-South-West-Center Buttons
|
||||
NET "sys_btn<0>" LOC = "E9"; # W Button
|
||||
NET "sys_btn<1>" LOC = "E7"; # N Button
|
||||
NET "sys_btn<2>" LOC = "F10"; # E Button
|
||||
NET "sys_btn<3>" LOC = "A6"; # S Button
|
||||
NET "sys_btn<4>" LOC = "B6"; # C Button
|
||||
NET "sys_btn<*>" TIG;
|
||||
NET "sys_btn<*>" PULLDOWN;
|
||||
#NET "sys_btn<*>" IOSTANDARD = LVCMOS33;
|
||||
# Dip Switches 1-8
|
||||
NET "sys_dip<7>" LOC = "U24"; # DIP SW 8
|
||||
NET "sys_dip<6>" LOC = "U25"; # DIP SW 7
|
||||
NET "sys_dip<5>" LOC = "V23"; # DIP SW 6
|
||||
NET "sys_dip<4>" LOC = "U23"; # DIP SW 5
|
||||
NET "sys_dip<3>" LOC = "U26"; # DIP SW 4
|
||||
NET "sys_dip<2>" LOC = "T26"; # DIP SW 3
|
||||
NET "sys_dip<1>" LOC = "R19"; # DIP SW 2
|
||||
NET "sys_dip<0>" LOC = "R20"; # DIP SW 1
|
||||
NET "sys_dip<*>" PULLDOWN;
|
||||
NET "sys_dip<*>" IOSTANDARD = LVCMOS33;
|
||||
NET "sys_dip<*>" TIG;
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
// LCD
|
||||
////////////////////////////////////////////////////////////////////////////
|
||||
NET sys_lcd_e LOC = AE13; # LCD_E
|
||||
NET sys_lcd_e IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_e SLEW = SLOW;
|
||||
NET sys_lcd_e DRIVE = 2;
|
||||
NET sys_lcd_e TIG;
|
||||
NET sys_lcd_rs LOC = AC17; # LCD_RS
|
||||
NET sys_lcd_rs IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rs SLEW = SLOW;
|
||||
NET sys_lcd_rs DRIVE = 2;
|
||||
NET sys_lcd_rs TIG;
|
||||
NET sys_lcd_rw LOC = AB17; # LCD_RW
|
||||
NET sys_lcd_rw IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_rw SLEW = SLOW;
|
||||
NET sys_lcd_rw DRIVE = 2;
|
||||
NET sys_lcd_rw TIG;
|
||||
NET sys_lcd_d<3> LOC = AF12; # LCD_DB7
|
||||
NET sys_lcd_d<2> LOC = AE12; # LCD_DB6
|
||||
NET sys_lcd_d<1> LOC = AC10; # LCD_DB5
|
||||
NET sys_lcd_d<0> LOC = AB10; # LCD_DB4
|
||||
NET sys_lcd_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_lcd_d<*> SLEW = SLOW;
|
||||
NET sys_lcd_d<*> DRIVE = 2;
|
||||
NET sys_lcd_d<*> PULLDOWN;
|
||||
NET sys_lcd_d<*> TIG;
|
||||
|
||||
#------------------------------------------------------------------------------
|
||||
# IO Pad Location Constraints / Properties for DDR Controllers
|
||||
#------------------------------------------------------------------------------
|
||||
|
||||
NET sys_sdr_a_q<0> LOC = C26; # DDR_A0
|
||||
NET sys_sdr_a_q<1> LOC = E17; # DDR_A1
|
||||
NET sys_sdr_a_q<2> LOC = D18; # DDR_A2
|
||||
NET sys_sdr_a_q<3> LOC = C19; # DDR_A3
|
||||
NET sys_sdr_a_q<4> LOC = F17; # DDR_A4
|
||||
NET sys_sdr_a_q<5> LOC = B18; # DDR_A5
|
||||
NET sys_sdr_a_q<6> LOC = B20; # DDR_A6
|
||||
NET sys_sdr_a_q<7> LOC = C20; # DDR_A7
|
||||
NET sys_sdr_a_q<8> LOC = D20; # DDR_A8
|
||||
NET sys_sdr_a_q<9> LOC = C21; # DDR_A9
|
||||
NET sys_sdr_a_q<10> LOC = A18; # DDR_A10
|
||||
NET sys_sdr_a_q<11> LOC = B21; # DDR_A11
|
||||
NET sys_sdr_a_q<12> LOC = A24; # DDR_A12
|
||||
NET sys_sdr_ba_q<0> LOC = B12; # DDR_BA0
|
||||
NET sys_sdr_ba_q<1> LOC = A16; # DDR_BA1
|
||||
NET sys_sdr_cas_qn LOC = F23; # DDR_CAS_N
|
||||
NET sys_sdr_cke_q LOC = G22; # DDR_CKE
|
||||
NET sys_sdr_cs_qn LOC = G21; # DDR_CS_N
|
||||
NET sys_sdr_ras_qn LOC = F24; # DDR_RAS_N
|
||||
NET sys_sdr_we_qn LOC = A23; # DDR_WE_N
|
||||
|
||||
NET sys_sdr_clk_p LOC = A10; # DDR_CK1_P
|
||||
NET sys_sdr_clk_fb LOC = B13; # DDR_CK1_P (FEEDBACK)
|
||||
NET sys_sdr_clk_n LOC = B10; # DDR_CK1_N
|
||||
|
||||
NET sys_sdr_dm_q<0> LOC = G19; # DDR_DM0
|
||||
NET sys_sdr_dm_q<1> LOC = G24; # DDR_DM1
|
||||
NET sys_sdr_dm_q<2> LOC = G20; # DDR_DM2
|
||||
NET sys_sdr_dm_q<3> LOC = C22; # DDR_DM3
|
||||
|
||||
NET sys_sdr_dqs_q<0> LOC = D25; # DDR_DQS0
|
||||
NET sys_sdr_dqs_q<1> LOC = G18; # DDR_DQS1
|
||||
NET sys_sdr_dqs_q<2> LOC = G17; # DDR_DQS2
|
||||
NET sys_sdr_dqs_q<3> LOC = D26; # DDR_DQS3
|
||||
|
||||
NET sys_sdr_data<0> LOC = H20; # DDR_D0
|
||||
NET sys_sdr_data<1> LOC = E23; # DDR_D1
|
||||
NET sys_sdr_data<2> LOC = H26; # DDR_D2
|
||||
NET sys_sdr_data<3> LOC = H22; # DDR_D3
|
||||
NET sys_sdr_data<4> LOC = E25; # DDR_D4
|
||||
NET sys_sdr_data<5> LOC = E26; # DDR_D5
|
||||
NET sys_sdr_data<6> LOC = F26; # DDR_D6
|
||||
NET sys_sdr_data<7> LOC = E24; # DDR_D7
|
||||
NET sys_sdr_data<8> LOC = E20; # DDR_D8
|
||||
NET sys_sdr_data<9> LOC = A22; # DDR_D9
|
||||
NET sys_sdr_data<10> LOC = C23; # DDR_D10
|
||||
NET sys_sdr_data<11> LOC = C24; # DDR_D11
|
||||
NET sys_sdr_data<12> LOC = A20; # DDR_D12
|
||||
NET sys_sdr_data<13> LOC = A21; # DDR_D13
|
||||
NET sys_sdr_data<14> LOC = D24; # DDR_D14
|
||||
NET sys_sdr_data<15> LOC = E18; # DDR_D15
|
||||
NET sys_sdr_data<16> LOC = F18; # DDR_D16
|
||||
NET sys_sdr_data<17> LOC = A19; # DDR_D17
|
||||
NET sys_sdr_data<18> LOC = F19; # DDR_D18
|
||||
NET sys_sdr_data<19> LOC = B23; # DDR_D19
|
||||
NET sys_sdr_data<20> LOC = E21; # DDR_D20
|
||||
NET sys_sdr_data<21> LOC = D22; # DDR_D21
|
||||
NET sys_sdr_data<22> LOC = D23; # DDR_D22
|
||||
NET sys_sdr_data<23> LOC = B24; # DDR_D23
|
||||
NET sys_sdr_data<24> LOC = E22; # DDR_D24
|
||||
NET sys_sdr_data<25> LOC = F20; # DDR_D25
|
||||
NET sys_sdr_data<26> LOC = H23; # DDR_D26
|
||||
NET sys_sdr_data<27> LOC = G25; # DDR_D27
|
||||
NET sys_sdr_data<28> LOC = G26; # DDR_D28
|
||||
NET sys_sdr_data<29> LOC = H25; # DDR_D29
|
||||
NET sys_sdr_data<30> LOC = H24; # DDR_D30
|
||||
NET sys_sdr_data<31> LOC = H21; # DDR_D31
|
||||
|
||||
NET sys_sdr_a_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_a_q<*> FAST;
|
||||
|
||||
NET sys_sdr_ba_q<*> IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ba_q<*> FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cke_q IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cke_q FAST;
|
||||
|
||||
NET sys_sdr_clk_p IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_p FAST;
|
||||
NET sys_sdr_clk_fb IOSTANDARD = LVCMOS25;
|
||||
NET sys_sdr_clk_fb IOBDELAY = NONE;
|
||||
NET sys_sdr_clk_n IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_clk_n FAST;
|
||||
|
||||
NET sys_sdr_cas_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cas_qn FAST;
|
||||
|
||||
NET sys_sdr_cs_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_cs_qn FAST;
|
||||
|
||||
NET sys_sdr_ras_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_ras_qn FAST;
|
||||
|
||||
NET sys_sdr_we_qn IOSTANDARD = SSTL2_I;
|
||||
NET sys_sdr_we_qn FAST;
|
||||
|
||||
NET sys_sdr_dqs_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dqs_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dqs_q<*> FAST;
|
||||
|
||||
NET sys_sdr_dm_q<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_dm_q<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_dm_q<*> FAST;
|
||||
|
||||
NET sys_sdr_data<*> IOSTANDARD = SSTL2_II;
|
||||
NET sys_sdr_data<*> IOBDELAY = NONE;
|
||||
NET sys_sdr_data<*> FAST;
|
||||
|
||||
#NET "sys_sdr_data<*>" OFFSET=OUT 2.5 ns BEFORE "sys_sdr_clk_n";
|
||||
|
||||
NET "sys_sdr_clk_p" TNM_NET = "ddr_clk_p";
|
||||
NET "sys_sdr_clk_n" TNM_NET = "ddr_clk_n";
|
||||
|
||||
# Timing Constraint for DDR Feedback Clock
|
||||
NET sys_sdr_clk_fb FEEDBACK = 1 ns NET sys_sdr_clk_p;
|
||||
|
||||
# USB
|
||||
NET sys_usb_a<0> LOC = Y10;
|
||||
NET sys_usb_a<1> LOC = AA10;
|
||||
NET sys_usb_a<*> IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_usb_d<0> LOC = AB7;
|
||||
NET sys_usb_d<1> LOC = AC9;
|
||||
NET sys_usb_d<2> LOC = AB9;
|
||||
NET sys_usb_d<3> LOC = AE6;
|
||||
NET sys_usb_d<4> LOC = AD6;
|
||||
NET sys_usb_d<5> LOC = AF9;
|
||||
NET sys_usb_d<6> LOC = AE9;
|
||||
NET sys_usb_d<7> LOC = AD8;
|
||||
NET sys_usb_d<8> LOC = AC8;
|
||||
NET sys_usb_d<9> LOC = AF4;
|
||||
NET sys_usb_d<10> LOC = AE4;
|
||||
NET sys_usb_d<11> LOC = AD3;
|
||||
NET sys_usb_d<12> LOC = AC3;
|
||||
NET sys_usb_d<13> LOC = AF6;
|
||||
NET sys_usb_d<14> LOC = AF5;
|
||||
NET sys_usb_d<15> LOC = AA7;
|
||||
NET sys_usb_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_d<*> SLEW = FAST;
|
||||
NET sys_usb_d<*> DRIVE = 8;
|
||||
NET sys_usb_d<*> PULLDOWN;
|
||||
|
||||
NET sys_usb_rdn LOC = AA8;
|
||||
NET sys_usb_rdn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_rdn SLEW = FAST;
|
||||
NET sys_usb_rdn DRIVE = 8;
|
||||
|
||||
NET sys_usb_wrn LOC = Y8;
|
||||
NET sys_usb_wrn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_wrn SLEW = FAST;
|
||||
NET sys_usb_wrn DRIVE = 8;
|
||||
|
||||
NET sys_usb_csn LOC = AF10;
|
||||
NET sys_usb_csn IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_csn SLEW = FAST;
|
||||
NET sys_usb_csn DRIVE = 8;
|
||||
|
||||
NET sys_usb_rstn LOC = A7;
|
||||
NET sys_usb_rstn IOSTANDARD = LVCMOS25;
|
||||
NET sys_usb_rstn TIG;
|
||||
|
||||
NET sys_usb_int LOC = V5;
|
||||
NET sys_usb_int IOSTANDARD = LVCMOS33;
|
||||
NET sys_usb_int PULLDOWN;
|
||||
NET sys_usb_int TIG;
|
||||
|
||||
# FLASH
|
||||
NET sys_flash_a<24> LOC = T21;
|
||||
NET sys_flash_a<23> LOC = U20;
|
||||
NET sys_flash_a<22> LOC = T19;
|
||||
NET sys_flash_a<21> LOC = AC5;
|
||||
NET sys_flash_a<20> LOC = AB5;
|
||||
NET sys_flash_a<19> LOC = AC4;
|
||||
NET sys_flash_a<18> LOC = AB4;
|
||||
NET sys_flash_a<17> LOC = AB3;
|
||||
NET sys_flash_a<16> LOC = AA4;
|
||||
NET sys_flash_a<15> LOC = AA3;
|
||||
NET sys_flash_a<14> LOC = W5;
|
||||
NET sys_flash_a<13> LOC = W6;
|
||||
NET sys_flash_a<12> LOC = W3;
|
||||
NET sys_flash_a<11> LOC = AF3;
|
||||
NET sys_flash_a<10> LOC = AE3;
|
||||
NET sys_flash_a<9> LOC = AD2;
|
||||
NET sys_flash_a<8> LOC = AD1;
|
||||
NET sys_flash_a<7> LOC = AC2;
|
||||
NET sys_flash_a<6> LOC = AC1;
|
||||
NET sys_flash_a<5> LOC = AB2;
|
||||
NET sys_flash_a<4> LOC = AB1;
|
||||
NET sys_flash_a<3> LOC = AA1;
|
||||
NET sys_flash_a<2> LOC = Y2;
|
||||
NET sys_flash_a<1> LOC = Y1;
|
||||
NET sys_flash_a<0> LOC = T20;
|
||||
|
||||
NET sys_flash_d<31> LOC = F14;
|
||||
NET sys_flash_d<30> LOC = F13;
|
||||
NET sys_flash_d<29> LOC = F12;
|
||||
NET sys_flash_d<28> LOC = F11;
|
||||
NET sys_flash_d<27> LOC = F16;
|
||||
NET sys_flash_d<26> LOC = F15;
|
||||
NET sys_flash_d<25> LOC = D14;
|
||||
NET sys_flash_d<24> LOC = D13;
|
||||
NET sys_flash_d<23> LOC = D15;
|
||||
NET sys_flash_d<22> LOC = E14;
|
||||
NET sys_flash_d<21> LOC = C11;
|
||||
NET sys_flash_d<20> LOC = D11;
|
||||
NET sys_flash_d<19> LOC = D16;
|
||||
NET sys_flash_d<18> LOC = C16;
|
||||
NET sys_flash_d<17> LOC = E13;
|
||||
NET sys_flash_d<16> LOC = D12;
|
||||
NET sys_flash_d<15> LOC = AA14;
|
||||
NET sys_flash_d<14> LOC = AB14;
|
||||
NET sys_flash_d<13> LOC = AC12;
|
||||
NET sys_flash_d<12> LOC = AC11;
|
||||
NET sys_flash_d<11> LOC = AA16;
|
||||
NET sys_flash_d<10> LOC = AA15;
|
||||
NET sys_flash_d<9> LOC = AB13;
|
||||
NET sys_flash_d<8> LOC = AA13;
|
||||
NET sys_flash_d<7> LOC = AC14;
|
||||
NET sys_flash_d<6> LOC = AD14;
|
||||
NET sys_flash_d<5> LOC = AA12;
|
||||
NET sys_flash_d<4> LOC = AA11;
|
||||
NET sys_flash_d<3> LOC = AC16;
|
||||
NET sys_flash_d<2> LOC = AC15;
|
||||
NET sys_flash_d<1> LOC = AC13;
|
||||
NET sys_flash_d<0> LOC = AD13;
|
||||
NET sys_flash_rdn LOC = AC6;
|
||||
NET sys_flash_wrn LOC = AB6;
|
||||
NET sys_flash_ce LOC = W7;
|
||||
NET sys_flash_rstn LOC = AD10;
|
||||
NET sys_flash_byten LOC = N22;
|
||||
|
||||
NET sys_flash_a<*> IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_a<*> SLEW = FAST;
|
||||
NET sys_flash_a<*> DRIVE = 8;
|
||||
|
||||
NET sys_flash_d<*> IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_d<*> DRIVE = 12;
|
||||
NET sys_flash_d<*> SLEW = FAST;
|
||||
NET sys_flash_d<*> PULLDOWN;
|
||||
|
||||
NET sys_flash_rdn IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_rdn SLEW = FAST;
|
||||
NET sys_flash_rdn DRIVE = 8;
|
||||
|
||||
NET sys_flash_wrn IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_wrn SLEW = FAST;
|
||||
NET sys_flash_wrn DRIVE = 8;
|
||||
|
||||
NET sys_flash_ce IOSTANDARD = LVDCI_33;
|
||||
NET sys_flash_ce SLEW = FAST;
|
||||
NET sys_flash_ce DRIVE = 8;
|
||||
|
||||
NET sys_flash_rstn IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_rstn DRIVE = 8;
|
||||
NET sys_flash_rstn SLEW = FAST;
|
||||
NET sys_flash_rstn TIG;
|
||||
|
||||
NET sys_flash_byten IOSTANDARD = LVCMOS33;
|
||||
NET sys_flash_byten DRIVE = 8;
|
||||
NET sys_flash_byten SLEW = FAST;
|
||||
NET sys_flash_byten TIG;
|
||||
|
||||
# VGA
|
||||
NET sys_vga_blue<0> LOC = M21; # VGA_B0
|
||||
NET sys_vga_blue<1> LOC = M26; # VGA_B1
|
||||
NET sys_vga_blue<2> LOC = L26; # VGA_B2
|
||||
NET sys_vga_blue<3> LOC = C5; # VGA_B3
|
||||
NET sys_vga_blue<4> LOC = C7; # VGA_B4
|
||||
NET sys_vga_blue<5> LOC = B7; # VGA_B5
|
||||
NET sys_vga_blue<6> LOC = G8; # VGA_B6
|
||||
NET sys_vga_blue<7> LOC = F8; # VGA_B7
|
||||
NET sys_vga_blue<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_blue<*> SLEW = FAST;
|
||||
NET sys_vga_blue<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_clk LOC = AF8;
|
||||
NET sys_vga_clk IOSTANDARD = LVDCI_33;
|
||||
NET sys_vga_clk SLEW = FAST;
|
||||
NET sys_vga_clk DRIVE = 8;
|
||||
|
||||
NET sys_vga_green<0> LOC = M22; # VGA_G0
|
||||
NET sys_vga_green<1> LOC = M23; # VGA_G1
|
||||
NET sys_vga_green<2> LOC = M20; # VGA_G2
|
||||
NET sys_vga_green<3> LOC = E4; # VGA_G3
|
||||
NET sys_vga_green<4> LOC = D3; # VGA_G4
|
||||
NET sys_vga_green<5> LOC = H7; # VGA_G5
|
||||
NET sys_vga_green<6> LOC = H8; # VGA_G6
|
||||
NET sys_vga_green<7> LOC = C1; # VGA_G7
|
||||
NET sys_vga_green<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_green<*> SLEW = FAST;
|
||||
NET sys_vga_green<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_hsync LOC = C10;
|
||||
NET sys_vga_hsync SLEW = FAST;
|
||||
NET sys_vga_hsync DRIVE = 8;
|
||||
#NET sys_vga_hsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_red<0> LOC = N23; #VGA_R0
|
||||
NET sys_vga_red<1> LOC = N24; #VGA_R1
|
||||
NET sys_vga_red<2> LOC = N25; #VGA_R2
|
||||
NET sys_vga_red<3> LOC = C2; #VGA_R3
|
||||
NET sys_vga_red<4> LOC = G7; #VGA_R4
|
||||
NET sys_vga_red<5> LOC = F7; #VGA_R5
|
||||
NET sys_vga_red<6> LOC = E5; #VGA_R6
|
||||
NET sys_vga_red<7> LOC = E6; #VGA_R7
|
||||
NET sys_vga_red<0> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<1> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<2> IOSTANDARD = LVCMOS33;
|
||||
NET sys_vga_red<*> SLEW = FAST;
|
||||
NET sys_vga_red<*> DRIVE = 8;
|
||||
|
||||
NET sys_vga_vsync LOC = A8;
|
||||
NET sys_vga_vsync SLEW = FAST;
|
||||
NET sys_vga_vsync DRIVE = 8;
|
||||
#NET sys_vga_vsync IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_blank_n LOC = M24;
|
||||
NET sys_vga_blank_n SLEW = FAST;
|
||||
NET sys_vga_blank_n DRIVE = 8;
|
||||
NET sys_vga_blank_n IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET sys_vga_sync_n LOC = L23;
|
||||
NET sys_vga_sync_n SLEW = FAST;
|
||||
NET sys_vga_sync_n DRIVE = 8;
|
||||
NET sys_vga_sync_n IOSTANDARD = LVCMOS33;
|
||||
@@ -1,106 +0,0 @@
|
||||
## NOTE: Do not edit this file.
|
||||
##
|
||||
vlib work
|
||||
# Configs
|
||||
vcom -explicit -93 "../src/sdram_config_sim.vhd"
|
||||
|
||||
# Packages
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd"
|
||||
|
||||
# RAMs
|
||||
vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/dpram_1w1r_dist.vhd"
|
||||
|
||||
# FIFOS
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_dist.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/async_fifo_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd"
|
||||
|
||||
# CPU
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_dcache.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_icache.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_biu.vhd"
|
||||
vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
|
||||
vcom -explicit -93 "../src/ram_sim.vhd"
|
||||
vcom -explicit -93 "../src/bootloader.ROM.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/ram_wb.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/rom_wb.vhd"
|
||||
|
||||
# VGA
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd"
|
||||
vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_frontend64.vhd"
|
||||
|
||||
# UART
|
||||
vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/kcuart_tx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/uart_rx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/uart_tx.vhd"
|
||||
vcom -explicit -93 "../../../lib/uart/uart_wb.vhd"
|
||||
|
||||
# GPIO
|
||||
vcom -explicit -93 "../../../lib/misc/gpio_wb.vhd"
|
||||
|
||||
# LCD
|
||||
vcom -explicit -93 "../../../lib/misc/lcd_port.vhd"
|
||||
|
||||
# Flash and USB
|
||||
vcom -explicit -93 "../../../lib/misc/async_types.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd"
|
||||
vcom -explicit -93 "../../../lib/misc/flash_port_wb.vhd"
|
||||
vcom -explicit -93 "../src/async_defs.vhd"
|
||||
|
||||
# Sync SRAM
|
||||
vcom -explicit -93 "../../../lib/SSRAM/src/package_utility.vhd"
|
||||
vcom -explicit -93 "../../../lib/SSRAM/src/CY7C1354B.vhd"
|
||||
vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd"
|
||||
|
||||
# SDRAM
|
||||
vcom -explicit -93 "../../../lib/misc/clockgen_virtex4.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
|
||||
vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd"
|
||||
|
||||
# AC-97
|
||||
vcom -explicit -93 "../../../lib/misc/singleshot.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_out.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_in.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac_io.vhd"
|
||||
vcom -explicit -93 "../../../lib/ac97_ctrl/src/core/ac97_wb.vhd"
|
||||
|
||||
# Top and TB
|
||||
vcom -explicit -93 "../src/mips_sys_sim.vhd"
|
||||
vcom -explicit -93 "../src/tb_mips_sys.vhd"
|
||||
|
||||
vsim -t 1ps -lib work tb_mips_sys
|
||||
do {tb_mips_sys.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 50ms
|
||||
@@ -1,360 +0,0 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider UUT
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_rst_n_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_clk_in
|
||||
add wave -noupdate -format Literal /tb_mips_sys/dip
|
||||
add wave -noupdate -format Literal /tb_mips_sys/btn
|
||||
add wave -noupdate -format Literal /tb_mips_sys/led
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_rx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_tx
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_lcd_d
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw
|
||||
add wave -noupdate -format Logic /tb_mips_sys/refresh
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cke_q
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_error
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -divider Arbiter
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt
|
||||
add wave -noupdate -divider AC97
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_in
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_sdata_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_reg_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/cmd_pending
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_valid
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/stat_pending
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_frame_valid
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_frame
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_tx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/sync_status
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_ac97_wb/request
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_data_start
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_data_start
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/ac97_stat
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_frame_sync
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_rx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/int_en_tx
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_almost_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_almost_empty
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/rx_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_almost_empty
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_ac97_wb/tx_fifo_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/ac_frame_reg
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_ssync
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_ac97_bit_clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/ac_synced
|
||||
add wave -noupdate -divider {CPU Master}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
|
||||
add wave -noupdate -divider {VGA Master}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_vga
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_vga
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga
|
||||
add wave -noupdate -divider BUI
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_icache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dcache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dmem_rd
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dmem_wr
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_icache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dcache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dmem_rd
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dmem_wr
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/uncached_access
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_timeout_cnt
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_timeout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we_out
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_sel_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_data_out
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_addr_out
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we_in
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_sel_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_data_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_addr_in
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_full
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_empty
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_busy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
|
||||
add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op
|
||||
add wave -noupdate -divider USB
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_csn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_wrn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rdn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_usb_int
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_usb_port/s
|
||||
add wave -noupdate -divider Flash
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ac97_rstn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/flash_do
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_oe_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_we_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_d_drv
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/flash_bsy
|
||||
add wave -noupdate -divider {Sync SRAM}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_cke_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_ce_n
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_dp
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_adv
|
||||
add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_bw_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_mode
|
||||
add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_zz
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_we_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_flash_ssram_oe_n
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_a
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/ssram_do
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_oe_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_we_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_d_drv
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/ssram_bsy
|
||||
add wave -noupdate -divider {MIPS TOP}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/events
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/badvaddr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_code
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status_save
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status_rest
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/test_reg
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/test_reg_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ir
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ir_valid
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_in
|
||||
add wave -noupdate -format Literal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags_reg_we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/eflags
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_run
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_reg_dual/reg_mem
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/id_stage
|
||||
add wave -noupdate -format Logic -label .exc_commit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_commit
|
||||
add wave -noupdate -format Logic -label .exc_pending /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_pending
|
||||
add wave -noupdate -format Logic -label .exc_exit /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.exc_exit
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exc_state
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/mem_stage
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/dout
|
||||
add wave -noupdate -format Logic -label .cop_read /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/ctrl_out.cop_read
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/sdu
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/wb_stage
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/status
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/exception
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/cause
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/inst_cop/epc
|
||||
add wave -noupdate -divider {CPU DMEM}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_be
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr
|
||||
add wave -noupdate -divider {CPU IMEM}
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_din
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_imem_rdy
|
||||
add wave -noupdate -divider {User ROM}
|
||||
add wave -noupdate -divider UUT
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_a_q
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_ba_q
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cas_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cke_q
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_fb
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_n
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_clk_p
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_cs_qn
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/sys_sdr_data
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dm_q
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/sys_sdr_dqs_q
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_ras_qn
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/sys_sdr_we_qn
|
||||
add wave -noupdate -divider I-Cache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/cpu_rst
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_pipeline/run_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_pipeline/pc
|
||||
add wave -noupdate -format Logic -label .branch -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.ctrl.branch
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/s
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cpu_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_busy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/cache_miss
|
||||
add wave -noupdate -format Literal -label tag_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_tag_ram/ram
|
||||
add wave -noupdate -format Literal -label data_ram -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/inst_data_ram/ram
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_addr_wr
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_ram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/ram_index_count
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/mem_index_count
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_icache/data_write
|
||||
add wave -noupdate -divider D-Cache
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/clk
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_din
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we_reg
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/s
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_busy
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_hit
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_reg_en
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/was_miss
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/data_write
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_index_count
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/word_index_reg
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_word_index
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/instant_raw
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_dout
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_hit_we
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_en
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_addr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_din
|
||||
add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_we
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_addr_rd
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_dout
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_addr_wr
|
||||
add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_din
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_re
|
||||
add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_we
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {23579127600 ps} 0} {{Cursor 100} {5544988254 ps} 0}
|
||||
configure wave -namecolwidth 187
|
||||
configure wave -valuecolwidth 64
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {37535226330 ps}
|
||||
@@ -1,4 +0,0 @@
|
||||
VHDL/projects/mips_sys/src/async_defs.vhd
|
||||
|
||||
VHDL/projects/mips_sys/src/sys_types.vhd
|
||||
VHDL/projects/mips_sys/src/async_defs.vhd
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,918 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
Library UNISIM;
|
||||
use UNISIM.vcomponents.all;
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
--use work.fifo_ctrl_pkg.all;
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
use work.vga_types.all;
|
||||
use work.async_types.all;
|
||||
use work.async_defs.all;
|
||||
|
||||
|
||||
ENTITY mips_sys IS
|
||||
GENERIC
|
||||
(
|
||||
sys_freq : integer := 100E6;
|
||||
ddr_phaseshift : integer := 0;
|
||||
ddr_frequency_hz : integer := 100E6
|
||||
);
|
||||
PORT
|
||||
(
|
||||
sys_rst_n_in : in std_logic;
|
||||
sys_clk_in : in std_logic;
|
||||
|
||||
-- Buttons and LEDs
|
||||
sys_btn : in unsigned(4 downto 0);
|
||||
sys_dip : in unsigned(7 downto 0);
|
||||
sys_led : out unsigned(8 downto 0);
|
||||
|
||||
-- UART
|
||||
sys_rx : in std_logic;
|
||||
sys_tx : out std_logic;
|
||||
|
||||
-- LCD
|
||||
sys_lcd_d : inout unsigned(3 downto 0);
|
||||
sys_lcd_e : out std_logic;
|
||||
sys_lcd_rs : out std_logic;
|
||||
sys_lcd_rw : out std_logic;
|
||||
|
||||
-- DDR SDRAM
|
||||
sys_sdr_clk_p : out std_logic; -- ddr_sdram_clock
|
||||
sys_sdr_clk_n : out std_logic; -- /ddr_sdram_clock
|
||||
sys_sdr_cke_q : out std_logic; -- clock enable
|
||||
sys_sdr_cs_qn : out std_logic; -- /chip select
|
||||
sys_sdr_ras_qn : out std_logic; -- /ras
|
||||
sys_sdr_cas_qn : out std_logic; -- /cas
|
||||
sys_sdr_we_qn : out std_logic; -- /write enable
|
||||
sys_sdr_dm_q : out unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00"
|
||||
sys_sdr_dqs_q : inout unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write
|
||||
sys_sdr_ba_q : out unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select
|
||||
sys_sdr_a_q : out unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus
|
||||
sys_sdr_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
|
||||
sys_sdr_clk_fb : in std_logic;
|
||||
|
||||
-- VGA
|
||||
sys_vga_clk : out std_logic;
|
||||
sys_vga_red : out unsigned(7 downto 0);
|
||||
sys_vga_green : out unsigned(7 downto 0);
|
||||
sys_vga_blue : out unsigned(7 downto 0);
|
||||
sys_vga_blank_n : out std_logic;
|
||||
sys_vga_sync_n : out std_logic;
|
||||
sys_vga_hsync : out std_logic;
|
||||
sys_vga_vsync : out std_logic;
|
||||
|
||||
sys_usb_d : inout unsigned(15 downto 0);
|
||||
sys_usb_a : out unsigned(1 downto 0);
|
||||
sys_usb_csn : out std_logic;
|
||||
sys_usb_wrn : out std_logic;
|
||||
sys_usb_rdn : out std_logic;
|
||||
sys_usb_rstn : out std_logic;
|
||||
sys_usb_int : in std_logic;
|
||||
|
||||
sys_flash_d : inout unsigned(31 downto 0);
|
||||
sys_flash_a : out unsigned(24 downto 0);
|
||||
sys_flash_ce : out std_logic;
|
||||
sys_flash_wrn : out std_logic;
|
||||
sys_flash_rdn : out std_logic;
|
||||
sys_flash_ac97_rstn : out std_logic;
|
||||
sys_flash_byten : out std_logic;
|
||||
|
||||
sys_ac97_sdata_in : in std_logic;
|
||||
sys_ac97_bit_clk : in std_logic;
|
||||
sys_ac97_sdata_out : out std_logic;
|
||||
sys_ac97_ssync : out std_logic;
|
||||
|
||||
sys_error : out unsigned(1 downto 0) -- indicates Errors
|
||||
|
||||
);
|
||||
-- attribute BUFFER_TYPE : string;
|
||||
-- attribute BUFFER_TYPE of sys_clk_in : signal is "BUFG";
|
||||
-- attribute BUFFER_TYPE of sys_sdr_dcm_clk_fb : signal is "BUFG";
|
||||
|
||||
END mips_sys;
|
||||
|
||||
ARCHITECTURE behavior OF mips_sys IS
|
||||
|
||||
COMPONENT mips_top
|
||||
Port
|
||||
(
|
||||
debug : out unsigned(1 downto 0);
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
ADDR_O : out word_t;
|
||||
DAT_I : in word_t;
|
||||
DAT_O : out word_t;
|
||||
WE_O : out STD_LOGIC;
|
||||
SEL_O : out unsigned(3 downto 0);
|
||||
CYC_O : out STD_LOGIC;
|
||||
STB_O : out STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
INT : in unsigned (5 downto 0)
|
||||
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT rom_wb
|
||||
PORT
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT ram_wb
|
||||
PORT
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT lcd_port
|
||||
PORT
|
||||
(
|
||||
rst : in std_logic;
|
||||
clk : in std_logic;
|
||||
we : in std_logic;
|
||||
din : in unsigned(7 downto 0);
|
||||
dout : out unsigned(7 downto 0);
|
||||
lcd_d : inout unsigned(3 downto 0);
|
||||
lcd_e : out std_logic;
|
||||
lcd_rs : out std_logic;
|
||||
lcd_rw : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT async_port_wb
|
||||
GENERIC
|
||||
(
|
||||
addr_width : natural := 32;
|
||||
data_width : natural := 32;
|
||||
byte_sel_width : natural := 4;
|
||||
async_timespec : async_timespec_t
|
||||
);
|
||||
PORT
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
async_a : out unsigned(addr_width-1 downto 0);
|
||||
async_d : inout unsigned(data_width-1 downto 0);
|
||||
async_cs : out std_logic;
|
||||
async_wr : out unsigned(byte_sel_width-1 downto 0);
|
||||
async_rd : out std_logic;
|
||||
async_rst : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT uart_wb
|
||||
PORT
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
INT_RX_O : out STD_LOGIC;
|
||||
INT_TX_O : out STD_LOGIC;
|
||||
ser_rx : in std_logic;
|
||||
ser_tx : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT gpio_wb
|
||||
PORT
|
||||
(
|
||||
CLK_I : in STD_LOGIC;
|
||||
RST_I : in STD_LOGIC;
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
WE_I : in STD_LOGIC;
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
DAT_I : in unsigned(31 downto 0);
|
||||
DAT_O : out unsigned(31 downto 0);
|
||||
|
||||
sys_gpo0 : out unsigned(31 downto 0);
|
||||
sys_gpo1 : out unsigned(31 downto 0);
|
||||
sys_gpi0 : in unsigned(31 downto 0);
|
||||
sys_gpi1 : in unsigned(31 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT vga_frontend64
|
||||
GENERIC
|
||||
(
|
||||
sys_freq : integer;
|
||||
fifo_depth : integer;
|
||||
fifo_almost_full_thresh : natural;
|
||||
fifo_almost_empty_thresh : natural;
|
||||
tsvga : vga_timespec_t
|
||||
);
|
||||
PORT
|
||||
(
|
||||
-- System signals
|
||||
RST_I : in STD_LOGIC;
|
||||
CLK_I : in STD_LOGIC;
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O : out STD_LOGIC;
|
||||
STB_O : out STD_LOGIC;
|
||||
WE_O : out STD_LOGIC;
|
||||
SEL_O : out unsigned(7 downto 0);
|
||||
ACK_I : in STD_LOGIC;
|
||||
SRDY_I : in STD_LOGIC;
|
||||
MRDY_O : out STD_LOGIC;
|
||||
ADDR_O : out unsigned(31 downto 0);
|
||||
MDAT_I : in unsigned(63 downto 0);
|
||||
MDAT_O : out unsigned(63 downto 0);
|
||||
|
||||
-- JBUS Slave signals
|
||||
CYC_I : in STD_LOGIC;
|
||||
STB_I : in STD_LOGIC;
|
||||
WE_I : in STD_LOGIC;
|
||||
SEL_I : in unsigned(3 downto 0);
|
||||
ACK_O : out STD_LOGIC;
|
||||
SRDY_O : out STD_LOGIC;
|
||||
MRDY_I : in STD_LOGIC;
|
||||
ADDR_I : in unsigned(31 downto 0);
|
||||
SDAT_I : in unsigned(31 downto 0);
|
||||
SDAT_O : out unsigned(31 downto 0);
|
||||
|
||||
-- VGA signals
|
||||
vga_clk_out : out std_logic;
|
||||
vga_red : out unsigned(7 downto 0);
|
||||
vga_green : out unsigned(7 downto 0);
|
||||
vga_blue : out unsigned(7 downto 0);
|
||||
vga_blank_n : out std_logic;
|
||||
vga_sync_n : out std_logic;
|
||||
vga_hsync : out std_logic;
|
||||
vga_vsync : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal rst : std_logic;
|
||||
signal clk : std_logic;
|
||||
signal clk270 : std_logic;
|
||||
signal clk270var : std_logic;
|
||||
signal rst_in : std_logic;
|
||||
signal int_uart_rx : std_logic;
|
||||
signal locked : std_logic;
|
||||
signal usb_addr : unsigned(31 downto 0);
|
||||
signal flash_addr : unsigned(31 downto 0);
|
||||
signal ac97_rstn : std_logic;
|
||||
signal flash_rstn : std_logic;
|
||||
signal usb_wrn : unsigned(0 downto 0);
|
||||
signal flash_wrn : unsigned(0 downto 0);
|
||||
|
||||
-- Arbiter
|
||||
constant ARB_MAX_MASTER : natural := 2;
|
||||
signal arb_idx : natural range 0 to ARB_MAX_MASTER-1;
|
||||
signal arb_req : unsigned (ARB_MAX_MASTER-1 downto 0);
|
||||
signal arb_gnt : unsigned (ARB_MAX_MASTER-1 downto 0);
|
||||
|
||||
-- J-Bus signals
|
||||
signal INT : unsigned(5 downto 0);
|
||||
signal MDAT_I : word_t;
|
||||
signal MDAT_O : word_t;
|
||||
signal ADDR_O : word_t;
|
||||
signal SEL_O : unsigned(3 downto 0);
|
||||
signal WE_O : std_logic;
|
||||
signal CYC_O : std_logic;
|
||||
signal STB_O : std_logic;
|
||||
signal ACK_I : std_logic;
|
||||
signal SRDY_I : std_logic;
|
||||
signal MRDY_O : std_logic;
|
||||
|
||||
-- CPU Master
|
||||
signal MRDY_O_cpu : std_logic;
|
||||
signal MDAT_O_cpu : word_t;
|
||||
signal ADDR_O_cpu : word_t;
|
||||
signal SEL_O_cpu : unsigned(3 downto 0);
|
||||
signal WE_O_cpu : std_logic;
|
||||
signal CYC_O_cpu : std_logic;
|
||||
signal STB_O_cpu : std_logic;
|
||||
signal SRDY_I_cpu : std_logic;
|
||||
signal ACK_I_cpu : std_logic;
|
||||
|
||||
-- VGA Master
|
||||
signal MRDY_O_vga : std_logic;
|
||||
signal ADDR_O_vga : word_t;
|
||||
signal SEL_O_vga : unsigned(7 downto 0);
|
||||
signal WE_O_vga : std_logic;
|
||||
signal CYC_O_vga : std_logic;
|
||||
signal STB_O_vga : std_logic;
|
||||
signal SRDY_I_vga : std_logic;
|
||||
signal ACK_I_vga : std_logic;
|
||||
signal MDAT_I_vga : unsigned(63 downto 0);
|
||||
signal MDAT_O_vga : unsigned(63 downto 0);
|
||||
|
||||
-- Slaves
|
||||
signal CYC_I_flash : std_logic;
|
||||
signal ACK_O_flash : std_logic;
|
||||
signal SRDY_O_flash : std_logic;
|
||||
signal SDAT_O_flash : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_usb : std_logic;
|
||||
signal ACK_O_usb : std_logic;
|
||||
signal SRDY_O_usb : std_logic;
|
||||
signal SDAT_O_usb : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_sdram : std_logic;
|
||||
signal ACK_O_sdram : std_logic;
|
||||
signal SRDY_O_sdram : std_logic;
|
||||
signal SDAT_O_sdram : unsigned(63 downto 0);
|
||||
signal SDAT_I_sdram : unsigned(63 downto 0);
|
||||
signal SEL_I_sdram : unsigned(7 downto 0);
|
||||
|
||||
signal CYC_I_ram : std_logic;
|
||||
signal ACK_O_ram : std_logic;
|
||||
signal SRDY_O_ram : std_logic;
|
||||
signal SDAT_O_ram : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_rom : std_logic;
|
||||
signal ACK_O_rom : std_logic;
|
||||
signal SRDY_O_rom : std_logic;
|
||||
signal SDAT_O_rom : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_gpio : std_logic;
|
||||
signal ACK_O_gpio : std_logic;
|
||||
signal SRDY_O_gpio : std_logic;
|
||||
signal SDAT_O_gpio : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_uart : std_logic;
|
||||
signal ACK_O_uart : std_logic;
|
||||
signal SRDY_O_uart : std_logic;
|
||||
signal SDAT_O_uart : unsigned(31 downto 0);
|
||||
|
||||
signal CYC_I_vga : std_logic;
|
||||
signal ACK_O_vga : std_logic;
|
||||
signal SRDY_O_vga : std_logic;
|
||||
signal SDAT_O_vga : unsigned(31 downto 0);
|
||||
|
||||
signal INT_O_ac97 : std_logic;
|
||||
signal CYC_I_ac97 : std_logic;
|
||||
signal ACK_O_ac97 : std_logic;
|
||||
signal SRDY_O_ac97 : std_logic;
|
||||
signal SDAT_O_ac97 : unsigned(31 downto 0);
|
||||
|
||||
signal gpo0 : unsigned(31 downto 0);
|
||||
signal gpo1 : unsigned(31 downto 0);
|
||||
signal gpi0 : unsigned(31 downto 0);
|
||||
signal gpi1 : unsigned(31 downto 0);
|
||||
|
||||
signal debug : unsigned(1 downto 0);
|
||||
|
||||
-- DDR SDRAM
|
||||
constant BURST_LEN : natural := 2;
|
||||
|
||||
|
||||
-- attribute rom_style: string;
|
||||
-- attribute rom_style of cmd_fifo_dout: signal is "DISTRIBUTED";
|
||||
-- attribute rom_style of cpu_cpu_write_fifo_dout: signal is "DISTRIBUTED";
|
||||
-- attribute rom_style of cpu_read_fifo_dout: signal is "DISTRIBUTED";
|
||||
|
||||
type mem_area_t is (mem_dead, mem_flash, mem_usb, mem_rom, mem_ram, mem_gpio, mem_uart, mem_sdram, mem_vga, mem_ac97);
|
||||
signal mem_area : mem_area_t;
|
||||
|
||||
BEGIN
|
||||
|
||||
gpi0(4 downto 0) <= sys_btn;
|
||||
gpi1(7 downto 0) <= sys_dip;
|
||||
sys_led <= gpo0(8 downto 0);
|
||||
sys_error <= debug;
|
||||
rst_in <= not sys_rst_n_in;
|
||||
rst <= not locked;
|
||||
sys_usb_rstn <= not gpo1(0);
|
||||
sys_flash_byten <= '1';
|
||||
usb_addr <= X"0000000" & "00" & ADDR_O(3 downto 2);
|
||||
flash_addr <= "0000000" & ADDR_O(25 downto 2) & '0';
|
||||
|
||||
SDAT_I_sdram <= MDAT_O & MDAT_O;
|
||||
SEL_I_sdram <= "0000" & SEL_O;
|
||||
|
||||
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
|
||||
sys_usb_wrn <= usb_wrn(0);
|
||||
sys_flash_wrn <= flash_wrn(0);
|
||||
|
||||
---------------------------------------------------------------
|
||||
-- Arbiter
|
||||
MRDY_O <= MRDY_O_cpu when arb_gnt(0) = '1' else MRDY_O_vga when arb_gnt(1) = '1' else '0';
|
||||
MDAT_O <= MDAT_O_cpu when arb_gnt(0) = '1' else MDAT_O_vga(31 downto 0) when arb_gnt(1) = '1' else (others => '0');
|
||||
ADDR_O <= ADDR_O_cpu when arb_gnt(0) = '1' else ADDR_O_vga when arb_gnt(1) = '1' else (others => '0');
|
||||
SEL_O <= SEL_O_cpu when arb_gnt(0) = '1' else SEL_O_vga(3 downto 0) when arb_gnt(1) = '1' else (others => '0');
|
||||
WE_O <= WE_O_cpu when arb_gnt(0) = '1' else WE_O_vga when arb_gnt(1) = '1' else '0';
|
||||
CYC_O <= CYC_O_cpu when arb_gnt(0) = '1' else CYC_O_vga when arb_gnt(1) = '1' else '0';
|
||||
STB_O <= STB_O_cpu when arb_gnt(0) = '1' else STB_O_vga when arb_gnt(1) = '1' else '0';
|
||||
SRDY_I_cpu <= SRDY_I and arb_gnt(0);
|
||||
SRDY_I_vga <= SRDY_I and arb_gnt(1);
|
||||
ACK_I_cpu <= ACK_I and arb_gnt(0);
|
||||
ACK_I_vga <= ACK_I and arb_gnt(1);
|
||||
|
||||
arb_req(0) <= CYC_O_cpu;
|
||||
arb_req(1) <= CYC_O_vga;
|
||||
|
||||
MDAT_I_vga <= SDAT_O_sdram(63 downto 32) & MDAT_I;
|
||||
|
||||
arbiter_proc:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
arb_gnt <= (others => '0');
|
||||
arb_idx <= 0;
|
||||
elsif arb_req(arb_idx) = '0' then
|
||||
if arb_idx /= ARB_MAX_MASTER-1 then
|
||||
arb_idx <= arb_idx + 1;
|
||||
else
|
||||
arb_idx <= 0;
|
||||
end if;
|
||||
else
|
||||
arb_gnt <= (others => '0');
|
||||
arb_gnt(arb_idx) <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
int_sample:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
int <= "00" & INT_O_ac97 & sys_usb_int & int_uart_rx & sys_btn(4);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
mem_mux:
|
||||
process(ADDR_O)
|
||||
begin
|
||||
mem_area <= mem_dead;
|
||||
-- if ADDR_O(31 downto 28) = X"0" then
|
||||
-- mem_area <= mem_flash;
|
||||
if ADDR_O(31 downto 28) = X"A" then
|
||||
if ADDR_O(27 downto 26) = "00" then
|
||||
if ADDR_O(18 downto 16) = "000" then
|
||||
mem_area <= mem_gpio;
|
||||
elsif ADDR_O(18 downto 16) = "001" then
|
||||
mem_area <= mem_uart;
|
||||
elsif ADDR_O(18 downto 16) = "010" then
|
||||
mem_area <= mem_usb;
|
||||
elsif ADDR_O(18 downto 16) = "011" then
|
||||
mem_area <= mem_vga;
|
||||
elsif ADDR_O(18 downto 16) = "100" then
|
||||
mem_area <= mem_ac97;
|
||||
end if;
|
||||
elsif ADDR_O(27 downto 26) = "01" then
|
||||
mem_area <= mem_flash;
|
||||
end if;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '0') then
|
||||
mem_area <= mem_rom;
|
||||
elsif (ADDR_O(31 downto 28) = X"B" and ADDR_O(15) = '1') then
|
||||
mem_area <= mem_ram;
|
||||
elsif (ADDR_O(31 downto 28) = X"8" or ADDR_O(30) = '1') then
|
||||
mem_area <= mem_sdram;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
signal_mux:
|
||||
process(mem_area, CYC_O)
|
||||
begin
|
||||
|
||||
CYC_I_uart <= '0';
|
||||
CYC_I_gpio <= '0';
|
||||
CYC_I_flash <= '0';
|
||||
CYC_I_usb <= '0';
|
||||
CYC_I_rom <= '0';
|
||||
CYC_I_ram <= '0';
|
||||
CYC_I_sdram <= '0';
|
||||
CYC_I_vga <= '0';
|
||||
CYC_I_ac97 <= '0';
|
||||
|
||||
case mem_area is
|
||||
|
||||
when mem_gpio =>
|
||||
CYC_I_gpio <= CYC_O;
|
||||
|
||||
when mem_uart =>
|
||||
CYC_I_uart <= CYC_O;
|
||||
|
||||
when mem_flash =>
|
||||
CYC_I_flash <= CYC_O;
|
||||
|
||||
when mem_usb =>
|
||||
CYC_I_usb <= CYC_O;
|
||||
|
||||
when mem_rom =>
|
||||
CYC_I_rom <= CYC_O;
|
||||
|
||||
when mem_ram =>
|
||||
CYC_I_ram <= CYC_O;
|
||||
|
||||
when mem_sdram =>
|
||||
CYC_I_sdram <= CYC_O;
|
||||
|
||||
when mem_vga =>
|
||||
CYC_I_vga <= CYC_O;
|
||||
|
||||
when mem_ac97 =>
|
||||
CYC_I_ac97 <= CYC_O;
|
||||
|
||||
when others => null;
|
||||
|
||||
end case;
|
||||
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------------
|
||||
SRDY_I <= SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_ram or SRDY_O_rom or SRDY_O_uart or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
|
||||
ACK_I <= ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_ram or ACK_O_rom or ACK_O_uart or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
|
||||
MDAT_I <= SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
|
||||
SDAT_O_ram when CYC_I_ram = '1' else
|
||||
SDAT_O_rom when CYC_I_rom = '1' else
|
||||
SDAT_O_flash when CYC_I_flash = '1' else
|
||||
SDAT_O_usb when CYC_I_usb = '1' else
|
||||
SDAT_O_uart when CYC_I_uart = '1' else
|
||||
SDAT_O_vga when CYC_I_vga = '1' else
|
||||
SDAT_O_ac97 when CYC_I_ac97 = '1' else
|
||||
SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
|
||||
|
||||
------------------------------------------------------------------
|
||||
inst_mips_top: mips_top
|
||||
PORT MAP
|
||||
(
|
||||
debug => debug,
|
||||
RST_I => rst,
|
||||
CLK_I => clk,
|
||||
ACK_I => ACK_I_cpu,
|
||||
SRDY_I => SRDY_I_cpu,
|
||||
MRDY_O => MRDY_O_cpu,
|
||||
CYC_O => CYC_O_cpu,
|
||||
STB_O => STB_O_cpu,
|
||||
WE_O => WE_O_cpu,
|
||||
SEL_O => SEL_O_cpu,
|
||||
DAT_I => MDAT_I,
|
||||
DAT_O => MDAT_O_cpu,
|
||||
ADDR_O => ADDR_O_cpu,
|
||||
INT => INT
|
||||
);
|
||||
|
||||
inst_ram_wb : ram_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_ram,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_ram,
|
||||
SRDY_O => SRDY_O_ram,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_ram
|
||||
);
|
||||
|
||||
inst_rom_wb : rom_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_rom,
|
||||
STB_I => STB_O,
|
||||
ACK_O => ACK_O_rom,
|
||||
MRDY_I => MRDY_O,
|
||||
SRDY_O => SRDY_O_rom,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_O => SDAT_O_rom
|
||||
);
|
||||
|
||||
|
||||
inst_lcd_port: lcd_port
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
we => '0',
|
||||
din => X"00",
|
||||
dout => open,
|
||||
lcd_d => sys_lcd_d,
|
||||
lcd_e => sys_lcd_e,
|
||||
lcd_rs => sys_lcd_rs,
|
||||
lcd_rw => sys_lcd_rw
|
||||
);
|
||||
|
||||
inst_gpio_wb : gpio_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_gpio,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_gpio,
|
||||
SRDY_O => SRDY_O_gpio,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_gpio,
|
||||
|
||||
sys_gpo0 => gpo0,
|
||||
sys_gpo1 => gpo1,
|
||||
sys_gpi0 => gpi0,
|
||||
sys_gpi1 => gpi1
|
||||
);
|
||||
|
||||
inst_flash_port : async_port_wb
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 25,
|
||||
data_width => 32,
|
||||
byte_sel_width => 1,
|
||||
async_timespec => ts_flash
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_flash,
|
||||
STB_I => STB_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_flash,
|
||||
SRDY_O => SRDY_O_flash,
|
||||
MRDY_I => MRDY_O,
|
||||
SEL_I => SEL_O,
|
||||
ADDR_I => flash_addr,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_flash,
|
||||
async_a => sys_flash_a,
|
||||
async_d => sys_flash_d,
|
||||
async_cs => sys_flash_ce,
|
||||
async_wr => flash_wrn,
|
||||
async_rd => sys_flash_rdn,
|
||||
async_rst => flash_rstn
|
||||
);
|
||||
|
||||
inst_usb_port : async_port_wb
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 2,
|
||||
data_width => 16,
|
||||
byte_sel_width => 1,
|
||||
async_timespec => ts_usb
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_usb,
|
||||
STB_I => STB_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_usb,
|
||||
SRDY_O => SRDY_O_usb,
|
||||
MRDY_I => MRDY_O,
|
||||
SEL_I => SEL_O,
|
||||
ADDR_I => usb_addr,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_usb,
|
||||
async_a => sys_usb_a,
|
||||
async_d => sys_usb_d,
|
||||
async_cs => sys_usb_csn,
|
||||
async_wr => usb_wrn,
|
||||
async_rd => sys_usb_rdn,
|
||||
async_rst => open
|
||||
);
|
||||
|
||||
inst_uart_wb : uart_wb
|
||||
PORT MAP
|
||||
(
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_uart,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_uart,
|
||||
SRDY_O => SRDY_O_uart,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_uart,
|
||||
INT_RX_O => int_uart_rx,
|
||||
INT_TX_O => open,
|
||||
ser_rx => sys_rx,
|
||||
ser_tx => sys_tx
|
||||
);
|
||||
|
||||
|
||||
inst_sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend64_wb
|
||||
GENERIC MAP
|
||||
(
|
||||
BL => BURST_LEN,
|
||||
f_sysclk => ddr_frequency_hz,
|
||||
fifo_depth => 5
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
RST_I => rst,
|
||||
CLK_I => clk,
|
||||
CLK270_I => clk270,
|
||||
CLK270VAR_I => clk270var,
|
||||
|
||||
CYC_I => CYC_I_sdram,
|
||||
STB_I => STB_O,
|
||||
SEL_I => SEL_I_sdram,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_sdram,
|
||||
MRDY_I => MRDY_O,
|
||||
SRDY_O => SRDY_O_sdram,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => SDAT_I_sdram,
|
||||
DAT_O => SDAT_O_sdram,
|
||||
|
||||
-- SDRAM signals
|
||||
sd_clk_p => sys_sdr_clk_p,
|
||||
sd_clk_n => sys_sdr_clk_n,
|
||||
sd_cke => sys_sdr_cke_q,
|
||||
sd_cs_n => sys_sdr_cs_qn,
|
||||
sd_cas_n => sys_sdr_cas_qn,
|
||||
sd_ras_n => sys_sdr_ras_qn,
|
||||
sd_we_n => sys_sdr_we_qn,
|
||||
sd_addr => sys_sdr_a_q,
|
||||
sd_ba => sys_sdr_ba_q,
|
||||
sd_dm => sys_sdr_dm_q,
|
||||
sd_dqs => sys_sdr_dqs_q,
|
||||
sd_data => sys_sdr_data
|
||||
|
||||
);
|
||||
|
||||
inst_clockgen : entity work.clockgen
|
||||
GENERIC MAP
|
||||
(
|
||||
sys1_phaseshift => 0,
|
||||
frequency_hz => 100E6
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- Clocks and Reset
|
||||
rst => rst_in, -- external async reset, low active
|
||||
clk_in => sys_clk_in, -- system clock (e.g. 100MHz), from board
|
||||
clk_fb_in => sys_sdr_clk_fb, -- feedback clock
|
||||
sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
|
||||
sys1_clk270_out => clk270var, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
|
||||
sys0_clk0_out => clk, -- System clock #0, dcm#0 output 0°
|
||||
sys0_clk270_out => clk270, -- System clock #0, dcm#0 output 270°
|
||||
locked_out => locked, -- DCM locked status
|
||||
error_out => open
|
||||
);
|
||||
|
||||
inst_vga_frontend : vga_frontend64
|
||||
GENERIC MAP
|
||||
(
|
||||
sys_freq => 100E6,
|
||||
fifo_depth => 2048,
|
||||
fifo_almost_full_thresh => 1860,
|
||||
fifo_almost_empty_thresh => 256,
|
||||
tsvga => ts_vga_800_600_72
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- System signals
|
||||
RST_I => rst,
|
||||
CLK_I => clk,
|
||||
|
||||
-- JBUS Master signals
|
||||
CYC_O => CYC_O_vga,
|
||||
STB_O => STB_O_vga,
|
||||
WE_O => WE_O_vga,
|
||||
SEL_O => SEL_O_vga,
|
||||
ACK_I => ACK_I_vga,
|
||||
SRDY_I => SRDY_I_vga,
|
||||
MRDY_O => MRDY_O_vga,
|
||||
ADDR_O => ADDR_O_vga,
|
||||
MDAT_I => MDAT_I_vga,
|
||||
MDAT_O => MDAT_O_vga,
|
||||
|
||||
-- JBUS Slave signals
|
||||
CYC_I => CYC_I_vga,
|
||||
STB_I => STB_O,
|
||||
WE_I => WE_O,
|
||||
SEL_I => SEL_O,
|
||||
ACK_O => ACK_O_vga,
|
||||
SRDY_O => SRDY_O_vga,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
SDAT_I => MDAT_O,
|
||||
SDAT_O => SDAT_O_vga,
|
||||
|
||||
-- VGA signals
|
||||
vga_clk_out => sys_vga_clk,
|
||||
vga_red => sys_vga_red,
|
||||
vga_green => sys_vga_green,
|
||||
vga_blue => sys_vga_blue,
|
||||
vga_blank_n => sys_vga_blank_n,
|
||||
vga_sync_n => sys_vga_sync_n,
|
||||
vga_hsync => sys_vga_hsync,
|
||||
vga_vsync => sys_vga_vsync
|
||||
);
|
||||
|
||||
inst_ac97_wb : entity work.ac97_wb
|
||||
GENERIC MAP
|
||||
(
|
||||
fifo_depth => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
-- J-Bus domain
|
||||
CLK_I => clk,
|
||||
RST_I => rst,
|
||||
CYC_I => CYC_I_ac97,
|
||||
STB_I => STB_O,
|
||||
WE_I => WE_O,
|
||||
ACK_O => ACK_O_ac97,
|
||||
SRDY_O => SRDY_O_ac97,
|
||||
MRDY_I => MRDY_O,
|
||||
ADDR_I => ADDR_O,
|
||||
DAT_I => MDAT_O,
|
||||
DAT_O => SDAT_O_ac97,
|
||||
INT_O => INT_O_ac97,
|
||||
|
||||
-- AC97 domain
|
||||
ac97_sdata_in => sys_ac97_sdata_in,
|
||||
ac97_bit_clk => sys_ac97_bit_clk,
|
||||
ac97_reset_n => ac97_rstn,
|
||||
ac97_sdata_out => sys_ac97_sdata_out,
|
||||
ac97_ssync => sys_ac97_ssync
|
||||
);
|
||||
|
||||
------------------------------------------------------------------
|
||||
END;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,173 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
ENTITY ram IS
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
we : in unsigned(3 downto 0);
|
||||
addr : in unsigned(31 downto 0);
|
||||
din : in unsigned(31 downto 0);
|
||||
dout : out unsigned(31 downto 0)
|
||||
);
|
||||
END ram;
|
||||
|
||||
ARCHITECTURE behavior OF ram IS
|
||||
|
||||
COMPONENT dpram_2w2r
|
||||
Generic
|
||||
(
|
||||
addr_width : integer;
|
||||
data_width : integer
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk_a : in STD_LOGIC;
|
||||
clk_b : in STD_LOGIC;
|
||||
en_a : in STD_LOGIC;
|
||||
en_b : in STD_LOGIC;
|
||||
we_a : in STD_LOGIC;
|
||||
we_b : in STD_LOGIC;
|
||||
addr_a : in unsigned (addr_width-1 downto 0);
|
||||
addr_b : in unsigned (addr_width-1 downto 0);
|
||||
din_a : in unsigned (data_width-1 downto 0);
|
||||
din_b : in unsigned (data_width-1 downto 0);
|
||||
dout_a : out unsigned (data_width-1 downto 0);
|
||||
dout_b : out unsigned (data_width-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
signal jtag_clk : STD_LOGIC;
|
||||
signal jtag_we : unsigned(3 downto 0);
|
||||
signal jtag_addr : unsigned (15 downto 0);
|
||||
signal jtag_dout : unsigned (31 downto 0);
|
||||
signal jtag_din : unsigned (31 downto 0);
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (47 downto 0);
|
||||
|
||||
BEGIN
|
||||
|
||||
gen_sram:
|
||||
for i in 0 to 3 generate
|
||||
begin
|
||||
inst_dpram_2w2r : dpram_2w2r
|
||||
GENERIC MAP
|
||||
(
|
||||
addr_width => 11,
|
||||
data_width => 8
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk_a => clk,
|
||||
en_a => ce,
|
||||
we_a => we(i),
|
||||
addr_a => addr(12 downto 2),
|
||||
din_a => din((i+1)*8-1 downto i*8),
|
||||
dout_a => dout((i+1)*8-1 downto i*8),
|
||||
|
||||
clk_b => jtag_clk,
|
||||
en_b => jtag_we(i),
|
||||
we_b => jtag_we(i),
|
||||
addr_b => jtag_addr(10 downto 0),
|
||||
din_b => jtag_din((i+1)*8-1 downto i*8),
|
||||
dout_b => jtag_dout((i+1)*8-1 downto i*8)
|
||||
);
|
||||
end generate;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_addr <= user_regi(user_regi'left downto jtag_dout'length);
|
||||
jtag_din <= user_regi(jtag_dout'length-1 downto 0);
|
||||
jtag_clk <= bs_update1;
|
||||
jtag_we <= (3 downto 0 => bs_sel);
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end behavior;
|
||||
@@ -1,88 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
|
||||
ENTITY ram IS
|
||||
Generic
|
||||
(
|
||||
word_addr_width : integer := 6
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
we : in unsigned(3 downto 0);
|
||||
addr : in unsigned(31 downto 0);
|
||||
din : in unsigned(31 downto 0);
|
||||
dout : out unsigned(31 downto 0)
|
||||
);
|
||||
END ram;
|
||||
|
||||
ARCHITECTURE behavior OF ram IS
|
||||
|
||||
constant depth : natural := 2**word_addr_width;
|
||||
|
||||
type sram_t is array (0 to depth-1) of unsigned(31 downto 0);
|
||||
|
||||
function sram_clear return sram_t is
|
||||
|
||||
variable result : sram_t;
|
||||
begin
|
||||
for i in 0 to sram_t'length-1 loop
|
||||
result(i) := (others => '0');
|
||||
end loop;
|
||||
return result;
|
||||
end sram_clear;
|
||||
|
||||
signal sram : sram_t := sram_clear;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
SRAM_RW:
|
||||
process(clk)
|
||||
variable index : natural range 0 to depth-1;
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
index := to_integer(addr(word_addr_width+1 downto 2));
|
||||
if we(0) = '1' then
|
||||
sram(index)(7 downto 0) <= din(7 downto 0);
|
||||
end if;
|
||||
if we(1) = '1' then
|
||||
sram(index)(15 downto 8) <= din(15 downto 8);
|
||||
end if;
|
||||
if we(2) = '1' then
|
||||
sram(index)(23 downto 16) <= din(23 downto 16);
|
||||
end if;
|
||||
if we(3) = '1' then
|
||||
sram(index)(31 downto 24) <= din(31 downto 24);
|
||||
end if;
|
||||
dout <= sram(index);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end behavior;
|
||||
@@ -1,74 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: User SDRAM component adjustments
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package sdram_config is
|
||||
|
||||
constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
|
||||
constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
|
||||
constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
|
||||
constant DDR_ROW_ADDR_WIDTH : positive := 13; --
|
||||
constant DDR_COL_ADDR_WIDTH : positive := 9; --
|
||||
|
||||
constant LMR_REG_BASE : natural := 0;
|
||||
constant LMR_REG_EXTENDED : natural := 1;
|
||||
constant LMR_OP_NORMAL : natural := 0;
|
||||
constant LMR_OP_RES_DLL : natural := 2;
|
||||
constant LMR_BT_SEQ : natural := 0;
|
||||
constant LMR_BT_ILVD : natural := 1;
|
||||
constant LMR_BL2 : natural := 1;
|
||||
constant LMR_BL4 : natural := 2;
|
||||
constant LMR_BL8 : natural := 3;
|
||||
constant LMR_CL2 : natural := 2;
|
||||
constant LMR_CL3 : natural := 3;
|
||||
constant LMR_CL2_5 : natural := 6;
|
||||
|
||||
-- DDR SDRAM Hardware defined constants
|
||||
constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
|
||||
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
|
||||
constant ENABLE_PRE_ALL : std_logic := '1';
|
||||
constant ENABLE_AUTO_PRE : std_logic := '0';
|
||||
|
||||
-- DDR-SDR TIMING constants ------------------------------------------------------------------
|
||||
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
|
||||
constant REFRESH_INTERVAL : real := 7.8125; -- us
|
||||
|
||||
-- These values are for your SDRAM part (see datasheet)
|
||||
constant TCAS : positive := 2; -- CAS latency [clocks]
|
||||
constant TRP : positive := 2; -- precharge command period
|
||||
constant TRAS : positive := 5; -- active to precharge delay
|
||||
constant TRFC : positive := 8; -- auto refresh command period
|
||||
constant TMRD : positive := 2; -- load mode register command cylce time
|
||||
constant TRCD : positive := 2; -- active to read or write delay !
|
||||
constant TWR : positive := 2; -- write recovery time
|
||||
|
||||
constant PWR_UP_WAIT : natural := 222; -- µs
|
||||
|
||||
subtype user_tag_t is unsigned(3 downto 0);
|
||||
|
||||
----------------------------------------------------------------------------------------------
|
||||
|
||||
end sdram_config;
|
||||
@@ -1,74 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: User SDRAM component adjustments
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package sdram_config is
|
||||
|
||||
constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
|
||||
constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
|
||||
constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
|
||||
constant DDR_ROW_ADDR_WIDTH : positive := 13; --
|
||||
constant DDR_COL_ADDR_WIDTH : positive := 9; --
|
||||
|
||||
constant LMR_REG_BASE : natural := 0;
|
||||
constant LMR_REG_EXTENDED : natural := 1;
|
||||
constant LMR_OP_NORMAL : natural := 0;
|
||||
constant LMR_OP_RES_DLL : natural := 2;
|
||||
constant LMR_BT_SEQ : natural := 0;
|
||||
constant LMR_BT_ILVD : natural := 1;
|
||||
constant LMR_BL2 : natural := 1;
|
||||
constant LMR_BL4 : natural := 2;
|
||||
constant LMR_BL8 : natural := 3;
|
||||
constant LMR_CL2 : natural := 2;
|
||||
constant LMR_CL3 : natural := 3;
|
||||
constant LMR_CL2_5 : natural := 6;
|
||||
|
||||
-- DDR SDRAM Hardware defined constants
|
||||
constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
|
||||
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
|
||||
constant ENABLE_PRE_ALL : std_logic := '1';
|
||||
constant ENABLE_AUTO_PRE : std_logic := '0';
|
||||
|
||||
-- DDR-SDR TIMING constants ------------------------------------------------------------------
|
||||
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
|
||||
constant REFRESH_INTERVAL : real := 7.8125; -- us
|
||||
|
||||
-- These values are for your SDRAM part (see datasheet)
|
||||
constant TCAS : positive := 2; -- CAS latency [clocks]
|
||||
constant TRP : positive := 2; -- precharge command period
|
||||
constant TRAS : positive := 5; -- active to precharge delay
|
||||
constant TRFC : positive := 8; -- auto refresh command period
|
||||
constant TMRD : positive := 2; -- load mode register command cylce time
|
||||
constant TRCD : positive := 2; -- active to read or write delay !
|
||||
constant TWR : positive := 2; -- write recovery time
|
||||
|
||||
constant PWR_UP_WAIT : natural := 22; -- µs
|
||||
|
||||
subtype user_tag_t is unsigned(3 downto 0);
|
||||
|
||||
----------------------------------------------------------------------------------------------
|
||||
|
||||
end sdram_config;
|
||||
@@ -1,62 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: MIPS System controller
|
||||
-- This file:
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
use work.async_types.all;
|
||||
|
||||
package async_defs is
|
||||
|
||||
constant ts_flash : async_timespec_t :=
|
||||
(
|
||||
ncyc_access => 1,
|
||||
ncyc_pulse_rd => 12,
|
||||
ncyc_pulse_wr => 7,
|
||||
ncyc_cs_hold => 1,
|
||||
ncyc_release => 1,
|
||||
ncyc_pulse_rst => 8,
|
||||
pol_cs => '1',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_rst => '0'
|
||||
);
|
||||
|
||||
constant ts_usb : async_timespec_t :=
|
||||
(
|
||||
ncyc_access => 1,
|
||||
ncyc_pulse_rd => 6,
|
||||
ncyc_pulse_wr => 6,
|
||||
ncyc_cs_hold => 1,
|
||||
ncyc_release => 6,
|
||||
ncyc_pulse_rst => 8,
|
||||
pol_cs => '0',
|
||||
pol_oe => '0',
|
||||
pol_we => '0',
|
||||
pol_rst => '0'
|
||||
);
|
||||
|
||||
----------------------------------------------------------------------------------------------
|
||||
|
||||
end async_defs;
|
||||
@@ -1,339 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.mips_types.all;
|
||||
use work.sdram_config.all;
|
||||
use work.sdram_types.all;
|
||||
|
||||
ENTITY tb_mips_sys IS
|
||||
END tb_mips_sys;
|
||||
|
||||
ARCHITECTURE behavior OF tb_mips_sys IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
constant AC97_CLK_PERIOD : time := 83 ns;
|
||||
signal sys_rst_n_in : std_logic := '0';
|
||||
signal sys_clk_in : std_logic := '1';
|
||||
signal dip : unsigned(7 downto 0) := (others => '0');
|
||||
signal btn : unsigned(4 downto 0) := (others => '0');
|
||||
signal led : unsigned(8 downto 0);
|
||||
signal sys_rx : std_logic := '1';
|
||||
signal sys_tx : std_logic;
|
||||
|
||||
signal sys_lcd_d : unsigned(3 downto 0);
|
||||
signal sys_lcd_e : std_logic;
|
||||
signal sys_lcd_rs : std_logic;
|
||||
signal sys_lcd_rw : std_logic;
|
||||
|
||||
signal refresh : boolean:= true;
|
||||
|
||||
signal sys_sdr_clk_p : std_logic; -- ddr_sdram_clock
|
||||
signal sys_sdr_clk_n : std_logic; -- /ddr_sdram_clock
|
||||
signal sys_sdr_cke_q : std_logic; -- clock enable
|
||||
signal sys_sdr_cs_qn : std_logic; -- /chip select
|
||||
signal sys_sdr_ras_qn : std_logic; -- /ras
|
||||
signal sys_sdr_cas_qn : std_logic; -- /cas
|
||||
signal sys_sdr_we_qn : std_logic; -- /write enable
|
||||
signal sys_sdr_dm_q : unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00"
|
||||
signal sys_sdr_dqs_q : unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write
|
||||
signal sys_sdr_ba_q : unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select
|
||||
signal sys_sdr_a_q : unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus
|
||||
signal sys_sdr_data : unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
|
||||
|
||||
signal sys_error : unsigned(1 downto 0); -- indicates DCM Errors
|
||||
signal sys_sdr_clk_fb : std_logic;
|
||||
|
||||
signal sys_usb_d : unsigned(15 downto 0) := (others => '0');
|
||||
signal sys_usb_a : unsigned(1 downto 0);
|
||||
signal sys_usb_csn : std_logic;
|
||||
signal sys_usb_wrn : std_logic;
|
||||
signal sys_usb_rdn : std_logic;
|
||||
signal sys_usb_rstn : std_logic;
|
||||
signal sys_usb_int : std_logic := '0';
|
||||
|
||||
signal sys_flash_ssram_d : word_t;
|
||||
signal sys_flash_ssram_a : unsigned(24 downto 0);
|
||||
signal sys_flash_ssram_we_n : std_logic;
|
||||
signal sys_flash_ssram_oe_n : std_logic;
|
||||
|
||||
signal sys_flash_ce : std_logic;
|
||||
signal sys_flash_ac97_rstn : std_logic;
|
||||
signal sys_flash_byten : std_logic;
|
||||
|
||||
signal sys_ssram_clk_fb : std_logic;
|
||||
signal sys_ssram_clk : std_logic;
|
||||
signal sys_ssram_cke_n : std_logic;
|
||||
signal sys_ssram_ce_n : std_logic;
|
||||
signal sys_ssram_bw_n : unsigned(3 downto 0);
|
||||
signal sys_ssram_dp : unsigned(3 downto 0);
|
||||
signal sys_ssram_adv : std_logic;
|
||||
signal sys_ssram_mode : std_logic;
|
||||
signal sys_ssram_zz : std_logic;
|
||||
|
||||
SIGNAL sys_ac97_bit_clk : std_logic := '0';
|
||||
SIGNAL sys_ac97_sdata_out : std_logic;
|
||||
SIGNAL sys_ac97_ssync : std_logic;
|
||||
SIGNAL sys_ac97_sdata_in : std_logic;
|
||||
|
||||
signal flash_reg : word_t;
|
||||
|
||||
type flash_data_t is array (natural range 0 to 2**16-1) of word_t;
|
||||
signal flash_data : flash_data_t;
|
||||
|
||||
signal ac_frame_reg : unsigned(255 downto 0) := (others => '0');
|
||||
signal ac_left : unsigned(17 downto 0) := X"0000" & "00";
|
||||
signal ac_right : unsigned(17 downto 0) := X"0000" & "01";
|
||||
signal ac_synced : std_logic;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: entity work.mips_sys
|
||||
-- GENERIC MAP
|
||||
-- (
|
||||
-- ddr_phaseshift => 90,
|
||||
-- ddr_frequency_hz => 100E6
|
||||
-- )
|
||||
PORT MAP
|
||||
(
|
||||
sys_rst_n_in => sys_rst_n_in,
|
||||
sys_clk_in => sys_clk_in,
|
||||
sys_btn => btn,
|
||||
sys_dip => dip,
|
||||
sys_led => led,
|
||||
|
||||
sys_rx => sys_rx,
|
||||
sys_tx => sys_tx,
|
||||
|
||||
sys_lcd_d => sys_lcd_d,
|
||||
sys_lcd_e => sys_lcd_e,
|
||||
sys_lcd_rs => sys_lcd_rs,
|
||||
sys_lcd_rw => sys_lcd_rw,
|
||||
|
||||
sys_sdr_clk_p => sys_sdr_clk_p,
|
||||
sys_sdr_clk_n => sys_sdr_clk_n,
|
||||
sys_sdr_cke_q => sys_sdr_cke_q,
|
||||
sys_sdr_clk_fb => sys_sdr_clk_fb,
|
||||
sys_sdr_cs_qn => sys_sdr_cs_qn,
|
||||
sys_sdr_ras_qn => sys_sdr_ras_qn,
|
||||
sys_sdr_cas_qn => sys_sdr_cas_qn,
|
||||
sys_sdr_we_qn => sys_sdr_we_qn,
|
||||
sys_sdr_dm_q => sys_sdr_dm_q,
|
||||
sys_sdr_dqs_q => sys_sdr_dqs_q,
|
||||
sys_sdr_ba_q => sys_sdr_ba_q,
|
||||
sys_sdr_a_q => sys_sdr_a_q,
|
||||
sys_sdr_data => sys_sdr_data,
|
||||
|
||||
sys_usb_d => sys_usb_d,
|
||||
sys_usb_a => sys_usb_a,
|
||||
sys_usb_csn => sys_usb_csn,
|
||||
sys_usb_wrn => sys_usb_wrn,
|
||||
sys_usb_rdn => sys_usb_rdn,
|
||||
sys_usb_rstn => sys_usb_rstn,
|
||||
sys_usb_int => sys_usb_int,
|
||||
|
||||
sys_flash_ssram_d => sys_flash_ssram_d,
|
||||
sys_flash_ssram_a => sys_flash_ssram_a,
|
||||
sys_flash_ssram_we_n => sys_flash_ssram_we_n,
|
||||
sys_flash_ssram_oe_n => sys_flash_ssram_oe_n,
|
||||
sys_flash_ce => sys_flash_ce,
|
||||
sys_flash_ac97_rstn => sys_flash_ac97_rstn,
|
||||
sys_flash_byten => sys_flash_byten,
|
||||
|
||||
sys_ssram_clk_fb => sys_ssram_clk_fb,
|
||||
sys_ssram_clk => sys_ssram_clk,
|
||||
sys_ssram_cke_n => sys_ssram_cke_n,
|
||||
sys_ssram_ce_n => sys_ssram_ce_n,
|
||||
sys_ssram_bw_n => sys_ssram_bw_n,
|
||||
sys_ssram_dp => sys_ssram_dp,
|
||||
sys_ssram_adv => sys_ssram_adv,
|
||||
sys_ssram_mode => sys_ssram_mode,
|
||||
sys_ssram_zz => sys_ssram_zz,
|
||||
|
||||
sys_ac97_bit_clk => sys_ac97_bit_clk,
|
||||
sys_ac97_sdata_out => sys_ac97_sdata_out,
|
||||
sys_ac97_ssync => sys_ac97_ssync,
|
||||
sys_ac97_sdata_in => sys_ac97_sdata_in,
|
||||
|
||||
sys_error => sys_error
|
||||
);
|
||||
|
||||
inst_ssram : entity work.cy7c1354
|
||||
PORT MAP
|
||||
(
|
||||
Dq => STD_LOGIC_VECTOR(sys_flash_ssram_d), -- Data I/O
|
||||
Dpq => STD_LOGIC_VECTOR(sys_ssram_dp), -- Data I/O
|
||||
Addr => STD_LOGIC_VECTOR(sys_flash_ssram_a(18 downto 1)), -- Address
|
||||
Mode => sys_ssram_mode, -- Burst Mode
|
||||
Clk => sys_ssram_clk, -- Clk
|
||||
CEN_n => sys_ssram_cke_n, -- CEN#
|
||||
AdvLd_n => sys_ssram_adv, -- Adv/Ld#
|
||||
Bwa_n => sys_ssram_bw_n(0), -- Bwa#
|
||||
Bwb_n => sys_ssram_bw_n(1), -- BWb#
|
||||
Bwc_n => sys_ssram_bw_n(2), -- Bwc#
|
||||
Bwd_n => sys_ssram_bw_n(3), -- BWd#
|
||||
Rw_n => sys_flash_ssram_we_n, -- RW#
|
||||
Oe_n => sys_flash_ssram_oe_n, -- OE#
|
||||
Ce1_n => sys_ssram_ce_n, -- CE1#
|
||||
Ce2 => '1', -- CE2
|
||||
Ce3_n => '0', -- CE3#
|
||||
Zz => sys_ssram_zz
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(sys_sdr_data(15 downto 0)),
|
||||
dqs => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
|
||||
addr => std_logic_vector(sys_sdr_a_q),
|
||||
ba => std_logic_vector(sys_sdr_ba_q),
|
||||
clk => sys_sdr_clk_p,
|
||||
clk_n => sys_sdr_clk_n,
|
||||
cke => sys_sdr_cke_q,
|
||||
cs_n => sys_sdr_cs_qn,
|
||||
ras_n => sys_sdr_ras_qn,
|
||||
cas_n => sys_sdr_cas_qn,
|
||||
we_n => sys_sdr_we_qn,
|
||||
dm => std_logic_vector(sys_sdr_dm_q(1 downto 0))
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_1 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(sys_sdr_data(31 downto 16)),
|
||||
dqs => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
|
||||
addr => std_logic_vector(sys_sdr_a_q),
|
||||
ba => std_logic_vector(sys_sdr_ba_q),
|
||||
clk => sys_sdr_clk_p,
|
||||
clk_n => sys_sdr_clk_n,
|
||||
cke => sys_sdr_cke_q,
|
||||
cs_n => sys_sdr_cs_qn,
|
||||
ras_n => sys_sdr_ras_qn,
|
||||
cas_n => sys_sdr_cas_qn,
|
||||
we_n => sys_sdr_we_qn,
|
||||
dm => std_logic_vector(sys_sdr_dm_q(3 downto 2))
|
||||
);
|
||||
|
||||
sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps;
|
||||
sys_ssram_clk_fb <= sys_ssram_clk after 0.5 ns;
|
||||
|
||||
refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
|
||||
|
||||
sys_usb_d <= X"1234" after 20 ns when sys_usb_csn = '0' and sys_usb_rdn = '0' else (others => 'Z') after 5 ns;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
sys_clk_in <= not sys_clk_in;
|
||||
end process;
|
||||
|
||||
|
||||
sys_ac97_sdata_in <= ac_frame_reg(ac_frame_reg'left); --sys_ac97_sdata_out;
|
||||
|
||||
ac97_data_gen :
|
||||
PROCESS(sys_ac97_bit_clk)
|
||||
begin
|
||||
if rising_edge(sys_ac97_bit_clk) then
|
||||
ac_frame_reg <= ac_frame_reg(ac_frame_reg'left-1 downto 0) & '0';
|
||||
if sys_flash_ac97_rstn = '0' then
|
||||
ac_synced <= '0';
|
||||
elsif sys_ac97_ssync = '1' then
|
||||
if ac_synced = '0' then
|
||||
ac_frame_reg <= X"F800_00000_00000" & ac_left & "00" & ac_right & "00" & X"00000_00000_00000_00000_00000_00000_00000_00000";
|
||||
ac_left <= ac_left + 2;
|
||||
ac_right <= ac_right + 2;
|
||||
ac_synced <= '1';
|
||||
end if;
|
||||
else
|
||||
ac_synced <= '0';
|
||||
end if;
|
||||
end if;
|
||||
END PROCESS;
|
||||
|
||||
ac97_clk_gen : PROCESS
|
||||
begin
|
||||
if (sys_flash_ac97_rstn = '0') then
|
||||
sys_ac97_bit_clk <= '0';
|
||||
wait until sys_flash_ac97_rstn = '1';
|
||||
wait for 150 us;
|
||||
end if;
|
||||
wait for AC97_CLK_PERIOD/2;
|
||||
sys_ac97_bit_clk <= not sys_ac97_bit_clk;
|
||||
END PROCESS;
|
||||
|
||||
FLASH_READ: process(sys_rst_n_in, sys_flash_ce, sys_flash_ssram_oe_n, sys_flash_ssram_a)
|
||||
type file_t is file of integer;
|
||||
file load_flash : file_t open read_mode is "test_ac97.flash.bin";
|
||||
variable instr : integer;
|
||||
variable index : natural;
|
||||
variable temp : signed(31 downto 0);
|
||||
begin
|
||||
if sys_rst_n_in = '0' then
|
||||
index := 0;
|
||||
while not endfile(load_flash) loop
|
||||
read(load_flash, instr);
|
||||
temp := to_signed(instr, word_t'length);
|
||||
flash_data(index) <= unsigned(temp);
|
||||
index := index + 1;
|
||||
end loop;
|
||||
else
|
||||
sys_flash_ssram_d <= (others => 'Z') after 10 ns;
|
||||
if sys_flash_ssram_oe_n = '0' and sys_flash_ce = '1' then
|
||||
index := to_integer(sys_flash_ssram_a(24 downto 1));
|
||||
sys_flash_ssram_d <= flash_data(index) after 10 ns;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
FLASH_WRITE: process(sys_flash_ce, sys_flash_ssram_we_n, sys_flash_ssram_d)
|
||||
begin
|
||||
if rising_edge(sys_flash_ssram_we_n) and sys_flash_ce = '1' then
|
||||
flash_reg <= sys_flash_ssram_d;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
sys_rst_n_in <= '1';
|
||||
wait for 200000*CLK_PERIOD;
|
||||
|
||||
loop
|
||||
wait for 251*CLK_PERIOD;
|
||||
btn(4) <= '1';
|
||||
wait for 311*CLK_PERIOD;
|
||||
btn(4) <= '0';
|
||||
end loop;
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -1,46 +0,0 @@
|
||||
#!/usr/bin/env ruby
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
# This file: Insertion of code fragments into templates
|
||||
#
|
||||
# Copyright (C) 2008 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
arg = $*
|
||||
rom_filename = arg[0].to_s
|
||||
tpl_filename = arg[1].to_s
|
||||
|
||||
subst_pattern = "ROM_INSERT_HERE"
|
||||
|
||||
# --------------------------------------------------------
|
||||
# Open file
|
||||
# --------------------------------------------------------
|
||||
romfile = File.open(rom_filename, "r")
|
||||
tplfile = File.open(tpl_filename, "r")
|
||||
re = Regexp.new(subst_pattern)
|
||||
|
||||
while (line = tplfile.gets)
|
||||
puts line
|
||||
line.scan(re).each do |word|
|
||||
romfile.each do |raw_line|
|
||||
puts raw_line
|
||||
end
|
||||
end
|
||||
end
|
||||
@@ -1,29 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
-- ROM_INSERT_HERE
|
||||
|
||||
@@ -1,147 +0,0 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2008 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE loadable OF irom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : unsigned (15 downto 0);
|
||||
signal jtag_ld_dout : unsigned (31 downto 0);
|
||||
signal jtag_ld_din : unsigned (31 downto 0);
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (47 downto 0);
|
||||
constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
|
||||
jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -1,50 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: rom-file generation for cpu_core
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
TARGET=$2
|
||||
DSTDIR=$1
|
||||
|
||||
JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools
|
||||
|
||||
$JASM_HOME/jasm.rb $TARGET.jsm
|
||||
|
||||
irom_tcl_snippet="$TARGET.irom.tcl.snip"
|
||||
irom_vhdl_snippet="$TARGET.irom.vhdl.snip"
|
||||
irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip"
|
||||
xrom_tcl_snippet="$TARGET.xrom.tcl.snip"
|
||||
xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip"
|
||||
xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip"
|
||||
|
||||
$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl
|
||||
$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl
|
||||
|
||||
$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl
|
||||
$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl
|
||||
|
||||
cat $irom_tcl_snippet > $TARGET.tcl.snip.snip
|
||||
cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip
|
||||
$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl
|
||||
|
||||
rm -f *.snip
|
||||
@@ -1,61 +0,0 @@
|
||||
# ----------------------------------------------------------------------
|
||||
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
# This file: The ROM file for upload to target over JTAG
|
||||
#
|
||||
# Copyright (C) 2007 J. Ahrensfeld
|
||||
#
|
||||
# This program is free software: you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation, either version 3 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
#
|
||||
# For questions and ideas, please contact the author at jens@jayfield.org
|
||||
#
|
||||
# ---------------------------------------------------------------------
|
||||
|
||||
# ---------------------------------------------------------------------
|
||||
# For Chipscope 9.1
|
||||
# ---------------------------------------------------------------------
|
||||
# Source JTAG/TCL frame work
|
||||
cd $env(CHIPSCOPE)\\bin\\nt
|
||||
source csejtag.tcl
|
||||
|
||||
namespace import ::chipscope::*
|
||||
|
||||
# Platform USB Cable
|
||||
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"]
|
||||
# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"
|
||||
|
||||
# Create session
|
||||
set handle [::chipscope::csejtag_session create 0]
|
||||
|
||||
# Open JTAG and lock
|
||||
set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]
|
||||
set lock_result [::chipscope::csejtag_target lock $handle 1000]
|
||||
|
||||
set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]
|
||||
|
||||
# Get Device ID
|
||||
set devtype "Virtex-4SX"
|
||||
set devid 2
|
||||
set irlength [::chipscope::csejtag_tap get_irlength $handle $devid]
|
||||
set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]
|
||||
|
||||
set CSE_OP $CSEJTAG_SHIFT_READWRITE
|
||||
set CSE_ES $CSEJTAG_RUN_TEST_IDLE
|
||||
|
||||
# Write Program
|
||||
# JASM_ROM_INSERT_HERE
|
||||
|
||||
::chipscope::csejtag_target unlock $handle
|
||||
::chipscope::csejtag_target close $handle
|
||||
::chipscope::csejtag_session destroy $handle
|
||||
exit
|
||||
@@ -1,117 +0,0 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
#define INT8 char
|
||||
#define INT16 short
|
||||
#define INT32 long
|
||||
#define UINT8 unsigned char
|
||||
#define UINT16 unsigned short
|
||||
#define UINT32 unsigned long
|
||||
#define INT int
|
||||
#define UINT unsigned int
|
||||
#define FLOAT32 float
|
||||
#define FLOAT64 double
|
||||
|
||||
#define SDRAM_BASE 0x40000000
|
||||
#define FLASH_OFFSET 0x00000000
|
||||
|
||||
// --------------------------------------------------------------
|
||||
typedef struct _sflash_img_hdr_t
|
||||
{
|
||||
UINT8 magic[4];
|
||||
UINT32 target_addr;
|
||||
UINT32 img_offset;
|
||||
UINT32 img_size;
|
||||
UINT32 hdr_next;
|
||||
UINT8 img_name[128];
|
||||
UINT8 res[108];
|
||||
|
||||
} flash_img_hdr_t;
|
||||
|
||||
// --------------------------------------------------------------
|
||||
void basename(char *pSrc, char *pDst)
|
||||
{
|
||||
int i, size;
|
||||
|
||||
size = strlen(pSrc);
|
||||
|
||||
while(pSrc[size] != '.')
|
||||
size--;
|
||||
|
||||
for (i=0; i < size; i++)
|
||||
pDst[i] = pSrc[i];
|
||||
|
||||
pDst[i] = 0;
|
||||
|
||||
}
|
||||
|
||||
// --------------------------------------------------------------
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
char *pFilenameIn;
|
||||
char name_flash[1024];
|
||||
char name_prj[1024];
|
||||
char *pBuf;
|
||||
flash_img_hdr_t img_hdr = {0};
|
||||
|
||||
FILE *pFile;
|
||||
int filesize;
|
||||
long start, end;
|
||||
int i;
|
||||
|
||||
if (argc < 2)
|
||||
{
|
||||
fprintf(stderr, "Usage: flashgen <input file>\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFilenameIn = argv[1];
|
||||
pFile = fopen(pFilenameIn, "rb");
|
||||
if (!pFile)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
basename(pFilenameIn, name_prj);
|
||||
sprintf(name_flash, "%s.flash.bin", name_prj);
|
||||
|
||||
// determine filesize
|
||||
fseek(pFile, 0, SEEK_SET);
|
||||
start = ftell(pFile);
|
||||
fseek(pFile, 0, SEEK_END);
|
||||
end = ftell(pFile);
|
||||
fseek(pFile, 0, SEEK_SET);
|
||||
filesize = (end-start);
|
||||
|
||||
pBuf = (char*)malloc(filesize);
|
||||
fread(pBuf, 1, filesize, pFile);
|
||||
|
||||
fclose(pFile);
|
||||
|
||||
pFile = fopen(name_flash, "wb");
|
||||
if (!pFile)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", name_flash);
|
||||
return 1;
|
||||
}
|
||||
|
||||
img_hdr.magic[0] = 'J';
|
||||
img_hdr.magic[1] = 'F';
|
||||
img_hdr.magic[2] = 'I';
|
||||
img_hdr.magic[3] = '1';
|
||||
img_hdr.target_addr = SDRAM_BASE;
|
||||
img_hdr.img_size = filesize;
|
||||
img_hdr.img_offset = FLASH_OFFSET + sizeof(flash_img_hdr_t);
|
||||
img_hdr.hdr_next = FLASH_OFFSET;
|
||||
|
||||
fwrite(&img_hdr, sizeof(flash_img_hdr_t), 1, pFile);
|
||||
fwrite(pBuf, 1, filesize, pFile);
|
||||
|
||||
fclose(pFile);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,385 +0,0 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
#define ARCH_NAME "data"
|
||||
#define ENT_NAME "ram"
|
||||
#define JTAG_ADDR_WIDTH 16
|
||||
|
||||
// --------------------------------------------------------------
|
||||
void basename(char *pSrc, char *pDst)
|
||||
{
|
||||
int i, size;
|
||||
|
||||
size = strlen(pSrc);
|
||||
|
||||
while(pSrc[size] != '.')
|
||||
size--;
|
||||
|
||||
for (i=0; i < size; i++)
|
||||
pDst[i] = pSrc[i];
|
||||
|
||||
pDst[i] = 0;
|
||||
|
||||
}
|
||||
|
||||
int SaveRAM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, filesize, romsize;
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "LIBRARY IEEE;\n");
|
||||
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
|
||||
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\tPort\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\twe\t\t: in unsigned(%d downto 0);\n", nbits_data/8-1);
|
||||
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t\tdin\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "END %s;\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
|
||||
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tconstant depth : natural := %d;\n", romsize/4);
|
||||
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
|
||||
|
||||
fprintf(pFileOut, "\tsignal sram : word_array_t :=\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
word = 0;
|
||||
for (; i < romsize; i += sizeof(int))
|
||||
{
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "begin\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "RAM_RW:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(clk)\n");
|
||||
fprintf(pFileOut, "\tvariable index : natural range 0 to depth-1;\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\tindex := to_integer(addr(%d downto 2));\n", nbits_addr+1);
|
||||
fprintf(pFileOut, "\t\t\tif we(0) = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tsram(index)(7 downto 0)\t\t<= din(7 downto 0);\n");
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\t\tif we(1) = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tsram(index)(15 downto 8)\t<= din(15 downto 8);\n");
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\t\tif we(2) = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tsram(index)(23 downto 16)\t<= din(23 downto 16);\n");
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\t\tif we(3) = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tsram(index)(31 downto 24)\t\t<= din(31 downto 24);\n");
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\t\tdout <= sram(index);\n");
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int SaveRAM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, filesize, romsize;
|
||||
|
||||
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "LIBRARY IEEE;\n");
|
||||
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
|
||||
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "library UNISIM;\n");
|
||||
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\tPort\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "END %s;\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
|
||||
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
|
||||
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
|
||||
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
|
||||
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
word = 0;
|
||||
for (; i < romsize; i += sizeof(int))
|
||||
{
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "begin\n", ARCH_NAME);
|
||||
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(clk)\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "\n");
|
||||
fputs(tpl, pFileOut);
|
||||
|
||||
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
|
||||
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
|
||||
fprintf(pFileOut, "\t\t\telse\n");
|
||||
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, word_addr, filesize, romsize;
|
||||
char binstr_addr[33];
|
||||
char binstr_data[33];
|
||||
|
||||
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fputs(tpl, pFileOut);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
|
||||
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
|
||||
fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n");
|
||||
fprintf(pFileOut, "# User 2\n");
|
||||
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n");
|
||||
|
||||
word_addr = 0;
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
|
||||
word_addr++;
|
||||
}
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
|
||||
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
|
||||
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
|
||||
fprintf(pFileOut, "exit\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
char *pFilenameIn;
|
||||
char name_prj[1024];
|
||||
char name_rom_tcl[1024];
|
||||
char name_rom[1024];
|
||||
char name_rom_v4ld[1024];
|
||||
|
||||
FILE *pFileIn;
|
||||
int filesize, romsize, nbits_addr, nbits_data;
|
||||
long start, end;
|
||||
int word, i;
|
||||
|
||||
if (argc < 2)
|
||||
{
|
||||
fprintf(stderr, "Usage: ramgen <input file> <num. word address bits>\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFilenameIn = argv[1];
|
||||
if (argc == 3)
|
||||
nbits_addr = atoi(argv[2]);
|
||||
|
||||
|
||||
basename(pFilenameIn, name_prj);
|
||||
sprintf(name_rom, "%s.vhd", name_prj);
|
||||
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
|
||||
sprintf(name_rom_tcl, "%s.tcl", name_prj);
|
||||
|
||||
SaveRAM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
// SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,368 +0,0 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
|
||||
#define ARCH_NAME "data"
|
||||
#define ENT_NAME "rom"
|
||||
#define JTAG_ADDR_WIDTH 16
|
||||
|
||||
// --------------------------------------------------------------
|
||||
void basename(char *pSrc, char *pDst)
|
||||
{
|
||||
int i, size;
|
||||
|
||||
size = strlen(pSrc);
|
||||
|
||||
while(pSrc[size] != '.')
|
||||
size--;
|
||||
|
||||
for (i=0; i < size; i++)
|
||||
pDst[i] = pSrc[i];
|
||||
|
||||
pDst[i] = 0;
|
||||
|
||||
}
|
||||
|
||||
int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, filesize, romsize;
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "LIBRARY IEEE;\n");
|
||||
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
|
||||
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\tPort\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "END %s;\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
|
||||
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
|
||||
|
||||
fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
word = 0;
|
||||
for (; i < romsize; i += sizeof(int))
|
||||
{
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "begin\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(clk)\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, filesize, romsize;
|
||||
|
||||
char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"};
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "LIBRARY IEEE;\n");
|
||||
fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n");
|
||||
fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "library UNISIM;\n");
|
||||
fprintf(pFileOut, "use UNISIM.VComponents.all;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\tPort\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "END %s;\n", ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
|
||||
fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1);
|
||||
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n");
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1);
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1);
|
||||
fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n");
|
||||
fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n");
|
||||
fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH);
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n");
|
||||
fprintf(pFileOut, "\t(\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
word = 0;
|
||||
for (; i < romsize; i += sizeof(int))
|
||||
{
|
||||
fprintf(pFileOut, "\t\tX\"%8.8X\"", word);
|
||||
if (i < (romsize-sizeof(int)))
|
||||
fprintf(pFileOut, ", -- %8.8X\n", i);
|
||||
else
|
||||
fprintf(pFileOut, " -- %8.8X\n", i);
|
||||
}
|
||||
fprintf(pFileOut, "\t);\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "begin\n", ARCH_NAME);
|
||||
|
||||
fprintf(pFileOut, "\n");
|
||||
fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(clk)\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1);
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "\n");
|
||||
fputs(tpl, pFileOut);
|
||||
|
||||
fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME);
|
||||
fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n");
|
||||
fprintf(pFileOut, "\tbegin\n");
|
||||
fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n");
|
||||
fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n");
|
||||
fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1);
|
||||
fprintf(pFileOut, "\t\t\telse\n");
|
||||
fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1);
|
||||
fprintf(pFileOut, "\t\t\tend if;\n");
|
||||
fprintf(pFileOut, "\t\tend if;\n");
|
||||
fprintf(pFileOut, "\tend process;\n");
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
fprintf(pFileOut, "end %s;\n", ARCH_NAME);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data)
|
||||
{
|
||||
FILE *pFileIn, *pFileOut;
|
||||
long start, end;
|
||||
int i, word, word_addr, filesize, romsize;
|
||||
char binstr_addr[33];
|
||||
char binstr_data[33];
|
||||
|
||||
char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"};
|
||||
|
||||
pFileIn = fopen(pFilenameIn, "rb");
|
||||
if (!pFileIn)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameIn);
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFileOut = fopen(pFilenameOut, "wb");
|
||||
if (!pFileOut)
|
||||
{
|
||||
fprintf(stderr, "Error opening file %s\n", pFilenameOut);
|
||||
return 1;
|
||||
}
|
||||
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
start = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_END);
|
||||
end = ftell(pFileIn);
|
||||
fseek(pFileIn, 0, SEEK_SET);
|
||||
|
||||
filesize = (end-start);
|
||||
romsize = (int)pow(2, nbits_addr+2);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Header
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
fputs(tpl, pFileOut);
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// ROM part
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn);
|
||||
fprintf(pFileOut, "# ---------------------------------------------------------------\n");
|
||||
fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n");
|
||||
fprintf(pFileOut, "# User 1\n");
|
||||
fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n");
|
||||
|
||||
word_addr = 0;
|
||||
for (i=0; i < filesize; i += sizeof(int))
|
||||
{
|
||||
fread(&word, 1, sizeof(int), pFileIn);
|
||||
fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word);
|
||||
word_addr++;
|
||||
}
|
||||
fprintf(pFileOut, "\n");
|
||||
|
||||
// -------------------------------------------------------------------------
|
||||
// Trailer
|
||||
// -------------------------------------------------------------------------
|
||||
fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n");
|
||||
fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n");
|
||||
fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n");
|
||||
fprintf(pFileOut, "exit\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
char *pFilenameIn;
|
||||
char name_prj[1024];
|
||||
char name_rom[1024];
|
||||
char name_rom_v4ld[1024];
|
||||
char name_rom_tcl[1024];
|
||||
|
||||
FILE *pFileIn;
|
||||
int filesize, romsize, nbits_addr, nbits_data;
|
||||
long start, end;
|
||||
int word, i;
|
||||
|
||||
if (argc < 2)
|
||||
{
|
||||
fprintf(stderr, "Usage: romgen <input file> <num. word address bits>\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
pFilenameIn = argv[1];
|
||||
if (argc == 3)
|
||||
nbits_addr = atoi(argv[2]);
|
||||
|
||||
|
||||
basename(pFilenameIn, name_prj);
|
||||
sprintf(name_rom, "%s.vhd", name_prj);
|
||||
sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj);
|
||||
sprintf(name_rom_tcl, "%s.tcl", name_prj);
|
||||
|
||||
SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user