148 lines
4.2 KiB
Smarty
148 lines
4.2 KiB
Smarty
-------------------------------------------------------------------------
|
|
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
|
|
-- This file: loadable ROM
|
|
--
|
|
-- Copyright (C) 2008 J. Ahrensfeld
|
|
--
|
|
-- This program is free software: you can redistribute it and/or modify
|
|
-- it under the terms of the GNU General Public License as published by
|
|
-- the Free Software Foundation, either version 3 of the License, or
|
|
-- (at your option) any later version.
|
|
--
|
|
-- This program is distributed in the hope that it will be useful,
|
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
-- GNU General Public License for more details.
|
|
--
|
|
-- You should have received a copy of the GNU General Public License
|
|
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
--
|
|
-- For questions and ideas, please contact the author at jens@jayfield.org
|
|
--
|
|
--------------------------------------------------------------------------
|
|
|
|
LIBRARY ieee;
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
USE ieee.numeric_std.ALL;
|
|
|
|
library UNISIM;
|
|
use UNISIM.VComponents.all;
|
|
|
|
ENTITY irom IS
|
|
Port (
|
|
clk : in STD_LOGIC;
|
|
addr : in inst_addr_t;
|
|
dout : out inst_t
|
|
);
|
|
|
|
END irom;
|
|
|
|
ARCHITECTURE loadable OF irom IS
|
|
|
|
-- JASM_ROM_INSERT_HERE
|
|
|
|
signal jtag_ld_clk : STD_LOGIC;
|
|
signal jtag_ld_we : STD_LOGIC;
|
|
signal jtag_ld_addr : unsigned (15 downto 0);
|
|
signal jtag_ld_dout : unsigned (31 downto 0);
|
|
signal jtag_ld_din : unsigned (31 downto 0);
|
|
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
|
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
|
signal user_regi, user_rego : unsigned (47 downto 0);
|
|
constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE";
|
|
|
|
begin
|
|
|
|
--------------------------------------------------------------------------
|
|
-- Virtex-4: JTAG Loader
|
|
--------------------------------------------------------------------------
|
|
i00_BUFG : BUFG
|
|
port map
|
|
(
|
|
O => bs_clk1,
|
|
I => bs_clk0
|
|
);
|
|
|
|
i01_BUFG : BUFG
|
|
port map
|
|
(
|
|
O => bs_update1,
|
|
I => bs_update0
|
|
);
|
|
|
|
BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4
|
|
generic map
|
|
(
|
|
JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
|
)
|
|
port map
|
|
(
|
|
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
|
DRCK => bs_clk0, -- Data register output for USER functions
|
|
RESET => bs_rst, -- Reset output from TAP controller
|
|
SEL => bs_sel, -- USER active output
|
|
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
|
TDI => bs_tdi, -- TDI output from TAP controller
|
|
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
|
TDO => bs_tdo -- Data input for USER function
|
|
);
|
|
|
|
jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);
|
|
jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);
|
|
jtag_ld_clk <= bs_update1;
|
|
jtag_ld_we <= bs_sel;
|
|
|
|
sipo:
|
|
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
|
begin
|
|
if bs_rst = '1' then
|
|
user_regi <= (others => '0');
|
|
elsif rising_edge(bs_clk1) then
|
|
if bs_shift = '1' then
|
|
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
piso:
|
|
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
|
begin
|
|
bs_tdo <= user_rego(0);
|
|
if bs_rst = '1' then
|
|
user_rego <= (others => '0');
|
|
elsif rising_edge(bs_clk1) then
|
|
if bs_shift = '1' then
|
|
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
|
else
|
|
user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;
|
|
-- user_rego <= id;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
PROM_WRITE:
|
|
process(jtag_ld_clk, jtag_ld_we)
|
|
begin
|
|
if rising_edge(jtag_ld_clk) then
|
|
if jtag_ld_we = '1' then
|
|
imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
|
else
|
|
jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr));
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
--------------------------------------------------------------------------
|
|
-- ROM Read/Write
|
|
--------------------------------------------------------------------------
|
|
PROM_READ:
|
|
process(clk)
|
|
begin
|
|
if rising_edge(clk) then
|
|
dout <= imem_rom(to_integer(addr));
|
|
end if;
|
|
end process;
|
|
|
|
--------------------------------------------------------------------------
|
|
end loadable;
|