Compare commits
| Author | SHA1 | Date | |
|---|---|---|---|
 jens
|
d19b90ebc6 |
@@ -4,14 +4,10 @@
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vlib work
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vlib work
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vcom -explicit -93 "../../misc/utils_pkg.vhd"
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vcom -explicit -93 "../../misc/utils_pkg.vhd"
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vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
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vcom -explicit -93 "../../misc/dpram_1w1r.vhd"
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vcom -explicit -93 "../../misc/dpram_2w2r.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
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vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
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vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
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vcom -explicit -93 "../../FIFO/src/fifo_async.vhd"
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vcom -explicit -93 "../src/piso.vhd"
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vcom -explicit -93 "../src/sipo.vhd"
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vcom -explicit -93 "../src/shifter.vhd"
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vcom -explicit -93 "../src/emac_jb.vhd"
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vcom -explicit -93 "../src/emac_jb.vhd"
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vcom -explicit -93 "../src/tb_emac_jb.vhd"
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vcom -explicit -93 "../src/tb_emac_jb.vhd"
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vsim -t 1ps -lib work tb_emac_jb
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vsim -t 1ps -lib work tb_emac_jb
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@@ -18,7 +18,6 @@ vcom -explicit -93 "../src/emac_types.vhd"
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vcom -explicit -93 "../src/emac_rx.vhd"
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vcom -explicit -93 "../src/emac_rx.vhd"
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vcom -explicit -93 "../src/emac_tx.vhd"
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vcom -explicit -93 "../src/emac_tx.vhd"
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vcom -explicit -93 "../src/emac_top_jb.vhd"
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vcom -explicit -93 "../src/emac_top_jb.vhd"
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vcom -explicit -93 "../src/pkt_gen.vhd"
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vcom -explicit -93 "../src/tb_emac_top_jb.vhd"
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vcom -explicit -93 "../src/tb_emac_top_jb.vhd"
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vsim -t 1ps -lib work tb_emac_top_jb
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vsim -t 1ps -lib work tb_emac_top_jb
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view wave
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view wave
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@@ -26,4 +25,4 @@ do {tb_emac_top_jb.wdo}
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view structure
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view structure
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view signals
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view signals
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run 50000 us
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run 250 us
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@@ -25,8 +25,6 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_gtx_clk
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_gtx_clk
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_crs
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_crs
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_col
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_col
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/status_reg
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/size_reg
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/dat_o_reg
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/dat_o_reg
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add wave -noupdate -format Literal /tb_emac_top_jb/emac_action
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add wave -noupdate -format Literal /tb_emac_top_jb/emac_action
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add wave -noupdate -format Logic /tb_emac_top_jb/dat_o_cnt_rst
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add wave -noupdate -format Logic /tb_emac_top_jb/dat_o_cnt_rst
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@@ -35,75 +33,81 @@ add wave -noupdate -format Literal /tb_emac_top_jb/pkt_count
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add wave -noupdate -divider {Packet generator}
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add wave -noupdate -divider {Packet generator}
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/pkt_delay
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_pkt_gen/pkt_data
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add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nbytes
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add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nbytes
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add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nwords
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add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nwords
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/pkt_delay
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/pkt_delay
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/host_s
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_in
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_pkt_gen/tx_ctrl_out
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
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add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_size
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add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/fill_cnt
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_rdy
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_set
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/fill_en
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_pkt_gen/tx_din
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_pkt_gen/tx_din_vld
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/pktgen_tx
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add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_en
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add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_tx_er
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add wave -noupdate -format Logic /tb_emac_top_jb/pktgen_en
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add wave -noupdate -divider RX
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add wave -noupdate -divider RX
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout_vld
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout_vld
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_in
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_in
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add wave -noupdate -format Literal -radix unsigned -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out
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add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_clk
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_clk
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_dv
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_dv
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_er
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_er
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_crs
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_crs
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_col
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_col
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_dout
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_we
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_re
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_empty
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_full
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_din
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||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_dout
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_dout
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||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_we
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_we
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||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_re
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_re
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||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_empty
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_empty
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||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_full
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_full
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ptr
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fill_ptr
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_limit
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_ram_base
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/commit_en
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/commit_en
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_limit
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_limit
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_full
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_full
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_base
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_base
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_size
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr_set
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr_adv
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt_set
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt_adv
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_rdy
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_a
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_a
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_a
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_a
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_dout_a
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_b
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_b
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_b
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_b
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout
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add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout_be
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout_vld
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout_en
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_en
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_rst
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_rst
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout_vld
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout_en
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_en
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count_en
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count_en
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add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count_reg
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add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_din_vld
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add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_en
|
||||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_be
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_full
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_vld
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_empty
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_dout_en
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_we
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_en
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_re
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo32_rst
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_din
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_dout
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_rst
|
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_vld
|
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo8_dout_en
|
|
||||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
|
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
|
||||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s
|
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s
|
||||||
|
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/stream_s
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rst
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rst
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_ok
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_ok
|
||||||
@@ -113,7 +117,9 @@ add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/m
|
|||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rst
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rst
|
||||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_num_ok
|
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_num_ok
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_addr
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_addr
|
||||||
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout_vld
|
||||||
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_cnt
|
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_cnt
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout
|
||||||
add wave -noupdate -divider TX
|
add wave -noupdate -divider TX
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst
|
||||||
@@ -161,27 +167,30 @@ add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/r
|
|||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_a
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_a
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_a
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_a
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_a
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_a
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_a
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_b
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_b
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_b
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_b
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_b
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_b
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_b
|
||||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_cnt
|
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_cnt
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_idle
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_idle
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din
|
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_be
|
||||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_be
|
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_rdy
|
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_din_vld
|
|
||||||
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout
|
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_vld
|
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso32_dout_en
|
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld
|
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy
|
||||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_vld
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout
|
||||||
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld
|
||||||
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_en
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_din
|
||||||
|
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_dout
|
||||||
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_we
|
||||||
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re
|
||||||
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_empty
|
||||||
|
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_full
|
||||||
|
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/stream_s
|
||||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s
|
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s
|
||||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s
|
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s
|
||||||
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_req
|
|
||||||
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_ack
|
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 1} {47057926829 ps} 0} {{Cursor 2} {50099085366 ps} 0} {{Cursor 3} {18156000484 ps} 0}
|
WaveRestoreCursors {{Cursor 1} {18401055846 ps} 0} {{Cursor 2} {49999375873 ps} 0}
|
||||||
configure wave -namecolwidth 150
|
configure wave -namecolwidth 150
|
||||||
configure wave -valuecolwidth 100
|
configure wave -valuecolwidth 100
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@@ -195,4 +204,4 @@ configure wave -gridperiod 100
|
|||||||
configure wave -griddelta 40
|
configure wave -griddelta 40
|
||||||
configure wave -timeline 1
|
configure wave -timeline 1
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {0 ps} {24865002750 ps}
|
WaveRestoreZoom {3250153138 ps} {28560670888 ps}
|
||||||
|
|||||||
+367
-181
@@ -37,6 +37,13 @@ ARCHITECTURE behavior OF emac_rx IS
|
|||||||
subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
|
subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
|
||||||
|
|
||||||
-- Signals for EMAC connections
|
-- Signals for EMAC connections
|
||||||
|
signal mii_fifo_din : unsigned(31 downto 0);
|
||||||
|
signal mii_fifo_dout : unsigned(31 downto 0);
|
||||||
|
signal mii_fifo_we : std_logic;
|
||||||
|
signal mii_fifo_re : std_logic;
|
||||||
|
signal mii_fifo_empty : std_logic;
|
||||||
|
signal mii_fifo_full : std_logic;
|
||||||
|
|
||||||
signal cmd_fifo_din : unsigned(2*word_ptr_t'length+2 downto 0);
|
signal cmd_fifo_din : unsigned(2*word_ptr_t'length+2 downto 0);
|
||||||
signal cmd_fifo_dout : unsigned(2*word_ptr_t'length+2 downto 0);
|
signal cmd_fifo_dout : unsigned(2*word_ptr_t'length+2 downto 0);
|
||||||
signal cmd_fifo_we : std_logic;
|
signal cmd_fifo_we : std_logic;
|
||||||
@@ -46,50 +53,62 @@ ARCHITECTURE behavior OF emac_rx IS
|
|||||||
|
|
||||||
signal reset_en : std_logic;
|
signal reset_en : std_logic;
|
||||||
|
|
||||||
signal host_ptr : word_ptr_t;
|
signal fill_ptr : word_ptr_t;
|
||||||
signal host_ram_limit : word_ptr_t;
|
|
||||||
signal host_ram_base : word_ptr_t;
|
|
||||||
|
|
||||||
signal commit_en : std_logic;
|
signal commit_en : std_logic;
|
||||||
|
|
||||||
signal xfer_ram_limit : word_ptr_t;
|
signal xfer_ram_limit : word_ptr_t;
|
||||||
signal xfer_ram_full : std_logic;
|
signal xfer_ram_full : std_logic;
|
||||||
signal xfer_base : word_ptr_t;
|
signal xfer_base : word_ptr_t;
|
||||||
|
signal xfer_size : word_ptr_t;
|
||||||
signal xfer_ptr : word_ptr_t;
|
signal xfer_ptr : word_ptr_t;
|
||||||
signal xfer_en : std_logic;
|
signal xfer_ptr_set : std_logic;
|
||||||
signal xfer_set : std_logic;
|
signal xfer_ptr_adv : std_logic;
|
||||||
|
signal xfer_cnt_set : std_logic;
|
||||||
|
signal xfer_cnt_adv : std_logic;
|
||||||
|
signal xfer_rdy : std_logic;
|
||||||
signal xfer_vld : std_logic;
|
signal xfer_vld : std_logic;
|
||||||
signal xfer_promiscious : std_logic;
|
|
||||||
|
|
||||||
signal ram_en_a : std_logic;
|
signal ram_en_a : std_logic;
|
||||||
signal ram_we_a : std_logic;
|
signal ram_we_a : std_logic;
|
||||||
signal ram_addr_a : word_ptr_t;
|
signal ram_addr_a : word_ptr_t;
|
||||||
signal ram_din_a : unsigned(31 downto 0);
|
signal ram_din_a : unsigned(31 downto 0);
|
||||||
signal ram_dout_b : unsigned(31 downto 0);
|
signal ram_dout_a : unsigned(31 downto 0);
|
||||||
signal ram_en_b : std_logic;
|
signal ram_en_b : std_logic;
|
||||||
|
signal ram_we_b : std_logic;
|
||||||
signal ram_addr_b : word_ptr_t;
|
signal ram_addr_b : word_ptr_t;
|
||||||
|
signal ram_din_b : unsigned(31 downto 0);
|
||||||
|
|
||||||
signal sipo32_din : unsigned(7 downto 0);
|
signal sipo_32bit_dout : unsigned(31 downto 0);
|
||||||
signal sipo32_din_vld : std_logic;
|
signal sipo_32bit_dout_be : unsigned(3 downto 0);
|
||||||
signal sipo32_dout : unsigned(31 downto 0);
|
signal sipo_32bit_dout_vld : std_logic;
|
||||||
signal sipo32_dout_be : unsigned(3 downto 0);
|
signal sipo_32bit_dout_en : std_logic;
|
||||||
signal sipo32_dout_vld : std_logic;
|
signal sipo_32bit_en : std_logic;
|
||||||
signal sipo32_dout_en : std_logic;
|
signal sipo_32bit_rst : std_logic;
|
||||||
signal sipo32_en : std_logic;
|
|
||||||
signal sipo32_rst : std_logic;
|
|
||||||
|
|
||||||
signal sipo8_dout : unsigned(7 downto 0);
|
signal sipo_8bit_dout : unsigned(7 downto 0);
|
||||||
signal sipo8_rst : std_logic;
|
signal sipo_8bit_rst : std_logic;
|
||||||
signal sipo8_dout_vld : std_logic;
|
signal sipo_8bit_dout_vld : std_logic;
|
||||||
signal sipo8_dout_en : std_logic;
|
signal sipo_8bit_dout_en : std_logic;
|
||||||
signal sipo8_en : std_logic;
|
signal sipo_8bit_en : std_logic;
|
||||||
|
|
||||||
signal byte_count_rst : std_logic;
|
signal byte_count_en : std_logic;
|
||||||
signal byte_count : word_ptr_t;
|
signal byte_count : word_ptr_t;
|
||||||
|
signal byte_count_reg : word_ptr_t;
|
||||||
|
|
||||||
|
signal word_count : word_ptr_t;
|
||||||
|
signal word_count_en : std_logic;
|
||||||
|
|
||||||
|
signal size_fifo_full : std_logic;
|
||||||
|
signal size_fifo_empty : std_logic;
|
||||||
|
signal size_fifo_we : std_logic;
|
||||||
|
signal size_fifo_re : std_logic;
|
||||||
|
signal size_fifo_din : unsigned(2*word_ptr_t'length+2 downto 0);
|
||||||
|
signal size_fifo_dout : unsigned(2*word_ptr_t'length+2 downto 0);
|
||||||
|
|
||||||
signal reset_pipe : unsigned(31 downto 0);
|
signal reset_pipe : unsigned(31 downto 0);
|
||||||
|
|
||||||
signal preamble_en : std_logic;
|
signal preamble_rst : std_logic;
|
||||||
signal preamble_rdy : std_logic;
|
signal preamble_rdy : std_logic;
|
||||||
signal preamble_bsy : std_logic;
|
signal preamble_bsy : std_logic;
|
||||||
signal preamble_OK : std_logic;
|
signal preamble_OK : std_logic;
|
||||||
@@ -97,62 +116,83 @@ ARCHITECTURE behavior OF emac_rx IS
|
|||||||
signal mac_chk_rdy : std_logic;
|
signal mac_chk_rdy : std_logic;
|
||||||
signal mac_chk_BC : std_logic;
|
signal mac_chk_BC : std_logic;
|
||||||
signal mac_chk_OK : std_logic;
|
signal mac_chk_OK : std_logic;
|
||||||
|
signal mac_chk_rst : std_logic;
|
||||||
signal mac_chk_num_OK : natural range 0 to 6;
|
signal mac_chk_num_OK : natural range 0 to 6;
|
||||||
signal mac_chk_num_BC : natural range 0 to 6;
|
signal mac_chk_num_BC : natural range 0 to 6;
|
||||||
signal mac_chk_cnt : natural range 0 to 5;
|
signal mac_chk_cnt : natural range 0 to 5;
|
||||||
signal mac_addr : mac_addr_t;
|
|
||||||
signal mac_chk_addr : mac_addr_t;
|
signal mac_chk_addr : mac_addr_t;
|
||||||
|
|
||||||
signal Gbps_en : std_logic;
|
|
||||||
signal rx_en : std_logic;
|
|
||||||
|
|
||||||
type host_state_t is (host_init, host_flush, host_idle);
|
type host_state_t is (host_init, host_flush, host_idle);
|
||||||
signal host_s, host_sn : host_state_t;
|
signal host_s, host_sn : host_state_t;
|
||||||
|
|
||||||
type xfer_state_t is (xfer_init, xfer_idle, xfer_preamble, xfer_setup, xfer_active, xfer_finish, xfer_commit);
|
type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_active, xfer_drop, xfer_commit, xfer_free);
|
||||||
signal xfer_s, xfer_sn : xfer_state_t;
|
signal xfer_s, xfer_sn : xfer_state_t;
|
||||||
|
|
||||||
|
type stream_state_t is (stream_init, stream_reset, stream_idle, stream_active, stream_stop, stream_finish);
|
||||||
|
signal stream_s, stream_sn : stream_state_t;
|
||||||
|
|
||||||
alias cmd_mac_ok_in is cmd_fifo_din(cmd_fifo_din'left);
|
alias cmd_mac_ok_in is cmd_fifo_din(cmd_fifo_din'left);
|
||||||
alias cmd_bcast_in is cmd_fifo_din(cmd_fifo_din'left-1);
|
alias cmd_bcast_in is cmd_fifo_din(cmd_fifo_din'left-1);
|
||||||
alias cmd_pkt_valid_in is cmd_fifo_din(cmd_fifo_din'left-2);
|
alias cmd_invalid_in is cmd_fifo_din(cmd_fifo_din'left-2);
|
||||||
alias cmd_nbytes_in is cmd_fifo_din(word_ptr_t'length-1 downto 0);
|
alias cmd_nbytes_in is cmd_fifo_din(word_ptr_t'length-1 downto 0);
|
||||||
alias cmd_base_in is cmd_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length);
|
alias cmd_base_in is cmd_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length);
|
||||||
|
|
||||||
alias cmd_mac_ok_out is cmd_fifo_dout(cmd_fifo_dout'left);
|
alias cmd_mac_ok_out is cmd_fifo_dout(cmd_fifo_dout'left);
|
||||||
alias cmd_bcast_out is cmd_fifo_dout(cmd_fifo_dout'left-1);
|
alias cmd_bcast_out is cmd_fifo_dout(cmd_fifo_dout'left-1);
|
||||||
alias cmd_pkt_valid_out is cmd_fifo_dout(cmd_fifo_dout'left-2);
|
alias cmd_invalid_out is cmd_fifo_dout(cmd_fifo_dout'left-2);
|
||||||
alias cmd_nbytes_out is cmd_fifo_dout(word_ptr_t'length-1 downto 0);
|
alias cmd_nbytes_out is cmd_fifo_dout(word_ptr_t'length-1 downto 0);
|
||||||
alias cmd_base_out is cmd_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length);
|
alias cmd_base_out is cmd_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length);
|
||||||
|
|
||||||
|
alias stream_mac_ok_in is size_fifo_din(size_fifo_din'left);
|
||||||
|
alias stream_broadcast_in is size_fifo_din(size_fifo_din'left-1);
|
||||||
|
alias stream_badcrc_in is size_fifo_din(size_fifo_din'left-2);
|
||||||
|
alias stream_nbytes_in is size_fifo_din(word_ptr_t'length-1 downto 0);
|
||||||
|
alias stream_nwords_in is size_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length);
|
||||||
|
|
||||||
|
alias stream_mac_ok_out is size_fifo_dout(size_fifo_dout'left);
|
||||||
|
alias stream_broadcast_out is size_fifo_dout(size_fifo_dout'left-1);
|
||||||
|
alias stream_badcrc_out is size_fifo_dout(size_fifo_dout'left-2);
|
||||||
|
alias stream_nbytes_out is size_fifo_dout(word_ptr_t'length-1 downto 0);
|
||||||
|
alias stream_nwords_out is size_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length);
|
||||||
|
|
||||||
begin
|
begin
|
||||||
|
|
||||||
ctrl_out.rx_size <= resize(cmd_nbytes_out, 16);
|
ctrl_out.rx_size <= resize(cmd_nbytes_out, 16);
|
||||||
ctrl_out.pkt_avail <= not cmd_fifo_empty;
|
ctrl_out.pkt_avail <= not cmd_fifo_empty;
|
||||||
ctrl_out.pkt_valid <= cmd_pkt_valid_out;
|
ctrl_out.rx_er <= mii_rx_er;
|
||||||
|
ctrl_out.reset_busy <= reset_en;
|
||||||
ctrl_out.pkt_bcast <= cmd_bcast_out;
|
ctrl_out.pkt_bcast <= cmd_bcast_out;
|
||||||
ctrl_out.pkt_mac_match <= cmd_mac_ok_out;
|
ctrl_out.pkt_mac_match <= cmd_mac_ok_out;
|
||||||
ctrl_out.reset_busy <= reset_en;
|
|
||||||
|
|
||||||
dout <= ram_dout_b;
|
dout <= ram_dout_a;
|
||||||
|
|
||||||
ram_en_b <= '1';
|
mii_fifo_din <= sipo_32bit_dout;
|
||||||
ram_addr_b <= host_ptr;
|
mii_fifo_we <= word_count_en and sipo_32bit_dout_vld;
|
||||||
|
|
||||||
ram_en_a <= '1';
|
ram_en_a <= '1';
|
||||||
ram_din_a <= sipo32_dout;
|
ram_din_a <= (others => '-');
|
||||||
ram_addr_a <= xfer_ptr;
|
ram_addr_a <= fill_ptr;
|
||||||
ram_we_a <= xfer_en and sipo32_dout_vld;
|
ram_we_a <= '0';
|
||||||
|
|
||||||
xfer_vld <= mac_chk_OK or mac_chk_BC or xfer_promiscious;
|
ram_en_b <= '1';
|
||||||
cmd_fifo_we <= commit_en and xfer_vld;
|
ram_din_b <= mii_fifo_dout;
|
||||||
|
ram_addr_b <= xfer_ptr;
|
||||||
|
ram_we_b <= xfer_ptr_adv;
|
||||||
|
|
||||||
|
cmd_fifo_we <= commit_en;
|
||||||
cmd_fifo_re <= ctrl_in.pkt_free_en;
|
cmd_fifo_re <= ctrl_in.pkt_free_en;
|
||||||
|
|
||||||
cmd_pkt_valid_in <= '1';
|
cmd_mac_ok_in <= stream_mac_ok_out;
|
||||||
cmd_mac_ok_in <= mac_chk_OK;
|
cmd_bcast_in <= stream_broadcast_out;
|
||||||
cmd_bcast_in <= mac_chk_BC;
|
cmd_invalid_in <= stream_badcrc_out;
|
||||||
cmd_nbytes_in <= byte_count;
|
cmd_nbytes_in <= stream_nbytes_out;
|
||||||
cmd_base_in <= xfer_base;
|
cmd_base_in <= xfer_base;
|
||||||
|
|
||||||
|
stream_nbytes_in <= byte_count_reg;
|
||||||
|
stream_nwords_in <= word_count;
|
||||||
|
stream_mac_ok_in <= mac_chk_OK;
|
||||||
|
stream_broadcast_in <= mac_chk_BC;
|
||||||
|
stream_badcrc_in <= '0';
|
||||||
|
|
||||||
reset_en <= reset_pipe(reset_pipe'left);
|
reset_en <= reset_pipe(reset_pipe'left);
|
||||||
|
|
||||||
@@ -178,9 +218,9 @@ fill_pointer:
|
|||||||
if rising_edge(clk) then
|
if rising_edge(clk) then
|
||||||
dout_vld <= ctrl_in.pkt_read_en;
|
dout_vld <= ctrl_in.pkt_read_en;
|
||||||
if ctrl_in.pkt_req_en = '1' then
|
if ctrl_in.pkt_req_en = '1' then
|
||||||
host_ptr <= cmd_base_out;
|
fill_ptr <= cmd_base_out;
|
||||||
elsif ctrl_in.pkt_read_en = '1' then
|
elsif ctrl_in.pkt_read_en = '1' then
|
||||||
host_ptr <= host_ptr + 1;
|
fill_ptr <= fill_ptr + 1;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
@@ -188,38 +228,117 @@ fill_pointer:
|
|||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
-- Transfer stuff
|
-- Transfer stuff
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
host2xfer_sync_register:
|
xfer_state_next:
|
||||||
process(mii_rx_clk)
|
|
||||||
begin
|
|
||||||
if rising_edge(mii_rx_clk) then
|
|
||||||
xfer_promiscious <= ctrl_in.promiscious;
|
|
||||||
Gbps_en <= ctrl_in.Gbps_en;
|
|
||||||
mac_addr <= ctrl_in.mac_addr;
|
|
||||||
xfer_ram_limit <= host_ram_limit;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
host_limit_register:
|
|
||||||
process(clk)
|
process(clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(clk) then
|
if rising_edge(clk) then
|
||||||
host_ram_base <= xfer_base;
|
if reset_en = '1' then
|
||||||
if cmd_fifo_empty = '1' then
|
xfer_s <= xfer_init;
|
||||||
host_ram_limit <= host_ram_base - 1;
|
|
||||||
else
|
else
|
||||||
host_ram_limit <= cmd_base_out - 1;
|
xfer_s <= xfer_sn;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
xfer_state:
|
||||||
|
process(xfer_s, size_fifo_empty, mii_fifo_empty, xfer_rdy, xfer_vld, xfer_ram_full)
|
||||||
|
begin
|
||||||
|
|
||||||
|
commit_en <= '0';
|
||||||
|
xfer_ptr_set <= '0';
|
||||||
|
xfer_ptr_adv <= '0';
|
||||||
|
xfer_cnt_set <= '0';
|
||||||
|
xfer_cnt_adv <= '0';
|
||||||
|
size_fifo_re <= '0';
|
||||||
|
mii_fifo_re <= '0';
|
||||||
|
|
||||||
|
xfer_sn <= xfer_s;
|
||||||
|
|
||||||
|
case xfer_s is
|
||||||
|
|
||||||
|
when xfer_init =>
|
||||||
|
xfer_sn <= xfer_idle;
|
||||||
|
|
||||||
|
when xfer_idle =>
|
||||||
|
if mii_fifo_empty = '0' then
|
||||||
|
xfer_sn <= xfer_setup;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when xfer_setup =>
|
||||||
|
xfer_cnt_set <= '1';
|
||||||
|
xfer_ptr_set <= '1';
|
||||||
|
xfer_sn <= xfer_active;
|
||||||
|
|
||||||
|
when xfer_active =>
|
||||||
|
mii_fifo_re <= '1';
|
||||||
|
xfer_cnt_adv <= not mii_fifo_empty;
|
||||||
|
xfer_ptr_adv <= not mii_fifo_empty;
|
||||||
|
if xfer_ram_full = '1' then
|
||||||
|
xfer_sn <= xfer_drop;
|
||||||
|
elsif size_fifo_empty = '0' then
|
||||||
|
if xfer_rdy = '1' then
|
||||||
|
xfer_sn <= xfer_free;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when xfer_drop =>
|
||||||
|
mii_fifo_re <= '1';
|
||||||
|
xfer_cnt_adv <= not mii_fifo_empty;
|
||||||
|
if size_fifo_empty = '0' then
|
||||||
|
if xfer_rdy = '1' then
|
||||||
|
xfer_sn <= xfer_free;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when xfer_free =>
|
||||||
|
size_fifo_re <= '1';
|
||||||
|
commit_en <= not xfer_ram_full and xfer_vld;
|
||||||
|
xfer_sn <= xfer_idle;
|
||||||
|
|
||||||
|
when others =>
|
||||||
|
xfer_sn <= xfer_idle;
|
||||||
|
end case;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
------------------------------------------------------------------
|
||||||
|
pkt_lost_register:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if reset_en = '1' then
|
||||||
|
ctrl_out.pkt_lost <= '0';
|
||||||
|
elsif size_fifo_re = '1' and xfer_ram_full = '1' then
|
||||||
|
ctrl_out.pkt_lost <= '1';
|
||||||
|
elsif ctrl_in.pkt_free_en = '1' then
|
||||||
|
ctrl_out.pkt_lost <= '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
xfer_limit_register:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if xfer_ptr_set = '1' then
|
||||||
|
if cmd_fifo_empty = '1' then
|
||||||
|
xfer_ram_limit <= xfer_base - 1;
|
||||||
|
else
|
||||||
|
xfer_ram_limit <= cmd_base_out - 1;
|
||||||
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
xfer_ram_full_detect:
|
xfer_ram_full_detect:
|
||||||
process(mii_rx_clk)
|
process(clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(mii_rx_clk) then
|
if rising_edge(clk) then
|
||||||
if xfer_set = '1' or reset_en = '1' then
|
if xfer_ptr_set = '1' or reset_en = '1' then
|
||||||
xfer_ram_full <= '0';
|
xfer_ram_full <= '0';
|
||||||
elsif xfer_en = '1' and sipo32_dout_vld = '1' then
|
elsif xfer_ptr_adv = '1' then
|
||||||
if xfer_ptr = xfer_ram_limit then
|
if xfer_ptr = xfer_ram_limit then
|
||||||
xfer_ram_full <= '1';
|
xfer_ram_full <= '1';
|
||||||
end if;
|
end if;
|
||||||
@@ -228,59 +347,101 @@ xfer_ram_full_detect:
|
|||||||
|
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
xfer_base_logic:
|
xfer_counter:
|
||||||
process(mii_rx_clk)
|
process(clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(mii_rx_clk) then
|
if rising_edge(clk) then
|
||||||
if reset_en = '1' then
|
if xfer_cnt_set = '1' then
|
||||||
xfer_base <= (others => '0');
|
xfer_rdy <= '0';
|
||||||
elsif commit_en = '1' and xfer_vld = '1' then
|
xfer_vld <= '0';
|
||||||
xfer_base <= xfer_ptr;
|
elsif xfer_size = stream_nwords_out then
|
||||||
|
xfer_rdy <= '1';
|
||||||
|
xfer_vld <= stream_mac_ok_out or stream_broadcast_out or ctrl_in.promiscious;
|
||||||
|
end if;
|
||||||
|
if xfer_cnt_set = '1' then
|
||||||
|
xfer_size <= (others => '0');
|
||||||
|
elsif xfer_cnt_adv = '1' then
|
||||||
|
xfer_size <= xfer_size + 1;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
xfer_pointer:
|
xfer_pointer:
|
||||||
process(mii_rx_clk)
|
process(clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(mii_rx_clk) then
|
if rising_edge(clk) then
|
||||||
if xfer_set = '1' then
|
if xfer_ptr_set = '1' then
|
||||||
xfer_ptr <= xfer_base;
|
xfer_ptr <= xfer_base;
|
||||||
elsif xfer_en = '1' and sipo32_dout_vld = '1' then
|
elsif xfer_ptr_adv = '1' then
|
||||||
xfer_ptr <= xfer_ptr + 1;
|
xfer_ptr <= xfer_ptr + 1;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
|
xfer_base_logic:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if reset_en = '1' then
|
||||||
|
xfer_base <= (others => '0');
|
||||||
|
elsif commit_en = '1' then
|
||||||
|
xfer_base <= xfer_ptr;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
byte_counter:
|
byte_counter:
|
||||||
process(mii_rx_clk)
|
process(mii_rx_clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(mii_rx_clk) then
|
if rising_edge(mii_rx_clk) then
|
||||||
if byte_count_rst = '1' then
|
if sipo_8bit_rst = '1' then
|
||||||
byte_count <= (others => '0');
|
byte_count <= (others => '0');
|
||||||
elsif sipo32_en = '1' and sipo32_din_vld = '1' then
|
elsif byte_count_en = '1' and sipo_8bit_dout_vld = '1' then
|
||||||
byte_count <= byte_count + 1;
|
byte_count <= byte_count + 1;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
|
byte_count_register:
|
||||||
|
process(mii_rx_clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(mii_rx_clk) then
|
||||||
|
if sipo_8bit_rst = '1' then
|
||||||
|
byte_count_reg <= byte_count;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
word_counter:
|
||||||
|
process(mii_rx_clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(mii_rx_clk) then
|
||||||
|
if sipo_32bit_rst = '1' then
|
||||||
|
word_count <= (others => '0');
|
||||||
|
elsif word_count_en = '1' and sipo_32bit_dout_vld = '1' then
|
||||||
|
word_count <= word_count + 1;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
preamble_sync_logic:
|
preamble_sync_logic:
|
||||||
process(mii_rx_clk)
|
process(mii_rx_clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(mii_rx_clk) then
|
if rising_edge(mii_rx_clk) then
|
||||||
if preamble_en = '0' then
|
if preamble_rst = '1' then
|
||||||
preamble_rdy <= '0';
|
preamble_rdy <= '0';
|
||||||
preamble_bsy <= '0';
|
preamble_bsy <= '0';
|
||||||
preamble_OK <= '0';
|
preamble_OK <= '0';
|
||||||
elsif sipo32_din_vld = '1' then
|
elsif sipo_8bit_dout_vld = '1' then
|
||||||
if preamble_bsy = '1' then
|
if preamble_bsy = '1' then
|
||||||
if sipo32_din = X"D5" then
|
if sipo_8bit_dout = X"D5" then
|
||||||
preamble_OK <= '1';
|
preamble_OK <= '1';
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
if sipo32_din /= X"55" then
|
if sipo_8bit_dout /= X"55" then
|
||||||
preamble_bsy <= '0';
|
preamble_bsy <= '0';
|
||||||
preamble_rdy <= preamble_bsy;
|
preamble_rdy <= preamble_bsy;
|
||||||
else
|
else
|
||||||
@@ -294,14 +455,14 @@ mac_check_logic:
|
|||||||
process(mii_rx_clk)
|
process(mii_rx_clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(mii_rx_clk) then
|
if rising_edge(mii_rx_clk) then
|
||||||
if byte_count_rst = '1' then
|
if mac_chk_rst = '1' then
|
||||||
mac_chk_rdy <= '0';
|
mac_chk_rdy <= '0';
|
||||||
mac_chk_OK <= '0';
|
mac_chk_OK <= '0';
|
||||||
mac_chk_BC <= '0';
|
mac_chk_BC <= '0';
|
||||||
mac_chk_cnt <= 0;
|
mac_chk_cnt <= 0;
|
||||||
mac_chk_num_OK <= 0;
|
mac_chk_num_OK <= 0;
|
||||||
mac_chk_num_BC <= 0;
|
mac_chk_num_BC <= 0;
|
||||||
mac_chk_addr <= mac_addr;
|
mac_chk_addr <= ctrl_in.mac_addr;
|
||||||
elsif mac_chk_rdy = '1' then
|
elsif mac_chk_rdy = '1' then
|
||||||
if mac_chk_num_OK = 6 then
|
if mac_chk_num_OK = 6 then
|
||||||
mac_chk_OK <= '1';
|
mac_chk_OK <= '1';
|
||||||
@@ -309,11 +470,11 @@ mac_check_logic:
|
|||||||
if mac_chk_num_BC = 6 then
|
if mac_chk_num_BC = 6 then
|
||||||
mac_chk_BC <= '1';
|
mac_chk_BC <= '1';
|
||||||
end if;
|
end if;
|
||||||
elsif sipo32_din_vld = '1' and sipo32_en = '1' then
|
elsif sipo_8bit_dout_vld = '1' then
|
||||||
if sipo32_din = mac_chk_addr(mac_chk_cnt) then
|
if sipo_8bit_dout = mac_chk_addr(mac_chk_cnt) then
|
||||||
mac_chk_num_OK <= mac_chk_num_OK + 1;
|
mac_chk_num_OK <= mac_chk_num_OK + 1;
|
||||||
end if;
|
end if;
|
||||||
if sipo32_din = X"FF" then
|
if sipo_8bit_dout = X"FF" then
|
||||||
mac_chk_num_BC <= mac_chk_num_BC + 1;
|
mac_chk_num_BC <= mac_chk_num_BC + 1;
|
||||||
end if;
|
end if;
|
||||||
if mac_chk_cnt /= 5 then
|
if mac_chk_cnt /= 5 then
|
||||||
@@ -326,91 +487,88 @@ mac_check_logic:
|
|||||||
end process;
|
end process;
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
xfer_state_next:
|
stream_state_next:
|
||||||
process(mii_rx_clk)
|
process(mii_rx_clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(mii_rx_clk) then
|
if rising_edge(mii_rx_clk) then
|
||||||
if reset_en = '1' then
|
if reset_en = '1' then
|
||||||
xfer_s <= xfer_init;
|
stream_s <= stream_init;
|
||||||
else
|
else
|
||||||
xfer_s <= xfer_sn;
|
stream_s <= stream_sn;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
xfer_state:
|
stream_state:
|
||||||
process(xfer_s, rx_en, sipo32_dout_en, preamble_bsy, preamble_OK, xfer_ram_full)
|
process(stream_s, reset_en, sipo_8bit_dout_en, sipo_8bit_dout, sipo_32bit_dout_en, sipo_32bit_dout_vld, preamble_rdy, preamble_OK)
|
||||||
begin
|
begin
|
||||||
|
|
||||||
commit_en <= '0';
|
sipo_32bit_en <= '0';
|
||||||
xfer_set <= '0';
|
sipo_32bit_rst <= reset_en;
|
||||||
xfer_en <= '0';
|
sipo_8bit_rst <= reset_en;
|
||||||
sipo32_rst <= '0';
|
word_count_en <= '0';
|
||||||
sipo32_en <= '0';
|
byte_count_en <= '0';
|
||||||
byte_count_rst <= '0';
|
size_fifo_we <= '0';
|
||||||
preamble_en <= '0';
|
preamble_rst <= reset_en;
|
||||||
|
mac_chk_rst <= reset_en;
|
||||||
|
|
||||||
xfer_sn <= xfer_s;
|
sipo_32bit_en <= sipo_8bit_dout_en;
|
||||||
|
|
||||||
case xfer_s is
|
stream_sn <= stream_s;
|
||||||
|
|
||||||
when xfer_init =>
|
case stream_s is
|
||||||
sipo32_rst <= '1';
|
|
||||||
if rx_en = '0' then
|
when stream_init =>
|
||||||
xfer_sn <= xfer_idle;
|
if sipo_8bit_dout_en = '0' then
|
||||||
|
stream_sn <= stream_reset;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when xfer_idle =>
|
when stream_reset =>
|
||||||
preamble_en <= rx_en;
|
sipo_32bit_rst <= '1';
|
||||||
if preamble_bsy = '1' then
|
sipo_8bit_rst <= '1';
|
||||||
xfer_sn <= xfer_preamble;
|
preamble_rst <= '1';
|
||||||
end if;
|
stream_sn <= stream_idle;
|
||||||
|
|
||||||
when xfer_preamble =>
|
when stream_idle =>
|
||||||
preamble_en <= rx_en;
|
sipo_32bit_en <= '0';
|
||||||
byte_count_rst <= preamble_bsy;
|
if preamble_rdy = '1' then
|
||||||
sipo32_en <= rx_en and not preamble_bsy;
|
stream_sn <= stream_init;
|
||||||
if preamble_bsy = '0' then
|
|
||||||
xfer_sn <= xfer_init;
|
|
||||||
if preamble_OK = '1' then
|
if preamble_OK = '1' then
|
||||||
xfer_sn <= xfer_setup;
|
byte_count_en <= '1';
|
||||||
|
mac_chk_rst <= '1';
|
||||||
|
sipo_32bit_rst <= '1';
|
||||||
|
stream_sn <= stream_active;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when xfer_setup =>
|
when stream_active =>
|
||||||
xfer_set <= '1';
|
word_count_en <= sipo_32bit_dout_en;
|
||||||
sipo32_en <= rx_en;
|
byte_count_en <= sipo_8bit_dout_en;
|
||||||
xfer_en <= sipo32_dout_en;
|
if sipo_8bit_dout_en = '0' then
|
||||||
xfer_sn <= xfer_active;
|
stream_sn <= stream_stop;
|
||||||
|
sipo_8bit_rst <= '1';
|
||||||
when xfer_active =>
|
|
||||||
xfer_en <= sipo32_dout_en;
|
|
||||||
sipo32_en <= rx_en;
|
|
||||||
if xfer_ram_full = '1' then
|
|
||||||
xfer_sn <= xfer_init;
|
|
||||||
elsif rx_en = '0' then
|
|
||||||
xfer_sn <= xfer_finish;
|
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when xfer_finish =>
|
when stream_stop =>
|
||||||
xfer_en <= sipo32_dout_en;
|
word_count_en <= sipo_32bit_dout_en;
|
||||||
if sipo32_dout_en = '0' then
|
byte_count_en <= sipo_8bit_dout_en;
|
||||||
xfer_sn <= xfer_commit;
|
if sipo_32bit_dout_en = '0' then
|
||||||
|
stream_sn <= stream_finish;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when xfer_commit =>
|
when stream_finish =>
|
||||||
commit_en <= '1';
|
size_fifo_we <= '1';
|
||||||
xfer_sn <= xfer_init;
|
stream_sn <= stream_init;
|
||||||
|
|
||||||
when others =>
|
when others =>
|
||||||
xfer_sn <= xfer_init;
|
stream_sn <= stream_init;
|
||||||
end case;
|
end case;
|
||||||
|
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
-- Instantiate synchronous FIFO
|
-- Instantiate synchronous FIFO
|
||||||
inst_cmd_fifo: entity work.fifo_async
|
inst_cmd_fifo: entity work.fifo_sync
|
||||||
GENERIC MAP
|
GENERIC MAP
|
||||||
(
|
(
|
||||||
addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words)
|
addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words)
|
||||||
@@ -420,8 +578,7 @@ inst_cmd_fifo: entity work.fifo_async
|
|||||||
PORT MAP
|
PORT MAP
|
||||||
(
|
(
|
||||||
rst => reset_en,
|
rst => reset_en,
|
||||||
clk_w => mii_rx_clk,
|
clk => clk,
|
||||||
clk_r => clk,
|
|
||||||
we => cmd_fifo_we,
|
we => cmd_fifo_we,
|
||||||
re => cmd_fifo_re,
|
re => cmd_fifo_re,
|
||||||
fifo_full => cmd_fifo_full,
|
fifo_full => cmd_fifo_full,
|
||||||
@@ -440,18 +597,64 @@ inst_ram : entity work.dpram_1w1r
|
|||||||
)
|
)
|
||||||
PORT MAP
|
PORT MAP
|
||||||
(
|
(
|
||||||
clka => mii_rx_clk,
|
clka => clk,
|
||||||
clkb => clk,
|
clkb => clk,
|
||||||
en_a => ram_en_a,
|
en_a => ram_en_b,
|
||||||
en_b => ram_en_b,
|
en_b => ram_en_a,
|
||||||
we_a => ram_we_a,
|
we_a => ram_we_b,
|
||||||
addr_a => ram_addr_a,
|
addr_a => ram_addr_b,
|
||||||
addr_b => ram_addr_b,
|
addr_b => ram_addr_a,
|
||||||
din_a => ram_din_a,
|
din_a => ram_din_b,
|
||||||
dout_b => ram_dout_b
|
dout_b => ram_dout_a
|
||||||
);
|
);
|
||||||
|
|
||||||
inst_sipo32 : entity work.sipo
|
-- Instantiate synchronous FIFO
|
||||||
|
inst_mii_fifo: entity work.fifo_async
|
||||||
|
GENERIC MAP
|
||||||
|
(
|
||||||
|
addr_width => 4,
|
||||||
|
data_width => mii_fifo_din'length,
|
||||||
|
do_last_read_update => true
|
||||||
|
)
|
||||||
|
PORT MAP
|
||||||
|
(
|
||||||
|
rst => reset_en,
|
||||||
|
clk_w => mii_rx_clk,
|
||||||
|
clk_r => clk,
|
||||||
|
we => mii_fifo_we,
|
||||||
|
re => mii_fifo_re,
|
||||||
|
fifo_full => mii_fifo_full,
|
||||||
|
fifo_empty => mii_fifo_empty,
|
||||||
|
fifo_afull => open,
|
||||||
|
fifo_aempty => open,
|
||||||
|
data_w => mii_fifo_din,
|
||||||
|
data_r => mii_fifo_dout
|
||||||
|
);
|
||||||
|
|
||||||
|
-- Instantiate synchronous FIFO
|
||||||
|
inst_size_fifo: entity work.fifo_async
|
||||||
|
GENERIC MAP
|
||||||
|
(
|
||||||
|
addr_width => 1,
|
||||||
|
data_width => size_fifo_din'length,
|
||||||
|
do_last_read_update => true
|
||||||
|
)
|
||||||
|
PORT MAP
|
||||||
|
(
|
||||||
|
rst => reset_en,
|
||||||
|
clk_w => mii_rx_clk,
|
||||||
|
clk_r => clk,
|
||||||
|
we => size_fifo_we,
|
||||||
|
re => size_fifo_re,
|
||||||
|
fifo_full => size_fifo_full,
|
||||||
|
fifo_empty => size_fifo_empty,
|
||||||
|
fifo_afull => open,
|
||||||
|
fifo_aempty => open,
|
||||||
|
data_w => size_fifo_din,
|
||||||
|
data_r => size_fifo_dout
|
||||||
|
);
|
||||||
|
|
||||||
|
inst_sipo : entity work.sipo
|
||||||
GENERIC MAP
|
GENERIC MAP
|
||||||
(
|
(
|
||||||
data_width_in => 8,
|
data_width_in => 8,
|
||||||
@@ -460,33 +663,18 @@ inst_sipo32 : entity work.sipo
|
|||||||
)
|
)
|
||||||
PORT MAP
|
PORT MAP
|
||||||
(
|
(
|
||||||
rst => sipo32_rst,
|
rst => sipo_32bit_rst,
|
||||||
clk => mii_rx_clk,
|
clk => mii_rx_clk,
|
||||||
din_vld => sipo32_din_vld,
|
din_vld => sipo_8bit_dout_vld,
|
||||||
din_en => sipo32_en,
|
din_en => sipo_32bit_en,
|
||||||
din => sipo32_din,
|
din => sipo_8bit_dout,
|
||||||
dout_be => sipo32_dout_be,
|
dout_be => sipo_32bit_dout_be,
|
||||||
dout_vld => sipo32_dout_vld,
|
dout_vld => sipo_32bit_dout_vld,
|
||||||
dout => sipo32_dout,
|
dout => sipo_32bit_dout,
|
||||||
dout_en => sipo32_dout_en
|
dout_en => sipo_32bit_dout_en
|
||||||
|
|
||||||
);
|
);
|
||||||
|
|
||||||
mii_input_register:
|
|
||||||
process(mii_rx_clk)
|
|
||||||
begin
|
|
||||||
if rising_edge(mii_rx_clk) then
|
|
||||||
if Gbps_en = '1' then
|
|
||||||
sipo32_din <= mii_rx;
|
|
||||||
sipo32_din_vld <= not mii_rx_er;
|
|
||||||
rx_en <= mii_rx_dv;
|
|
||||||
else
|
|
||||||
sipo32_din <= sipo8_dout;
|
|
||||||
sipo32_din_vld <= sipo8_dout_vld;
|
|
||||||
rx_en <= sipo8_dout_en;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
inst_sipo_8bit : entity work.sipo
|
inst_sipo_8bit : entity work.sipo
|
||||||
GENERIC MAP
|
GENERIC MAP
|
||||||
@@ -497,19 +685,17 @@ inst_sipo_8bit : entity work.sipo
|
|||||||
)
|
)
|
||||||
PORT MAP
|
PORT MAP
|
||||||
(
|
(
|
||||||
rst => sipo8_rst,
|
rst => sipo_8bit_rst,
|
||||||
clk => mii_rx_clk,
|
clk => mii_rx_clk,
|
||||||
din_vld => mii_rx_dv,
|
din_vld => mii_rx_dv,
|
||||||
din_en => mii_rx_dv,
|
din_en => sipo_8bit_en,
|
||||||
din => mii_rx(3 downto 0),
|
din => mii_rx(3 downto 0),
|
||||||
dout_be => open,
|
dout_be => open,
|
||||||
dout_vld => sipo8_dout_vld,
|
dout_vld => sipo_8bit_dout_vld,
|
||||||
dout => sipo8_dout,
|
dout => sipo_8bit_dout,
|
||||||
dout_en => sipo8_dout_en
|
dout_en => sipo_8bit_dout_en
|
||||||
|
|
||||||
);
|
);
|
||||||
|
sipo_8bit_en <= mii_rx_dv;
|
||||||
sipo8_rst <= reset_en or not (mii_rx_dv or sipo8_dout_en);
|
|
||||||
sipo8_en <= not mii_rx_er;
|
|
||||||
|
|
||||||
end behavior;
|
end behavior;
|
||||||
|
|||||||
@@ -86,55 +86,39 @@ registers_write:
|
|||||||
if RST_I = '1' then
|
if RST_I = '1' then
|
||||||
rx_int_en <= '0';
|
rx_int_en <= '0';
|
||||||
tx_int_en <= '0';
|
tx_int_en <= '0';
|
||||||
|
tx_ctrl_in.tx_er <= '0';
|
||||||
tx_ctrl_in.tx_size <= (others => '0');
|
tx_ctrl_in.tx_size <= (others => '0');
|
||||||
rx_ctrl_in.mac_addr <= (X"03", X"02", X"01", X"00", X"07", X"06");
|
rx_ctrl_in.mac_addr <= (X"03", X"02", X"01", X"00", X"07", X"06");
|
||||||
rx_ctrl_in.promiscious <= '0';
|
rx_ctrl_in.promiscious <= '1';
|
||||||
tx_ctrl_in.Gbps_en <= '0';
|
|
||||||
rx_ctrl_in.Gbps_en <= '0';
|
|
||||||
elsif (STB_I and CYC_I and WE_I) = '1' then
|
elsif (STB_I and CYC_I and WE_I) = '1' then
|
||||||
case ADDR_I(5 downto 2) is
|
case ADDR_I(5 downto 2) is
|
||||||
|
|
||||||
-- 0x0000
|
|
||||||
when "0000" =>
|
when "0000" =>
|
||||||
rx_ctrl_in.reset <= DAT_I(31);
|
tx_ctrl_in.tx_er <= DAT_I(31);
|
||||||
rx_ctrl_in.Gbps_en <= DAT_I(30);
|
tx_ctrl_in.reset <= DAT_I(27);
|
||||||
rx_ctrl_in.promiscious <= DAT_I(23);
|
tx_ctrl_in.pkt_alloc_en <= DAT_I(25);
|
||||||
rx_ctrl_in.pkt_req_en <= DAT_I(17);
|
tx_ctrl_in.pkt_commit_en <= DAT_I(24);
|
||||||
rx_ctrl_in.pkt_free_en <= DAT_I(16);
|
rx_ctrl_in.reset <= DAT_I(23);
|
||||||
|
rx_ctrl_in.pkt_free_en <= DAT_I(17);
|
||||||
|
rx_ctrl_in.pkt_req_en <= DAT_I(16);
|
||||||
|
tx_int_en <= DAT_I(5);
|
||||||
rx_int_en <= DAT_I(4);
|
rx_int_en <= DAT_I(4);
|
||||||
|
rx_ctrl_in.promiscious <= DAT_I(3);
|
||||||
|
|
||||||
-- 0x0004
|
when "0001" =>
|
||||||
-- rx_size R/O
|
tx_ctrl_in.tx_size <= DAT_I(31 downto 16);
|
||||||
|
|
||||||
-- 0x0008
|
|
||||||
when "0010" =>
|
when "0010" =>
|
||||||
tx_ctrl_in.reset <= DAT_I(31);
|
|
||||||
tx_ctrl_in.Gbps_en <= DAT_I(30);
|
|
||||||
tx_ctrl_in.pkt_alloc_en <= DAT_I(17);
|
|
||||||
tx_ctrl_in.pkt_commit_en <= DAT_I(16);
|
|
||||||
tx_int_en <= DAT_I(4);
|
|
||||||
|
|
||||||
-- 0x000C
|
|
||||||
when "0011" =>
|
|
||||||
tx_ctrl_in.tx_size <= DAT_I(15 downto 0);
|
|
||||||
|
|
||||||
-- 0x0010
|
|
||||||
when "0100" =>
|
|
||||||
tx_din_vld <= '1';
|
tx_din_vld <= '1';
|
||||||
tx_din <= DAT_I;
|
tx_din <= DAT_I;
|
||||||
|
|
||||||
-- 0x0014
|
when "0100" =>
|
||||||
-- Gap
|
|
||||||
|
|
||||||
-- 0x0018
|
|
||||||
when "0110" =>
|
|
||||||
rx_ctrl_in.mac_addr(0) <= DAT_I(31 downto 24);
|
rx_ctrl_in.mac_addr(0) <= DAT_I(31 downto 24);
|
||||||
rx_ctrl_in.mac_addr(1) <= DAT_I(23 downto 16);
|
rx_ctrl_in.mac_addr(1) <= DAT_I(23 downto 16);
|
||||||
rx_ctrl_in.mac_addr(2) <= DAT_I(15 downto 8);
|
rx_ctrl_in.mac_addr(2) <= DAT_I(15 downto 8);
|
||||||
rx_ctrl_in.mac_addr(3) <= DAT_I(7 downto 0);
|
rx_ctrl_in.mac_addr(3) <= DAT_I(7 downto 0);
|
||||||
|
|
||||||
-- 0x001C
|
when "0101" =>
|
||||||
when "0111" =>
|
|
||||||
rx_ctrl_in.mac_addr(4) <= DAT_I(31 downto 24);
|
rx_ctrl_in.mac_addr(4) <= DAT_I(31 downto 24);
|
||||||
rx_ctrl_in.mac_addr(5) <= DAT_I(23 downto 16);
|
rx_ctrl_in.mac_addr(5) <= DAT_I(23 downto 16);
|
||||||
|
|
||||||
@@ -154,54 +138,38 @@ registers_read:
|
|||||||
if (STB_I and CYC_I) = '1' and WE_I = '0' then
|
if (STB_I and CYC_I) = '1' and WE_I = '0' then
|
||||||
case ADDR_I(5 downto 2) is
|
case ADDR_I(5 downto 2) is
|
||||||
|
|
||||||
-- 0x0000
|
|
||||||
when "0000" =>
|
when "0000" =>
|
||||||
ACK_O <= ready;
|
ACK_O <= ready;
|
||||||
DAT_O <= (others => '0');
|
DAT_O <= (others => '0');
|
||||||
DAT_O(31) <= rx_ctrl_out.reset_busy;
|
DAT_O(31) <= tx_ctrl_in.tx_er;
|
||||||
DAT_O(30) <= rx_ctrl_in.Gbps_en;
|
DAT_O(30) <= mii_rx_er; -- remove that
|
||||||
DAT_O(23) <= rx_ctrl_in.promiscious;
|
DAT_O(29) <= mii_col; -- remove that
|
||||||
|
DAT_O(28) <= mii_crs; -- remove that
|
||||||
|
DAT_O(27) <= tx_ctrl_out.reset_busy;
|
||||||
|
DAT_O(26) <= tx_ctrl_out.pkt_done;
|
||||||
|
DAT_O(25) <= tx_ctrl_out.pkt_alloc_req;
|
||||||
|
DAT_O(24) <= tx_ctrl_out.pkt_armed;
|
||||||
|
DAT_O(23) <= rx_ctrl_out.reset_busy;
|
||||||
DAT_O(19) <= rx_ctrl_out.pkt_bcast;
|
DAT_O(19) <= rx_ctrl_out.pkt_bcast;
|
||||||
DAT_O(18) <= rx_ctrl_out.pkt_mac_match;
|
DAT_O(18) <= rx_ctrl_out.pkt_mac_match;
|
||||||
DAT_O(17) <= rx_ctrl_out.pkt_valid;
|
DAT_O(17) <= rx_ctrl_out.pkt_lost;
|
||||||
DAT_O(16) <= rx_ctrl_out.pkt_avail;
|
DAT_O(16) <= rx_ctrl_out.pkt_avail;
|
||||||
|
DAT_O(5) <= tx_int_en;
|
||||||
DAT_O(4) <= rx_int_en;
|
DAT_O(4) <= rx_int_en;
|
||||||
|
DAT_O(3) <= rx_ctrl_in.promiscious;
|
||||||
|
|
||||||
-- 0x0004
|
|
||||||
when "0001" =>
|
when "0001" =>
|
||||||
ACK_O <= '1';
|
ACK_O <= '1';
|
||||||
DAT_O <= X"0000" & rx_ctrl_out.rx_size;
|
DAT_O <= tx_ctrl_out.tx_size & rx_ctrl_out.rx_size;
|
||||||
|
|
||||||
-- 0x0008
|
|
||||||
when "0010" =>
|
when "0010" =>
|
||||||
ACK_O <= ready;
|
|
||||||
DAT_O <= (others => '0');
|
|
||||||
DAT_O(31) <= tx_ctrl_out.reset_busy;
|
|
||||||
DAT_O(30) <= tx_ctrl_in.Gbps_en;
|
|
||||||
DAT_O(24) <= tx_ctrl_out.pkt_done;
|
|
||||||
DAT_O(17) <= tx_ctrl_out.pkt_alloc_req;
|
|
||||||
DAT_O(16) <= tx_ctrl_out.pkt_armed;
|
|
||||||
DAT_O(4) <= tx_int_en;
|
|
||||||
|
|
||||||
-- 0x000C
|
|
||||||
when "0011" =>
|
|
||||||
ACK_O <= '1';
|
|
||||||
DAT_O <= X"0000" & tx_ctrl_out.tx_size;
|
|
||||||
|
|
||||||
-- 0x0010
|
|
||||||
when "0100" =>
|
|
||||||
rx_ctrl_in.pkt_read_en <= '1';
|
rx_ctrl_in.pkt_read_en <= '1';
|
||||||
|
|
||||||
-- 0x0014
|
when "0100" =>
|
||||||
-- Gap
|
|
||||||
|
|
||||||
-- 0x0018
|
|
||||||
when "0110" =>
|
|
||||||
ACK_O <= '1';
|
ACK_O <= '1';
|
||||||
DAT_O <= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3);
|
DAT_O <= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3);
|
||||||
|
|
||||||
-- 0x001C
|
when "0101" =>
|
||||||
when "0111" =>
|
|
||||||
ACK_O <= '1';
|
ACK_O <= '1';
|
||||||
DAT_O <= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000";
|
DAT_O <= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000";
|
||||||
|
|
||||||
|
|||||||
+203
-152
@@ -34,6 +34,13 @@ ARCHITECTURE behavior OF emac_tx IS
|
|||||||
|
|
||||||
subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
|
subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
|
||||||
|
|
||||||
|
signal mii_fifo_din : unsigned(35 downto 0);
|
||||||
|
signal mii_fifo_dout : unsigned(35 downto 0);
|
||||||
|
signal mii_fifo_we : std_logic;
|
||||||
|
signal mii_fifo_re : std_logic;
|
||||||
|
signal mii_fifo_empty : std_logic;
|
||||||
|
signal mii_fifo_full : std_logic;
|
||||||
|
|
||||||
signal cmd_fifo_din : unsigned(2*word_ptr_t'length-1 downto 0);
|
signal cmd_fifo_din : unsigned(2*word_ptr_t'length-1 downto 0);
|
||||||
signal cmd_fifo_dout : unsigned(2*word_ptr_t'length-1 downto 0);
|
signal cmd_fifo_dout : unsigned(2*word_ptr_t'length-1 downto 0);
|
||||||
signal cmd_fifo_we : std_logic;
|
signal cmd_fifo_we : std_logic;
|
||||||
@@ -65,41 +72,40 @@ ARCHITECTURE behavior OF emac_tx IS
|
|||||||
signal mem_alloc_en : std_logic;
|
signal mem_alloc_en : std_logic;
|
||||||
signal mem_free_en : std_logic;
|
signal mem_free_en : std_logic;
|
||||||
signal nwords_free : word_ptr_t;
|
signal nwords_free : word_ptr_t;
|
||||||
signal mem_free_req : std_logic;
|
|
||||||
signal mem_free_ack : unsigned(1 downto 0);
|
|
||||||
|
|
||||||
signal xfer_size : word_ptr_t;
|
signal xfer_size : word_ptr_t;
|
||||||
signal xfer_ptr : word_ptr_t;
|
signal xfer_ptr : word_ptr_t;
|
||||||
signal xfer_cnt : word_ptr_t;
|
signal xfer_cnt : word_ptr_t;
|
||||||
signal xfer_set : std_logic;
|
signal xfer_set : std_logic;
|
||||||
signal xfer_en : std_logic;
|
signal xfer_en : std_logic;
|
||||||
|
signal xfer_sync : unsigned(1 downto 0);
|
||||||
signal xfer_cnt_en : std_logic;
|
signal xfer_cnt_en : std_logic;
|
||||||
signal xfer_bsy : std_logic;
|
signal xfer_bsy : std_logic;
|
||||||
signal xfer_free_en : std_logic;
|
|
||||||
|
|
||||||
signal ram_en_a : std_logic;
|
signal ram_en_a : std_logic;
|
||||||
signal ram_we_a : std_logic;
|
signal ram_we_a : std_logic;
|
||||||
signal ram_addr_a : word_ptr_t;
|
signal ram_addr_a : word_ptr_t;
|
||||||
signal ram_din_a : unsigned(35 downto 0);
|
signal ram_din_a : unsigned(35 downto 0);
|
||||||
|
signal ram_dout_a : unsigned(35 downto 0);
|
||||||
signal ram_en_b : std_logic;
|
signal ram_en_b : std_logic;
|
||||||
signal ram_addr_b : word_ptr_t;
|
signal ram_addr_b : word_ptr_t;
|
||||||
|
signal ram_din_b : unsigned(35 downto 0);
|
||||||
signal ram_dout_b : unsigned(35 downto 0);
|
signal ram_dout_b : unsigned(35 downto 0);
|
||||||
|
|
||||||
signal piso32_din : unsigned(31 downto 0);
|
signal piso8_din : unsigned(31 downto 0);
|
||||||
signal piso32_din_be : unsigned(3 downto 0);
|
signal piso8_din_be : unsigned(3 downto 0);
|
||||||
signal piso32_din_rdy : std_logic;
|
|
||||||
signal piso32_din_vld : std_logic;
|
|
||||||
|
|
||||||
signal piso32_dout : unsigned(7 downto 0);
|
|
||||||
signal piso32_dout_vld : std_logic;
|
|
||||||
signal piso32_dout_en : std_logic;
|
|
||||||
|
|
||||||
signal piso8_dout_vld : std_logic;
|
|
||||||
signal piso8_din_rdy : std_logic;
|
signal piso8_din_rdy : std_logic;
|
||||||
signal piso8_dout : unsigned(3 downto 0);
|
signal piso8_din_vld : std_logic;
|
||||||
|
|
||||||
|
signal piso8_dout : unsigned(7 downto 0);
|
||||||
|
signal piso8_dout_vld : std_logic;
|
||||||
|
signal piso8_dout_en : std_logic;
|
||||||
|
|
||||||
|
signal piso4_dout_vld : std_logic;
|
||||||
|
signal piso4_din_rdy : std_logic;
|
||||||
|
signal piso4_dout : unsigned(3 downto 0);
|
||||||
|
|
||||||
signal reset_pipe : unsigned(31 downto 0);
|
signal reset_pipe : unsigned(31 downto 0);
|
||||||
signal Gbps_en : std_logic;
|
|
||||||
|
|
||||||
subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
|
subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
|
||||||
-- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
|
-- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
|
||||||
@@ -110,9 +116,12 @@ ARCHITECTURE behavior OF emac_tx IS
|
|||||||
type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
|
type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
|
||||||
signal host_s, host_sn : host_state_t;
|
signal host_s, host_sn : host_state_t;
|
||||||
|
|
||||||
type xfer_state_t is (xfer_init, xfer_idle, xfer_start, xfer_preamble0, xfer_preamble1, xfer_active, xfer_crc, xfer_stop, xfer_finish);
|
type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free);
|
||||||
signal xfer_s, xfer_sn : xfer_state_t;
|
signal xfer_s, xfer_sn : xfer_state_t;
|
||||||
|
|
||||||
|
type stream_state_t is (stream_init, stream_idle, stream_start, stream_preamble0, stream_preamble1, stream_active, stream_crc, stream_stop, stream_finish);
|
||||||
|
signal stream_s, stream_sn : stream_state_t;
|
||||||
|
|
||||||
type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
|
type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
|
||||||
constant piso_byte_mask_rom : piso_byte_mask_array_t :=
|
constant piso_byte_mask_rom : piso_byte_mask_array_t :=
|
||||||
(
|
(
|
||||||
@@ -137,6 +146,8 @@ begin
|
|||||||
ctrl_out.pkt_alloc_req <= alloc_req;
|
ctrl_out.pkt_alloc_req <= alloc_req;
|
||||||
ctrl_out.pkt_done <= cmd_fifo_empty;
|
ctrl_out.pkt_done <= cmd_fifo_empty;
|
||||||
ctrl_out.reset_busy <= reset_en;
|
ctrl_out.reset_busy <= reset_en;
|
||||||
|
mii_tx_er <= ctrl_in.tx_er;
|
||||||
|
|
||||||
|
|
||||||
ram_en_a <= din_vld;
|
ram_en_a <= din_vld;
|
||||||
ram_we_a <= fill_bsy;
|
ram_we_a <= fill_bsy;
|
||||||
@@ -144,20 +155,22 @@ begin
|
|||||||
ram_din_a(35 downto 32) <= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111";
|
ram_din_a(35 downto 32) <= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111";
|
||||||
ram_addr_a <= fill_ptr;
|
ram_addr_a <= fill_ptr;
|
||||||
|
|
||||||
piso32_din <= preamble(preamble_addr) when preamble_en = '1' else ram_dout_b(31 downto 0);
|
mii_fifo_din <= ram_dout_b;
|
||||||
piso32_din_be <= "1111" when preamble_en = '1' else ram_dout_b(35 downto 32);
|
|
||||||
|
piso8_din <= preamble(preamble_addr) when preamble_en = '1' else mii_fifo_dout(31 downto 0);
|
||||||
|
piso8_din_be <= "1111" when preamble_en = '1' else mii_fifo_dout(35 downto 32);
|
||||||
|
|
||||||
cmd_fifo_we <= commit_en;
|
cmd_fifo_we <= commit_en;
|
||||||
cmd_fifo_re <= uncommit_en;
|
cmd_fifo_re <= uncommit_en;
|
||||||
cmd_fifo_din <= fill_size & fill_base;
|
cmd_fifo_din <= fill_size & fill_base;
|
||||||
ram_en_b <= piso32_din_rdy;
|
ram_en_b <= not mii_fifo_full;
|
||||||
ram_addr_b <= xfer_ptr;
|
ram_addr_b <= xfer_ptr;
|
||||||
|
|
||||||
reset_en <= reset_pipe(reset_pipe'left);
|
reset_en <= reset_pipe(reset_pipe'left);
|
||||||
|
|
||||||
xfer_cnt_en <= xfer_bsy and piso32_din_rdy;
|
mii_fifo_we <= xfer_bsy;
|
||||||
|
xfer_cnt_en <= xfer_bsy and not mii_fifo_full;
|
||||||
fill_cnt_en <= fill_bsy and din_vld;
|
fill_cnt_en <= fill_bsy and din_vld;
|
||||||
mem_free_en <= not mem_free_ack(0) and mem_free_ack(1);
|
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
reset_gen:
|
reset_gen:
|
||||||
@@ -186,7 +199,7 @@ host_state_next:
|
|||||||
end process;
|
end process;
|
||||||
|
|
||||||
host_state:
|
host_state:
|
||||||
process(host_s, alloc_OK, fill_bsy, ctrl_in.pkt_commit_en, alloc_req, mem_free_ack)
|
process(host_s, alloc_OK, fill_bsy, ctrl_in.pkt_commit_en, alloc_req)
|
||||||
begin
|
begin
|
||||||
|
|
||||||
fill_set <= '0';
|
fill_set <= '0';
|
||||||
@@ -233,11 +246,9 @@ host_state:
|
|||||||
end if;
|
end if;
|
||||||
|
|
||||||
when host_commit =>
|
when host_commit =>
|
||||||
if mem_free_ack = "00" then
|
commit_en <= '1';
|
||||||
commit_en <= '1';
|
mem_alloc_en <= '1';
|
||||||
mem_alloc_en <= '1';
|
host_sn <= host_idle;
|
||||||
host_sn <= host_idle;
|
|
||||||
end if;
|
|
||||||
|
|
||||||
when others =>
|
when others =>
|
||||||
host_sn <= host_idle;
|
host_sn <= host_idle;
|
||||||
@@ -307,7 +318,7 @@ fill_base_logic:
|
|||||||
end process;
|
end process;
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
mem_free_counter:
|
nwords_free_counter:
|
||||||
process(clk)
|
process(clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(clk) then
|
if rising_edge(clk) then
|
||||||
@@ -321,47 +332,6 @@ mem_free_counter:
|
|||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
mem_free_mii:
|
|
||||||
process(mii_tx_clk)
|
|
||||||
begin
|
|
||||||
if rising_edge(mii_tx_clk) then
|
|
||||||
if reset_en = '1' then
|
|
||||||
mem_free_req <= '0';
|
|
||||||
elsif mem_free_ack(0) = '0' then
|
|
||||||
if xfer_free_en = '1' then
|
|
||||||
mem_free_req <= '1';
|
|
||||||
end if;
|
|
||||||
else
|
|
||||||
mem_free_req <= '0';
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
mem_free_host:
|
|
||||||
process(clk)
|
|
||||||
begin
|
|
||||||
if rising_edge(clk) then
|
|
||||||
mem_free_ack(1) <= mem_free_ack(0);
|
|
||||||
if reset_en = '1' then
|
|
||||||
mem_free_ack <= "00";
|
|
||||||
elsif mem_free_req = '1' then
|
|
||||||
if mem_alloc_en = '0' then
|
|
||||||
mem_free_ack(0) <= '1';
|
|
||||||
end if;
|
|
||||||
else
|
|
||||||
mem_free_ack(0) <= '0';
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
host2xfer_sync_register:
|
|
||||||
process(mii_tx_clk)
|
|
||||||
begin
|
|
||||||
if rising_edge(mii_tx_clk) then
|
|
||||||
Gbps_en <= ctrl_in.Gbps_en;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
-- Fill stuff
|
-- Fill stuff
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
@@ -405,13 +375,89 @@ fill_pointer:
|
|||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
-- Transfer stuff
|
-- Transfer stuff
|
||||||
|
------------------------------------------------------------------
|
||||||
|
xfer_state_next:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if reset_en = '1' then
|
||||||
|
xfer_s <= xfer_init;
|
||||||
|
else
|
||||||
|
xfer_s <= xfer_sn;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
xfer_state:
|
||||||
|
process(xfer_s, cmd_fifo_empty, xfer_bsy, xfer_sync, mem_alloc_en)
|
||||||
|
begin
|
||||||
|
|
||||||
|
xfer_set <= '0';
|
||||||
|
xfer_en <= '0';
|
||||||
|
mem_free_en <= '0';
|
||||||
|
uncommit_en <= '0';
|
||||||
|
|
||||||
|
xfer_sn <= xfer_s;
|
||||||
|
|
||||||
|
case xfer_s is
|
||||||
|
|
||||||
|
when xfer_init =>
|
||||||
|
xfer_sn <= xfer_idle;
|
||||||
|
|
||||||
|
when xfer_idle =>
|
||||||
|
if cmd_fifo_empty = '0' then
|
||||||
|
xfer_sn <= xfer_setup;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when xfer_setup =>
|
||||||
|
xfer_set <= '1';
|
||||||
|
xfer_sn <= xfer_arm;
|
||||||
|
|
||||||
|
when xfer_arm =>
|
||||||
|
xfer_en <= '1';
|
||||||
|
xfer_sn <= xfer_active;
|
||||||
|
|
||||||
|
when xfer_active =>
|
||||||
|
xfer_en <= '1';
|
||||||
|
if xfer_bsy = '0' then
|
||||||
|
xfer_sn <= xfer_uncommit;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when xfer_uncommit =>
|
||||||
|
mem_free_en <= not mem_alloc_en;
|
||||||
|
if mem_alloc_en = '0' then
|
||||||
|
uncommit_en <= '1';
|
||||||
|
xfer_sn <= xfer_free;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when xfer_free =>
|
||||||
|
if xfer_sync(1) = '1' then
|
||||||
|
xfer_sn <= xfer_idle;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when others =>
|
||||||
|
xfer_sn <= xfer_idle;
|
||||||
|
end case;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
------------------------------------------------------------------
|
||||||
|
interframe_gap_ready:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
xfer_sync(1) <= xfer_sync(0);
|
||||||
|
xfer_sync(0) <= mii_fifo_empty;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
interframe_gap_counter:
|
interframe_gap_counter:
|
||||||
process(mii_tx_clk)
|
process(mii_tx_clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(mii_tx_clk) then
|
if rising_edge(mii_tx_clk) then
|
||||||
ifg_idle <= '0';
|
ifg_idle <= '0';
|
||||||
if reset_en = '1' or piso32_dout_vld = '1' then
|
if reset_en = '1' or piso8_dout_vld = '1' then
|
||||||
ifg_cnt <= ifg_cnt_t'high;
|
ifg_cnt <= ifg_cnt_t'high;
|
||||||
ifg_idle <= '1';
|
ifg_idle <= '1';
|
||||||
elsif ifg_cnt /= 0 then
|
elsif ifg_cnt /= 0 then
|
||||||
@@ -424,9 +470,9 @@ interframe_gap_counter:
|
|||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
xfer_counter:
|
xfer_counter:
|
||||||
process(mii_tx_clk)
|
process(clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(mii_tx_clk) then
|
if rising_edge(clk) then
|
||||||
xfer_bsy <= '0';
|
xfer_bsy <= '0';
|
||||||
if xfer_set = '1' then
|
if xfer_set = '1' then
|
||||||
xfer_cnt <= cmd_fifo_dout(cmd_fifo_dout'left downto word_ptr_t'length);
|
xfer_cnt <= cmd_fifo_dout(cmd_fifo_dout'left downto word_ptr_t'length);
|
||||||
@@ -447,9 +493,9 @@ xfer_counter:
|
|||||||
end process;
|
end process;
|
||||||
|
|
||||||
xfer_pointer:
|
xfer_pointer:
|
||||||
process(mii_tx_clk)
|
process(clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(mii_tx_clk) then
|
if rising_edge(clk) then
|
||||||
if xfer_set = '1' then
|
if xfer_set = '1' then
|
||||||
xfer_ptr <= cmd_fifo_dout(xfer_ptr'left downto 0);
|
xfer_ptr <= cmd_fifo_dout(xfer_ptr'left downto 0);
|
||||||
elsif xfer_en = '1' then
|
elsif xfer_en = '1' then
|
||||||
@@ -462,87 +508,82 @@ xfer_pointer:
|
|||||||
end process;
|
end process;
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
xfer_state_next:
|
stream_state_next:
|
||||||
process(mii_tx_clk)
|
process(mii_tx_clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(mii_tx_clk) then
|
if rising_edge(mii_tx_clk) then
|
||||||
if reset_en = '1' then
|
if reset_en = '1' then
|
||||||
xfer_s <= xfer_init;
|
stream_s <= stream_init;
|
||||||
else
|
else
|
||||||
xfer_s <= xfer_sn;
|
stream_s <= stream_sn;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
xfer_state:
|
stream_state:
|
||||||
process(xfer_s, ifg_idle, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy)
|
process(stream_s, ifg_idle, mii_fifo_empty, piso8_din_rdy, piso8_dout_vld)
|
||||||
begin
|
begin
|
||||||
|
|
||||||
piso32_din_vld <= '0';
|
piso8_din_vld <= '0';
|
||||||
|
mii_fifo_re <= '0';
|
||||||
preamble_en <= '0';
|
preamble_en <= '0';
|
||||||
preamble_addr <= 0;
|
preamble_addr <= 0;
|
||||||
xfer_set <= '0';
|
|
||||||
xfer_en <= '0';
|
|
||||||
xfer_free_en <= '0';
|
|
||||||
uncommit_en <= '0';
|
|
||||||
|
|
||||||
xfer_sn <= xfer_s;
|
stream_sn <= stream_s;
|
||||||
|
|
||||||
case xfer_s is
|
case stream_s is
|
||||||
|
|
||||||
when xfer_init =>
|
when stream_init =>
|
||||||
xfer_sn <= xfer_idle;
|
if mii_fifo_empty = '1' then
|
||||||
|
stream_sn <= stream_idle;
|
||||||
when xfer_idle =>
|
|
||||||
if cmd_fifo_empty = '0' and piso32_din_rdy = '1' then
|
|
||||||
xfer_sn <= xfer_start;
|
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when xfer_start =>
|
when stream_idle =>
|
||||||
xfer_set <= '1';
|
if mii_fifo_empty = '0' and piso8_din_rdy = '1' then
|
||||||
xfer_sn <= xfer_preamble0;
|
stream_sn <= stream_start;
|
||||||
|
end if;
|
||||||
|
|
||||||
when xfer_preamble0 =>
|
when stream_start =>
|
||||||
|
stream_sn <= stream_preamble0;
|
||||||
|
|
||||||
|
when stream_preamble0 =>
|
||||||
preamble_addr <= 0;
|
preamble_addr <= 0;
|
||||||
preamble_en <= '1';
|
preamble_en <= '1';
|
||||||
piso32_din_vld <= '1';
|
piso8_din_vld <= '1';
|
||||||
if piso32_din_rdy = '1' then
|
if piso8_din_rdy = '1' then
|
||||||
xfer_sn <= xfer_preamble1;
|
stream_sn <= stream_preamble1;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when xfer_preamble1 =>
|
when stream_preamble1 =>
|
||||||
preamble_addr <= 1;
|
preamble_addr <= 1;
|
||||||
preamble_en <= '1';
|
preamble_en <= '1';
|
||||||
piso32_din_vld <= '1';
|
piso8_din_vld <= '1';
|
||||||
if piso32_din_rdy = '1' then
|
if piso8_din_rdy = '1' then
|
||||||
xfer_sn <= xfer_active;
|
stream_sn <= stream_active;
|
||||||
xfer_en <= '1';
|
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when xfer_active =>
|
when stream_active =>
|
||||||
piso32_din_vld <= xfer_bsy;
|
piso8_din_vld <= not mii_fifo_empty;
|
||||||
xfer_en <= '1';
|
mii_fifo_re <= piso8_din_rdy;
|
||||||
if xfer_bsy = '0' then
|
if mii_fifo_empty = '1' then
|
||||||
uncommit_en <= '1';
|
stream_sn <= stream_crc;
|
||||||
xfer_free_en <= '1';
|
|
||||||
xfer_sn <= xfer_crc;
|
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when xfer_crc =>
|
when stream_crc =>
|
||||||
xfer_sn <= xfer_stop;
|
stream_sn <= stream_stop;
|
||||||
|
|
||||||
when xfer_stop =>
|
when stream_stop =>
|
||||||
if piso32_dout_vld = '0' then
|
if piso8_dout_vld = '0' then
|
||||||
xfer_sn <= xfer_finish;
|
stream_sn <= stream_finish;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when xfer_finish =>
|
when stream_finish =>
|
||||||
if ifg_idle = '0' then
|
if ifg_idle = '0' then
|
||||||
xfer_sn <= xfer_idle;
|
stream_sn <= stream_idle;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when others =>
|
when others =>
|
||||||
xfer_sn <= xfer_idle;
|
stream_sn <= stream_idle;
|
||||||
end case;
|
end case;
|
||||||
|
|
||||||
end process;
|
end process;
|
||||||
@@ -557,7 +598,7 @@ inst_ram : entity work.dpram_1w1r
|
|||||||
PORT MAP
|
PORT MAP
|
||||||
(
|
(
|
||||||
clka => clk,
|
clka => clk,
|
||||||
clkb => mii_tx_clk,
|
clkb => clk,
|
||||||
en_a => ram_en_a,
|
en_a => ram_en_a,
|
||||||
en_b => ram_en_b,
|
en_b => ram_en_b,
|
||||||
we_a => ram_we_a,
|
we_a => ram_we_a,
|
||||||
@@ -568,7 +609,7 @@ inst_ram : entity work.dpram_1w1r
|
|||||||
);
|
);
|
||||||
|
|
||||||
-- Instantiate synchronous FIFO
|
-- Instantiate synchronous FIFO
|
||||||
inst_cmd_fifo: entity work.fifo_async
|
inst_cmd_fifo: entity work.fifo_sync
|
||||||
GENERIC MAP
|
GENERIC MAP
|
||||||
(
|
(
|
||||||
addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words)
|
addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words)
|
||||||
@@ -578,8 +619,7 @@ inst_cmd_fifo: entity work.fifo_async
|
|||||||
PORT MAP
|
PORT MAP
|
||||||
(
|
(
|
||||||
rst => reset_en,
|
rst => reset_en,
|
||||||
clk_w => clk,
|
clk => clk,
|
||||||
clk_r => mii_tx_clk,
|
|
||||||
we => cmd_fifo_we,
|
we => cmd_fifo_we,
|
||||||
re => cmd_fifo_re,
|
re => cmd_fifo_re,
|
||||||
fifo_full => cmd_fifo_full,
|
fifo_full => cmd_fifo_full,
|
||||||
@@ -590,7 +630,30 @@ inst_cmd_fifo: entity work.fifo_async
|
|||||||
data_r => cmd_fifo_dout
|
data_r => cmd_fifo_dout
|
||||||
);
|
);
|
||||||
|
|
||||||
inst_piso32 : entity work.piso
|
-- Instantiate synchronous FIFO
|
||||||
|
inst_mii_fifo: entity work.fifo_async
|
||||||
|
GENERIC MAP
|
||||||
|
(
|
||||||
|
addr_width => 4,
|
||||||
|
data_width => mii_fifo_din'length,
|
||||||
|
do_last_read_update => true
|
||||||
|
)
|
||||||
|
PORT MAP
|
||||||
|
(
|
||||||
|
rst => reset_en,
|
||||||
|
clk_w => clk,
|
||||||
|
clk_r => mii_tx_clk,
|
||||||
|
we => mii_fifo_we,
|
||||||
|
re => mii_fifo_re,
|
||||||
|
fifo_full => mii_fifo_full,
|
||||||
|
fifo_empty => mii_fifo_empty,
|
||||||
|
fifo_afull => open,
|
||||||
|
fifo_aempty => open,
|
||||||
|
data_w => mii_fifo_din,
|
||||||
|
data_r => mii_fifo_dout
|
||||||
|
);
|
||||||
|
|
||||||
|
inst_piso8 : entity work.piso
|
||||||
GENERIC MAP
|
GENERIC MAP
|
||||||
(
|
(
|
||||||
data_width_in => 32,
|
data_width_in => 32,
|
||||||
@@ -601,19 +664,19 @@ inst_piso32 : entity work.piso
|
|||||||
(
|
(
|
||||||
rst => reset_en,
|
rst => reset_en,
|
||||||
clk => mii_tx_clk,
|
clk => mii_tx_clk,
|
||||||
din_vld => piso32_din_vld,
|
din_vld => piso8_din_vld,
|
||||||
din_rdy => piso32_din_rdy,
|
din_rdy => piso8_din_rdy,
|
||||||
din_be => piso32_din_be,
|
din_be => piso8_din_be,
|
||||||
din => piso32_din,
|
din => piso8_din,
|
||||||
dout_vld => piso32_dout_vld,
|
dout_vld => piso8_dout_vld,
|
||||||
dout_en => piso32_dout_en,
|
dout_en => piso8_dout_en,
|
||||||
dout => piso32_dout
|
dout => piso8_dout
|
||||||
|
|
||||||
);
|
);
|
||||||
|
|
||||||
piso32_dout_en <= '1' when Gbps_en = '1' else piso8_din_rdy;
|
piso8_dout_en <= piso4_din_rdy and ifg_idle;
|
||||||
|
|
||||||
inst_piso8 : entity work.piso
|
inst_piso4 : entity work.piso
|
||||||
GENERIC MAP
|
GENERIC MAP
|
||||||
(
|
(
|
||||||
data_width_in => 8,
|
data_width_in => 8,
|
||||||
@@ -624,29 +687,17 @@ inst_piso8 : entity work.piso
|
|||||||
(
|
(
|
||||||
rst => reset_en,
|
rst => reset_en,
|
||||||
clk => mii_tx_clk,
|
clk => mii_tx_clk,
|
||||||
din_vld => piso32_dout_vld,
|
din_vld => piso8_dout_vld,
|
||||||
din_rdy => piso8_din_rdy,
|
din_rdy => piso4_din_rdy,
|
||||||
din_be => "11",
|
din_be => "11",
|
||||||
din => piso32_dout,
|
din => piso8_dout,
|
||||||
dout_vld => piso8_dout_vld,
|
dout_vld => piso4_dout_vld,
|
||||||
dout_en => '1',
|
dout_en => '1',
|
||||||
dout => piso8_dout
|
dout => piso4_dout
|
||||||
|
|
||||||
);
|
);
|
||||||
|
|
||||||
mii_output_register:
|
mii_tx_en <= piso4_dout_vld;
|
||||||
process(mii_tx_clk)
|
mii_tx <= "0000" & piso4_dout;
|
||||||
begin
|
|
||||||
if rising_edge(mii_tx_clk) then
|
|
||||||
mii_tx_er <= '0';
|
|
||||||
if Gbps_en = '1' then
|
|
||||||
mii_tx_en <= piso32_dout_vld;
|
|
||||||
mii_tx <= piso32_dout;
|
|
||||||
else
|
|
||||||
mii_tx_en <= piso8_dout_vld;
|
|
||||||
mii_tx <= "0000" & piso8_dout;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
|
|
||||||
end behavior;
|
end behavior;
|
||||||
|
|||||||
@@ -16,11 +16,11 @@ package emac_types is
|
|||||||
|
|
||||||
-- Types
|
-- Types
|
||||||
type tx_ctrl_in_t is record
|
type tx_ctrl_in_t is record
|
||||||
Gbps_en : std_logic;
|
tx_er : std_logic;
|
||||||
reset : std_logic;
|
|
||||||
tx_size : unsigned(15 downto 0);
|
tx_size : unsigned(15 downto 0);
|
||||||
pkt_commit_en : std_logic;
|
pkt_commit_en : std_logic;
|
||||||
pkt_alloc_en : std_logic;
|
pkt_alloc_en : std_logic;
|
||||||
|
reset : std_logic;
|
||||||
end record;
|
end record;
|
||||||
|
|
||||||
type tx_ctrl_out_t is record
|
type tx_ctrl_out_t is record
|
||||||
@@ -32,7 +32,6 @@ package emac_types is
|
|||||||
end record;
|
end record;
|
||||||
|
|
||||||
type rx_ctrl_in_t is record
|
type rx_ctrl_in_t is record
|
||||||
Gbps_en : std_logic;
|
|
||||||
reset : std_logic;
|
reset : std_logic;
|
||||||
pkt_read_en : std_logic;
|
pkt_read_en : std_logic;
|
||||||
pkt_req_en : std_logic;
|
pkt_req_en : std_logic;
|
||||||
@@ -42,8 +41,9 @@ package emac_types is
|
|||||||
end record;
|
end record;
|
||||||
|
|
||||||
type rx_ctrl_out_t is record
|
type rx_ctrl_out_t is record
|
||||||
|
rx_er : std_logic;
|
||||||
pkt_avail : std_logic;
|
pkt_avail : std_logic;
|
||||||
pkt_valid : std_logic;
|
pkt_lost : std_logic;
|
||||||
pkt_bcast : std_logic;
|
pkt_bcast : std_logic;
|
||||||
pkt_mac_match : std_logic;
|
pkt_mac_match : std_logic;
|
||||||
rx_size : unsigned(15 downto 0);
|
rx_size : unsigned(15 downto 0);
|
||||||
|
|||||||
+316
-108
@@ -11,7 +11,6 @@ ENTITY pkt_gen IS
|
|||||||
Generic
|
Generic
|
||||||
(
|
(
|
||||||
f_sysclk : real := 100.0;
|
f_sysclk : real := 100.0;
|
||||||
TX_RAM_SIZE : natural := 2048;
|
|
||||||
PKT_DLY_MIN : real := 1.0E-6;
|
PKT_DLY_MIN : real := 1.0E-6;
|
||||||
PKT_DLY_MAX : real := 100.0E-6;
|
PKT_DLY_MAX : real := 100.0E-6;
|
||||||
PKT_SIZE_MIN : natural := 64;
|
PKT_SIZE_MIN : natural := 64;
|
||||||
@@ -22,7 +21,6 @@ ENTITY pkt_gen IS
|
|||||||
(
|
(
|
||||||
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
||||||
rst : in STD_LOGIC;
|
rst : in STD_LOGIC;
|
||||||
en : in STD_LOGIC;
|
|
||||||
mii_tx_clk : in STD_LOGIC;
|
mii_tx_clk : in STD_LOGIC;
|
||||||
mii_tx_en : out STD_LOGIC;
|
mii_tx_en : out STD_LOGIC;
|
||||||
mii_tx_er : out STD_LOGIC;
|
mii_tx_er : out STD_LOGIC;
|
||||||
@@ -40,96 +38,173 @@ ARCHITECTURE behavior OF pkt_gen IS
|
|||||||
signal pkt_nwords : word_ptr_t := X"0010";
|
signal pkt_nwords : word_ptr_t := X"0010";
|
||||||
signal pkt_delay : natural := natural(1.0*f_sysclk);
|
signal pkt_delay : natural := natural(1.0*f_sysclk);
|
||||||
|
|
||||||
signal fill_size : word_ptr_t;
|
|
||||||
signal fill_cnt : word_ptr_t;
|
|
||||||
signal fill_rdy : std_logic;
|
|
||||||
signal fill_set : std_logic;
|
|
||||||
signal fill_en : std_logic;
|
|
||||||
|
|
||||||
signal tx_packets : natural;
|
signal tx_packets : natural;
|
||||||
signal tx_bytes : natural;
|
signal tx_bytes : natural;
|
||||||
|
|
||||||
signal tx_ctrl_in : tx_ctrl_in_t;
|
signal mii_fifo_din : unsigned(35 downto 0);
|
||||||
signal tx_ctrl_out : tx_ctrl_out_t;
|
signal mii_fifo_dout : unsigned(35 downto 0);
|
||||||
signal tx_din : unsigned(31 downto 0);
|
signal mii_fifo_we : std_logic;
|
||||||
signal tx_din_vld : std_logic;
|
signal mii_fifo_re : std_logic;
|
||||||
|
signal mii_fifo_empty : std_logic;
|
||||||
|
signal mii_fifo_full : std_logic;
|
||||||
|
|
||||||
type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
|
signal xfer_size : word_ptr_t;
|
||||||
signal host_s, host_sn : host_state_t;
|
signal xfer_ptr : word_ptr_t;
|
||||||
|
signal xfer_cnt : word_ptr_t;
|
||||||
|
signal xfer_set : std_logic;
|
||||||
|
signal xfer_en : std_logic;
|
||||||
|
signal xfer_sync : unsigned(1 downto 0);
|
||||||
|
signal xfer_cnt_en : std_logic;
|
||||||
|
signal xfer_bsy : std_logic;
|
||||||
|
signal xfer_pre_rdy : std_logic;
|
||||||
|
signal uncommit_en : std_logic;
|
||||||
|
|
||||||
|
signal piso8_din : unsigned(31 downto 0);
|
||||||
|
signal piso8_din_be : unsigned(3 downto 0);
|
||||||
|
signal piso8_din_rdy : std_logic;
|
||||||
|
signal piso8_din_vld : std_logic;
|
||||||
|
|
||||||
|
signal piso8_dout : unsigned(7 downto 0);
|
||||||
|
signal piso8_dout_vld : std_logic;
|
||||||
|
signal piso8_dout_en : std_logic;
|
||||||
|
signal piso4_din_rdy : std_logic;
|
||||||
|
signal tx_en : std_logic;
|
||||||
|
|
||||||
|
subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
|
||||||
|
-- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
|
||||||
|
|
||||||
|
signal ifg_cnt : ifg_cnt_t;
|
||||||
|
signal ifg_idle : std_logic;
|
||||||
|
|
||||||
|
type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free);
|
||||||
|
signal xfer_s, xfer_sn : xfer_state_t;
|
||||||
|
|
||||||
|
type stream_state_t is (stream_init, stream_idle, stream_start, stream_preamble0, stream_preamble1, stream_active, stream_crc, stream_stop, stream_finish);
|
||||||
|
signal stream_s, stream_sn : stream_state_t;
|
||||||
|
|
||||||
|
type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
|
||||||
|
constant piso_byte_mask_rom : piso_byte_mask_array_t :=
|
||||||
|
(
|
||||||
|
"1111",
|
||||||
|
"1000",
|
||||||
|
"1100",
|
||||||
|
"1110"
|
||||||
|
);
|
||||||
|
|
||||||
|
signal preamble_en : std_logic;
|
||||||
|
signal preamble_addr : natural range 0 to 1;
|
||||||
|
type preamble_t is array (0 to 1) of unsigned(31 downto 0);
|
||||||
|
constant preamble : preamble_t :=
|
||||||
|
(
|
||||||
|
X"55555555",
|
||||||
|
X"555555D5"
|
||||||
|
);
|
||||||
|
|
||||||
begin
|
begin
|
||||||
|
|
||||||
|
mii_tx_er <= '0';
|
||||||
|
|
||||||
|
piso8_din <= preamble(preamble_addr) when preamble_en = '1' else mii_fifo_dout(31 downto 0);
|
||||||
|
piso8_din_be <= "1111" when preamble_en = '1' else mii_fifo_dout(35 downto 32);
|
||||||
|
|
||||||
|
mii_fifo_we <= xfer_bsy;
|
||||||
|
xfer_cnt_en <= xfer_bsy and not mii_fifo_full;
|
||||||
|
|
||||||
|
mii_fifo_din(35 downto 32) <= piso_byte_mask_rom(to_integer(pkt_nbytes(1 downto 0))) when xfer_pre_rdy = '1' else "1111";
|
||||||
|
mii_fifo_din(31 downto 0) <= pkt_data;
|
||||||
|
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
host_state_next:
|
-- Transfer stuff
|
||||||
|
------------------------------------------------------------------
|
||||||
|
xfer_state_next:
|
||||||
process(clk)
|
process(clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(clk) then
|
if rising_edge(clk) then
|
||||||
if rst = '1' then
|
if rst = '1' then
|
||||||
host_s <= host_init;
|
xfer_s <= xfer_init;
|
||||||
else
|
else
|
||||||
host_s <= host_sn;
|
xfer_s <= xfer_sn;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
host_state:
|
xfer_state:
|
||||||
process(host_s, tx_ctrl_out, pkt_nbytes, fill_rdy, en)
|
process(xfer_s, xfer_bsy, xfer_sync)
|
||||||
begin
|
begin
|
||||||
|
|
||||||
tx_ctrl_in.pkt_alloc_en <= '0';
|
uncommit_en <= '0';
|
||||||
tx_ctrl_in.pkt_commit_en <= '0';
|
xfer_set <= '0';
|
||||||
tx_ctrl_in.reset <= '0';
|
xfer_en <= '0';
|
||||||
tx_ctrl_in.Gbps_en <= '0';
|
|
||||||
tx_ctrl_in.tx_size <= pkt_nbytes;
|
|
||||||
fill_set <= '0';
|
|
||||||
fill_en <= '0';
|
|
||||||
|
|
||||||
host_sn <= host_s;
|
xfer_sn <= xfer_s;
|
||||||
|
|
||||||
case host_s is
|
case xfer_s is
|
||||||
|
|
||||||
when host_init =>
|
when xfer_init =>
|
||||||
if tx_ctrl_out.reset_busy = '0' then
|
xfer_sn <= xfer_idle;
|
||||||
host_sn <= host_idle;
|
|
||||||
|
when xfer_idle =>
|
||||||
|
xfer_sn <= xfer_setup;
|
||||||
|
|
||||||
|
when xfer_setup =>
|
||||||
|
xfer_set <= '1';
|
||||||
|
xfer_sn <= xfer_arm;
|
||||||
|
|
||||||
|
when xfer_arm =>
|
||||||
|
xfer_en <= '1';
|
||||||
|
xfer_sn <= xfer_active;
|
||||||
|
|
||||||
|
when xfer_active =>
|
||||||
|
xfer_en <= '1';
|
||||||
|
if xfer_bsy = '0' then
|
||||||
|
xfer_sn <= xfer_uncommit;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when host_idle =>
|
when xfer_uncommit =>
|
||||||
if tx_ctrl_out.pkt_alloc_req = '0' and en = '1' then
|
uncommit_en <= '1';
|
||||||
tx_ctrl_in.pkt_alloc_en <= '1';
|
xfer_sn <= xfer_free;
|
||||||
host_sn <= host_alloc;
|
|
||||||
|
when xfer_free =>
|
||||||
|
if xfer_sync(1) = '1' then
|
||||||
|
xfer_sn <= xfer_idle;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when host_alloc =>
|
|
||||||
if tx_ctrl_out.pkt_alloc_req = '0' then
|
|
||||||
if tx_ctrl_out.pkt_armed = '1' then
|
|
||||||
host_sn <= host_setup;
|
|
||||||
else
|
|
||||||
host_sn <= host_idle;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
|
|
||||||
when host_setup =>
|
|
||||||
fill_set <= '1';
|
|
||||||
host_sn <= host_fill;
|
|
||||||
|
|
||||||
when host_fill =>
|
|
||||||
fill_en <= '1';
|
|
||||||
if fill_rdy = '1' then
|
|
||||||
host_sn <= host_commit;
|
|
||||||
end if;
|
|
||||||
|
|
||||||
when host_commit =>
|
|
||||||
tx_ctrl_in.pkt_commit_en <= '1';
|
|
||||||
host_sn <= host_idle;
|
|
||||||
|
|
||||||
when others =>
|
when others =>
|
||||||
host_sn <= host_idle;
|
xfer_sn <= xfer_idle;
|
||||||
end case;
|
end case;
|
||||||
|
|
||||||
end process;
|
end process;
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
pkt_generator:
|
interframe_gap_ready:
|
||||||
|
process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
xfer_sync(1) <= xfer_sync(0);
|
||||||
|
xfer_sync(0) <= mii_fifo_empty;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
------------------------------------------------------------------
|
||||||
|
interframe_gap_counter:
|
||||||
|
process(mii_tx_clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(mii_tx_clk) then
|
||||||
|
ifg_idle <= '0';
|
||||||
|
if rst = '1' or piso8_dout_vld = '1' then
|
||||||
|
ifg_cnt <= ifg_cnt_t'high;
|
||||||
|
ifg_idle <= '1';
|
||||||
|
elsif ifg_cnt /= 0 then
|
||||||
|
ifg_cnt <= ifg_cnt - 1;
|
||||||
|
else
|
||||||
|
ifg_idle <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
------------------------------------------------------------------
|
||||||
|
pkt_params:
|
||||||
process(clk)
|
process(clk)
|
||||||
variable size : word_ptr_t;
|
variable size : word_ptr_t;
|
||||||
variable delay : natural;
|
variable delay : natural;
|
||||||
@@ -146,7 +221,7 @@ pkt_generator:
|
|||||||
seed2 := 12586901;
|
seed2 := 12586901;
|
||||||
tx_packets <= 0;
|
tx_packets <= 0;
|
||||||
tx_bytes <= 0;
|
tx_bytes <= 0;
|
||||||
elsif tx_ctrl_in.pkt_commit_en = '1' then
|
elsif uncommit_en = '1' then
|
||||||
uniform(seed1, seed2, krand);
|
uniform(seed1, seed2, krand);
|
||||||
size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length);
|
size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length);
|
||||||
delay := natural(1.0E6*f_sysclk*(PKT_DLY_MIN + (PKT_DLY_MAX-PKT_DLY_MIN)*krand));
|
delay := natural(1.0E6*f_sysclk*(PKT_DLY_MIN + (PKT_DLY_MAX-PKT_DLY_MIN)*krand));
|
||||||
@@ -164,44 +239,27 @@ pkt_generator:
|
|||||||
end process;
|
end process;
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
pkt_data_gen:
|
xfer_counter:
|
||||||
process(clk)
|
|
||||||
variable data : unsigned(7 downto 0);
|
|
||||||
begin
|
|
||||||
if rising_edge(clk) then
|
|
||||||
tx_din_vld <= fill_en;
|
|
||||||
if fill_set = '1' then
|
|
||||||
data := X"00";
|
|
||||||
tx_din <= X"03020100";
|
|
||||||
elsif fill_en = '1' then
|
|
||||||
tx_din(7 downto 0) <= data;
|
|
||||||
data := data + 1;
|
|
||||||
tx_din(15 downto 8) <= data;
|
|
||||||
data := data + 1;
|
|
||||||
tx_din(23 downto 16) <= data;
|
|
||||||
data := data + 1;
|
|
||||||
tx_din(31 downto 24) <= data;
|
|
||||||
data := data + 1;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
|
|
||||||
end process;
|
|
||||||
|
|
||||||
------------------------------------------------------------------
|
|
||||||
pkt_data_counter:
|
|
||||||
process(clk)
|
process(clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(clk) then
|
if rising_edge(clk) then
|
||||||
if fill_set = '1' then
|
if xfer_set = '1' then
|
||||||
fill_size <= (others => '0');
|
xfer_cnt <= pkt_nwords;
|
||||||
fill_rdy <= '0';
|
xfer_size <= (others => '0');
|
||||||
fill_cnt <= pkt_nwords;
|
xfer_bsy <= '0';
|
||||||
elsif fill_en = '1' then
|
xfer_pre_rdy <= '0';
|
||||||
if fill_cnt /= 0 then
|
elsif xfer_en = '1' then
|
||||||
fill_cnt <= fill_cnt - 1;
|
xfer_bsy <= '1';
|
||||||
fill_size <= fill_size + 1;
|
if xfer_cnt_en = '1' or xfer_bsy = '0' then
|
||||||
else
|
if xfer_cnt /= 1 then
|
||||||
fill_rdy <= '1';
|
xfer_cnt <= xfer_cnt - 1;
|
||||||
|
xfer_size <= xfer_size + 1;
|
||||||
|
else
|
||||||
|
xfer_pre_rdy <= '1';
|
||||||
|
end if;
|
||||||
|
if xfer_pre_rdy = '1' then
|
||||||
|
xfer_bsy <= '0';
|
||||||
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
@@ -209,26 +267,176 @@ pkt_data_counter:
|
|||||||
end process;
|
end process;
|
||||||
|
|
||||||
------------------------------------------------------------------
|
------------------------------------------------------------------
|
||||||
inst_emac_tx : entity work.emac_tx
|
pkt_data_gen:
|
||||||
|
process(clk)
|
||||||
|
variable data : unsigned(7 downto 0);
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
if xfer_set = '1' then
|
||||||
|
data := (others => '0');
|
||||||
|
elsif xfer_cnt_en = '1' or xfer_bsy = '0' then
|
||||||
|
pkt_data(7 downto 0) <= data;
|
||||||
|
data := data + 1;
|
||||||
|
pkt_data(15 downto 8) <= data;
|
||||||
|
data := data + 1;
|
||||||
|
pkt_data(23 downto 16) <= data;
|
||||||
|
data := data + 1;
|
||||||
|
pkt_data(31 downto 24) <= data;
|
||||||
|
data := data + 1;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
------------------------------------------------------------------
|
||||||
|
stream_state_next:
|
||||||
|
process(mii_tx_clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(mii_tx_clk) then
|
||||||
|
if rst = '1' then
|
||||||
|
stream_s <= stream_init;
|
||||||
|
else
|
||||||
|
stream_s <= stream_sn;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
stream_state:
|
||||||
|
process(stream_s, ifg_idle, mii_fifo_empty, piso8_din_rdy, piso8_dout_vld)
|
||||||
|
begin
|
||||||
|
|
||||||
|
piso8_din_vld <= '0';
|
||||||
|
mii_fifo_re <= '0';
|
||||||
|
preamble_en <= '0';
|
||||||
|
preamble_addr <= 0;
|
||||||
|
|
||||||
|
stream_sn <= stream_s;
|
||||||
|
|
||||||
|
case stream_s is
|
||||||
|
|
||||||
|
when stream_init =>
|
||||||
|
if mii_fifo_empty = '1' then
|
||||||
|
stream_sn <= stream_idle;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when stream_idle =>
|
||||||
|
if mii_fifo_empty = '0' and piso8_din_rdy = '1' then
|
||||||
|
stream_sn <= stream_start;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when stream_start =>
|
||||||
|
stream_sn <= stream_preamble0;
|
||||||
|
|
||||||
|
when stream_preamble0 =>
|
||||||
|
preamble_addr <= 0;
|
||||||
|
preamble_en <= '1';
|
||||||
|
piso8_din_vld <= '1';
|
||||||
|
if piso8_din_rdy = '1' then
|
||||||
|
stream_sn <= stream_preamble1;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when stream_preamble1 =>
|
||||||
|
preamble_addr <= 1;
|
||||||
|
preamble_en <= '1';
|
||||||
|
piso8_din_vld <= '1';
|
||||||
|
if piso8_din_rdy = '1' then
|
||||||
|
stream_sn <= stream_active;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when stream_active =>
|
||||||
|
piso8_din_vld <= not mii_fifo_empty;
|
||||||
|
mii_fifo_re <= piso8_din_rdy;
|
||||||
|
if mii_fifo_empty = '1' then
|
||||||
|
stream_sn <= stream_crc;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when stream_crc =>
|
||||||
|
stream_sn <= stream_stop;
|
||||||
|
|
||||||
|
when stream_stop =>
|
||||||
|
if piso8_dout_vld = '0' then
|
||||||
|
stream_sn <= stream_finish;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when stream_finish =>
|
||||||
|
if ifg_idle = '0' then
|
||||||
|
stream_sn <= stream_idle;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when others =>
|
||||||
|
stream_sn <= stream_idle;
|
||||||
|
end case;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
------------------------------------------------------------------
|
||||||
|
-- Instantiate synchronous FIFO
|
||||||
|
inst_mii_fifo: entity work.fifo_async
|
||||||
GENERIC MAP
|
GENERIC MAP
|
||||||
(
|
(
|
||||||
f_sysclk => f_sysclk,
|
addr_width => 4,
|
||||||
RAM_SIZE => TX_RAM_SIZE
|
data_width => mii_fifo_din'length,
|
||||||
|
do_last_read_update => true
|
||||||
|
)
|
||||||
|
PORT MAP
|
||||||
|
(
|
||||||
|
rst => rst,
|
||||||
|
clk_w => clk,
|
||||||
|
clk_r => mii_tx_clk,
|
||||||
|
we => mii_fifo_we,
|
||||||
|
re => mii_fifo_re,
|
||||||
|
fifo_full => mii_fifo_full,
|
||||||
|
fifo_empty => mii_fifo_empty,
|
||||||
|
fifo_afull => open,
|
||||||
|
fifo_aempty => open,
|
||||||
|
data_w => mii_fifo_din,
|
||||||
|
data_r => mii_fifo_dout
|
||||||
|
);
|
||||||
|
|
||||||
|
inst_piso : entity work.piso
|
||||||
|
GENERIC MAP
|
||||||
|
(
|
||||||
|
data_width_in => 32,
|
||||||
|
data_width_out => 8,
|
||||||
|
msb_first => true
|
||||||
)
|
)
|
||||||
PORT MAP
|
PORT MAP
|
||||||
(
|
(
|
||||||
clk => clk,
|
|
||||||
rst => rst,
|
rst => rst,
|
||||||
din_vld => tx_din_vld,
|
clk => mii_tx_clk,
|
||||||
din => tx_din,
|
din_vld => piso8_din_vld,
|
||||||
ctrl_in => tx_ctrl_in,
|
din_rdy => piso8_din_rdy,
|
||||||
ctrl_out => tx_ctrl_out,
|
din_be => piso8_din_be,
|
||||||
mii_tx_clk => mii_tx_clk,
|
din => piso8_din,
|
||||||
mii_tx_en => mii_tx_en,
|
dout_vld => piso8_dout_vld,
|
||||||
mii_tx_er => mii_tx_er,
|
dout_en => piso8_dout_en,
|
||||||
mii_tx => mii_tx
|
dout => piso8_dout
|
||||||
|
|
||||||
);
|
);
|
||||||
|
|
||||||
|
piso8_dout_en <= piso4_din_rdy and ifg_idle;
|
||||||
|
|
||||||
|
inst_piso_10mbps : entity work.piso
|
||||||
|
GENERIC MAP
|
||||||
|
(
|
||||||
|
data_width_in => 8,
|
||||||
|
data_width_out => 4,
|
||||||
|
msb_first => false
|
||||||
|
)
|
||||||
|
PORT MAP
|
||||||
|
(
|
||||||
|
rst => rst,
|
||||||
|
clk => mii_tx_clk,
|
||||||
|
din_vld => piso8_dout_vld,
|
||||||
|
din_rdy => piso4_din_rdy,
|
||||||
|
din_be => "11",
|
||||||
|
din => piso8_dout,
|
||||||
|
dout_vld => tx_en,
|
||||||
|
dout_en => '1',
|
||||||
|
dout => mii_tx(3 downto 0)
|
||||||
|
|
||||||
|
);
|
||||||
|
mii_tx_en <= tx_en;
|
||||||
|
mii_tx(7 downto 4) <= "0000";
|
||||||
|
|
||||||
end behavior;
|
end behavior;
|
||||||
|
|||||||
@@ -60,7 +60,7 @@ end process;
|
|||||||
process(clk)
|
process(clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(clk) then
|
if rising_edge(clk) then
|
||||||
din_vld_r <= din_vld and din_en;
|
din_vld_r <= din_vld;
|
||||||
if rst = '1' then
|
if rst = '1' then
|
||||||
out_en <= '0';
|
out_en <= '0';
|
||||||
elsif out_en = '0' then
|
elsif out_en = '0' then
|
||||||
@@ -87,15 +87,15 @@ begin
|
|||||||
if rising_edge(clk) then
|
if rising_edge(clk) then
|
||||||
if rst = '1' or pre_fin = '1' then
|
if rst = '1' or pre_fin = '1' then
|
||||||
if (msb_first) then
|
if (msb_first) then
|
||||||
shift_cnt_pipe <= (shift_cnt_pipe'left downto 1 => '0') & (din_en and din_vld);
|
shift_cnt_pipe <= (shift_cnt_pipe'left downto 1 => '0') & din_vld;
|
||||||
else
|
else
|
||||||
shift_cnt_pipe <= (din_en and din_vld) & (shift_cnt_pipe'left downto 1 => '0');
|
shift_cnt_pipe <= din_vld & (shift_cnt_pipe'left downto 1 => '0');
|
||||||
end if;
|
end if;
|
||||||
elsif din_vld = '1' or abort = '1' then
|
elsif din_vld = '1' or abort = '1' then
|
||||||
if (msb_first) then
|
if (msb_first) then
|
||||||
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & din_en;
|
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & din_vld;
|
||||||
else
|
else
|
||||||
shift_cnt_pipe <= din_en & shift_cnt_pipe(shift_cnt_pipe'left downto 1);
|
shift_cnt_pipe <= din_vld & shift_cnt_pipe(shift_cnt_pipe'left downto 1);
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
@@ -104,7 +104,7 @@ end process;
|
|||||||
process(clk)
|
process(clk)
|
||||||
begin
|
begin
|
||||||
if rising_edge(clk) then
|
if rising_edge(clk) then
|
||||||
if (din_en and din_vld) = '1' or abort = '1' then
|
if din_vld = '1' or abort = '1' then
|
||||||
if (msb_first) then
|
if (msb_first) then
|
||||||
shift_pipe <= shift_pipe(shift_pipe'left-data_width_in downto 0) & din;
|
shift_pipe <= shift_pipe(shift_pipe'left-data_width_in downto 0) & din;
|
||||||
else
|
else
|
||||||
|
|||||||
@@ -32,7 +32,7 @@ END tb_emac_top_jb;
|
|||||||
ARCHITECTURE behavior OF tb_emac_top_jb IS
|
ARCHITECTURE behavior OF tb_emac_top_jb IS
|
||||||
|
|
||||||
constant CLK_PERIOD : time := 10 ns;
|
constant CLK_PERIOD : time := 10 ns;
|
||||||
constant MII_CLK_PERIOD : time := 38.7 ns;
|
constant MII_CLK_PERIOD : time := 40.7 ns;
|
||||||
|
|
||||||
signal CLK : std_logic := '1';
|
signal CLK : std_logic := '1';
|
||||||
signal RST : std_logic := '1';
|
signal RST : std_logic := '1';
|
||||||
@@ -50,8 +50,6 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
|
|||||||
signal DAT_I : unsigned(31 downto 0) := (others => '-');
|
signal DAT_I : unsigned(31 downto 0) := (others => '-');
|
||||||
signal DAT_O : unsigned(31 downto 0) := (others => '-');
|
signal DAT_O : unsigned(31 downto 0) := (others => '-');
|
||||||
signal DAT_O_reg : unsigned(31 downto 0) := (others => '-');
|
signal DAT_O_reg : unsigned(31 downto 0) := (others => '-');
|
||||||
signal status_reg : unsigned(31 downto 0) := (others => '0');
|
|
||||||
signal size_reg : unsigned(31 downto 0) := (others => '0');
|
|
||||||
|
|
||||||
-- MII signals
|
-- MII signals
|
||||||
signal mii_rx_clk_board : std_logic := '1';
|
signal mii_rx_clk_board : std_logic := '1';
|
||||||
@@ -73,7 +71,7 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
|
|||||||
signal pktgen_tx : unsigned(7 downto 0);
|
signal pktgen_tx : unsigned(7 downto 0);
|
||||||
signal pktgen_tx_en : std_logic;
|
signal pktgen_tx_en : std_logic;
|
||||||
signal pktgen_tx_er : std_logic;
|
signal pktgen_tx_er : std_logic;
|
||||||
signal pktgen_en : std_logic := '0';
|
signal pktgen_rst : std_logic := '1';
|
||||||
|
|
||||||
signal dat_o_cnt_en : std_logic := '0';
|
signal dat_o_cnt_en : std_logic := '0';
|
||||||
signal dat_o_cnt_rst : std_logic := '1';
|
signal dat_o_cnt_rst : std_logic := '1';
|
||||||
@@ -83,12 +81,6 @@ ARCHITECTURE behavior OF tb_emac_top_jb IS
|
|||||||
type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free);
|
type emac_action_t is (emac_idle, emac_alloc, emac_write, emac_commit, emac_wait_data, emac_read, emac_free);
|
||||||
signal emac_action : emac_action_t;
|
signal emac_action : emac_action_t;
|
||||||
|
|
||||||
constant RX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0000";
|
|
||||||
constant RX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_0004";
|
|
||||||
constant TX_STATUS_REG_ADDR : unsigned(31 downto 0) := X"0000_0008";
|
|
||||||
constant TX_SIZE_REG_ADDR : unsigned(31 downto 0) := X"0000_000C";
|
|
||||||
constant DATA_REG_ADDR : unsigned(31 downto 0) := X"0000_0010";
|
|
||||||
|
|
||||||
BEGIN
|
BEGIN
|
||||||
|
|
||||||
inst_emac_top_jb : entity work.emac_top_jb
|
inst_emac_top_jb : entity work.emac_top_jb
|
||||||
@@ -140,8 +132,7 @@ inst_pkt_gen : entity work.pkt_gen
|
|||||||
PORT MAP
|
PORT MAP
|
||||||
(
|
(
|
||||||
clk => CLK,
|
clk => CLK,
|
||||||
rst => RST,
|
rst => pktgen_rst,
|
||||||
en => pktgen_en,
|
|
||||||
mii_tx_clk => mii_tx_clk_board,
|
mii_tx_clk => mii_tx_clk_board,
|
||||||
mii_tx_en => pktgen_tx_en,
|
mii_tx_en => pktgen_tx_en,
|
||||||
mii_tx_er => pktgen_tx_er,
|
mii_tx_er => pktgen_tx_er,
|
||||||
@@ -205,45 +196,36 @@ STIMULUS: process
|
|||||||
emac_action <= emac_alloc;
|
emac_action <= emac_alloc;
|
||||||
CYC_I <= '1';
|
CYC_I <= '1';
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
DAT_I <= to_unsigned(size, 32);
|
DAT_I <= to_unsigned(size, 16) & X"55AA";
|
||||||
STB_I <= '1';
|
STB_I <= '1';
|
||||||
WE_I <= '1';
|
WE_I <= '1';
|
||||||
ADDR_I <= TX_SIZE_REG_ADDR;
|
ADDR_I <= X"0000_0004";
|
||||||
|
|
||||||
check_alloc_ok:
|
check_alloc_ok:
|
||||||
while(true) loop
|
while(true) loop
|
||||||
|
|
||||||
-- set alloc request
|
-- set alloc request
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
WE_I <= '0';
|
DAT_I <= X"0200_0000";
|
||||||
STB_I <= '1';
|
|
||||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
|
||||||
STB_I <= '0';
|
|
||||||
wait until rising_edge(CLK) and ACK_O = '1';
|
|
||||||
status_reg <= DAT_O;
|
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
|
||||||
DAT_I <= X"0002_0000" or (not X"0001_0000" and status_reg);
|
|
||||||
STB_I <= '1';
|
STB_I <= '1';
|
||||||
WE_I <= '1';
|
WE_I <= '1';
|
||||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
ADDR_I <= X"0000_0000";
|
||||||
|
|
||||||
check_bsy:
|
check_bsy:
|
||||||
while (true) loop
|
while (true) loop
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
WE_I <= '0';
|
WE_I <= '0';
|
||||||
STB_I <= '1';
|
STB_I <= '1';
|
||||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
ADDR_I <= X"0000_0000";
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
STB_I <= '0';
|
STB_I <= '0';
|
||||||
wait until rising_edge(CLK) and ACK_O = '1';
|
wait until rising_edge(CLK) and ACK_O = '1';
|
||||||
status_reg <= DAT_O;
|
|
||||||
wait until rising_edge(CLK);
|
wait until rising_edge(CLK);
|
||||||
if status_reg(17) = '0' then
|
if DAT_O_reg(25) = '0' then
|
||||||
exit check_bsy;
|
exit check_bsy;
|
||||||
end if;
|
end if;
|
||||||
end loop;
|
end loop;
|
||||||
if status_reg(16) = '1' then
|
if DAT_O_reg(24) = '1' then
|
||||||
exit check_alloc_ok;
|
exit check_alloc_ok;
|
||||||
end if;
|
end if;
|
||||||
end loop;
|
end loop;
|
||||||
@@ -262,18 +244,10 @@ STIMULUS: process
|
|||||||
-- set free request
|
-- set free request
|
||||||
CYC_I <= '1';
|
CYC_I <= '1';
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
WE_I <= '0';
|
DAT_I <= X"0100_0000";
|
||||||
STB_I <= '1';
|
|
||||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
|
||||||
STB_I <= '0';
|
|
||||||
wait until rising_edge(CLK) and ACK_O = '1';
|
|
||||||
status_reg <= DAT_O;
|
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
|
||||||
DAT_I <= X"0001_0000" or (not X"0002_0000" and status_reg);
|
|
||||||
STB_I <= '1';
|
STB_I <= '1';
|
||||||
WE_I <= '1';
|
WE_I <= '1';
|
||||||
ADDR_I <= TX_STATUS_REG_ADDR;
|
ADDR_I <= X"0000_0000";
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
STB_I <= '0';
|
STB_I <= '0';
|
||||||
WE_I <= '0';
|
WE_I <= '0';
|
||||||
@@ -298,7 +272,7 @@ STIMULUS: process
|
|||||||
CYC_I <= '1';
|
CYC_I <= '1';
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
data := X"00";
|
data := X"00";
|
||||||
ADDR_I <= DATA_REG_ADDR;
|
ADDR_I <= X"0000_0008";
|
||||||
WE_I <= '1';
|
WE_I <= '1';
|
||||||
for i in 1 to num_words loop
|
for i in 1 to num_words loop
|
||||||
STB_I <= '1';
|
STB_I <= '1';
|
||||||
@@ -336,13 +310,12 @@ STIMULUS: process
|
|||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
WE_I <= '0';
|
WE_I <= '0';
|
||||||
STB_I <= '1';
|
STB_I <= '1';
|
||||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
ADDR_I <= X"0000_0000";
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
STB_I <= '0';
|
STB_I <= '0';
|
||||||
wait until rising_edge(CLK) and ACK_O = '1';
|
wait until rising_edge(CLK) and ACK_O = '1';
|
||||||
status_reg <= DAT_O;
|
|
||||||
wait until rising_edge(CLK);
|
wait until rising_edge(CLK);
|
||||||
if status_reg(17) = '1' and status_reg(16) = '1' then
|
if DAT_O_reg(16) = '1' then
|
||||||
exit check_data_avail;
|
exit check_data_avail;
|
||||||
end if;
|
end if;
|
||||||
end loop;
|
end loop;
|
||||||
@@ -353,28 +326,19 @@ STIMULUS: process
|
|||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
WE_I <= '0';
|
WE_I <= '0';
|
||||||
STB_I <= '1';
|
STB_I <= '1';
|
||||||
ADDR_I <= RX_SIZE_REG_ADDR;
|
ADDR_I <= X"0000_0004";
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
STB_I <= '0';
|
STB_I <= '0';
|
||||||
wait until rising_edge(CLK) and ACK_O = '1';
|
wait until rising_edge(CLK) and ACK_O = '1';
|
||||||
size_reg <= DAT_O;
|
|
||||||
wait until rising_edge(CLK);
|
wait until rising_edge(CLK);
|
||||||
|
|
||||||
-- set packet request
|
-- set packet request
|
||||||
CYC_I <= '1';
|
CYC_I <= '1';
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
WE_I <= '0';
|
DAT_I <= X"0001_0000";
|
||||||
STB_I <= '1';
|
|
||||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
|
||||||
STB_I <= '0';
|
|
||||||
wait until rising_edge(CLK) and ACK_O = '1';
|
|
||||||
status_reg <= DAT_O;
|
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
|
||||||
DAT_I <= X"0002_0000" or (not X"0001_0000" and status_reg);
|
|
||||||
STB_I <= '1';
|
STB_I <= '1';
|
||||||
WE_I <= '1';
|
WE_I <= '1';
|
||||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
ADDR_I <= X"0000_0000";
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
STB_I <= '0';
|
STB_I <= '0';
|
||||||
WE_I <= '0';
|
WE_I <= '0';
|
||||||
@@ -383,7 +347,7 @@ STIMULUS: process
|
|||||||
-- Read RX data
|
-- Read RX data
|
||||||
size := size_in;
|
size := size_in;
|
||||||
if (size_in = 0) then
|
if (size_in = 0) then
|
||||||
size := to_integer(size_reg(15 downto 0));
|
size := to_integer(DAT_O_reg(15 downto 0));
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
if (size mod 4) = 0 then
|
if (size mod 4) = 0 then
|
||||||
@@ -396,7 +360,8 @@ STIMULUS: process
|
|||||||
dat_o_cnt_en <= '1';
|
dat_o_cnt_en <= '1';
|
||||||
CYC_I <= '1';
|
CYC_I <= '1';
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
ADDR_I <= DATA_REG_ADDR;
|
data := X"00";
|
||||||
|
ADDR_I <= X"0000_0008";
|
||||||
WE_I <= '0';
|
WE_I <= '0';
|
||||||
STB_I <= '1';
|
STB_I <= '1';
|
||||||
for i in 1 to num_words loop
|
for i in 1 to num_words loop
|
||||||
@@ -418,18 +383,10 @@ STIMULUS: process
|
|||||||
-- set free request
|
-- set free request
|
||||||
CYC_I <= '1';
|
CYC_I <= '1';
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
WE_I <= '0';
|
DAT_I <= X"0002_0000";
|
||||||
STB_I <= '1';
|
|
||||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
|
||||||
STB_I <= '0';
|
|
||||||
wait until rising_edge(CLK) and ACK_O = '1';
|
|
||||||
status_reg <= DAT_O;
|
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
|
||||||
DAT_I <= X"0001_0000" or (not X"0002_0000" and status_reg);
|
|
||||||
STB_I <= '1';
|
STB_I <= '1';
|
||||||
WE_I <= '1';
|
WE_I <= '1';
|
||||||
ADDR_I <= RX_STATUS_REG_ADDR;
|
ADDR_I <= X"0000_0000";
|
||||||
wait until rising_edge(CLK) and SRDY_O = '1';
|
wait until rising_edge(CLK) and SRDY_O = '1';
|
||||||
STB_I <= '0';
|
STB_I <= '0';
|
||||||
WE_I <= '0';
|
WE_I <= '0';
|
||||||
@@ -569,15 +526,15 @@ STIMULUS: process
|
|||||||
wait for 6000*CLK_PERIOD;
|
wait for 6000*CLK_PERIOD;
|
||||||
|
|
||||||
loop_back_en <= '0';
|
loop_back_en <= '0';
|
||||||
pktgen_en <= '1';
|
pktgen_rst <= '0';
|
||||||
pkt_count <= 0;
|
pkt_count <= 0;
|
||||||
for i in 1 to 500 loop
|
for i in 1 to 500 loop
|
||||||
wait for 50 us;
|
wait for 10 us;
|
||||||
emac_read (0);
|
emac_read (0);
|
||||||
emac_free;
|
emac_free;
|
||||||
pkt_count <= pkt_count + 1;
|
pkt_count <= pkt_count + 1;
|
||||||
end loop;
|
end loop;
|
||||||
pktgen_en <= '0';
|
pktgen_rst <= '1';
|
||||||
emac_read (0);
|
emac_read (0);
|
||||||
emac_free;
|
emac_free;
|
||||||
|
|
||||||
|
|||||||
Reference in New Issue
Block a user