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base: jens/vhdl:EMAC_R0
Branches Tags
jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
..
compare: jens/vhdl:EMAC_R1
Branches Tags
jens/vhdl:master jens/vhdl:BRANCH_MIPS_R14 jens/vhdl:BRANCH_MIPS_TLB jens/vhdl:trunk jens/vhdl:EMAC_BRANCH_DMA jens/vhdl:BRANCH_TEST_2 jens/vhdl:BRANCH_TEST
jens/vhdl:MIPS_PRE_R14 jens/vhdl:MIPS_R13 jens/vhdl:MIPS_R12 jens/vhdl:EMAC_R01 jens/vhdl:EMAC_R4 jens/vhdl:EMAC_R3 jens/vhdl:EMAC_R2 jens/vhdl:EMAC_R1 jens/vhdl:EMAC_R0 jens/vhdl:JCPU_R4 jens/vhdl:MIPS_R11 jens/vhdl:MIPS_R10b jens/vhdl:MIPS_R10a jens/vhdl:MIPS_R10 jens/vhdl:MIPS_R9 jens/vhdl:R8 jens/vhdl:R7 jens/vhdl:R6 jens/vhdl:R5 jens/vhdl:R4 jens/vhdl:R3 jens/vhdl:R2 jens/vhdl:R1
7 Commits
EMAC_R0 .. EMAC_R1
Author SHA1 Message Date
jens d19b90ebc6 This commit was manufactured by cvs2svn to create tag 'EMAC_R1'. 
git-svn-id: http://moon:8086/svn/vhdl/tags/EMAC_R1@856 cc03376c-175c-47c8-b038-4cd826a8556b
 2010-04-04 09:56:38 +00:00
jens bd64cab371 - minor changes 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@855 cc03376c-175c-47c8-b038-4cd826a8556b
 2010-04-04 09:56:37 +00:00
jens c6e0de57ec - minor fix 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@854 cc03376c-175c-47c8-b038-4cd826a8556b
 2010-04-04 09:55:51 +00:00
jens e8deef86a6 - added preamble genration 
- simplified design
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@853 cc03376c-175c-47c8-b038-4cd826a8556b
 2010-04-04 09:55:22 +00:00
jens 4d41635f19 - added MAC own address register 
- added MAC check and promiscious mode
- added new flags
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@852 cc03376c-175c-47c8-b038-4cd826a8556b
 2010-04-04 09:54:27 +00:00
jens d7a1ee94e6 - added preamble sync and preamble stripping 
- added MAC own address register
- added MAC check and promiscious mode
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@851 cc03376c-175c-47c8-b038-4cd826a8556b
 2010-04-04 09:53:55 +00:00
jens bd90e641cf - added ethernet MAC 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@850 cc03376c-175c-47c8-b038-4cd826a8556b
 2010-03-30 10:22:46 +00:00
9 changed files with 917 additions and 430 deletions
Expand all files Collapse all files
lib/emac/sim/tb_emac_jb.wdo
+127 -2
View File
@@ -16,18 +16,143 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/dat_o
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_clk add wave -noupdate -format Logic /tb_emac_jb/mii_rx_clk
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_rx add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_rx
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_tx
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_dv add wave -noupdate -format Logic /tb_emac_jb/mii_rx_dv
add wave -noupdate -format Logic /tb_emac_jb/mii_rx_er add wave -noupdate -format Logic /tb_emac_jb/mii_rx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/mii_tx
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_en add wave -noupdate -format Logic /tb_emac_jb/mii_tx_en
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_er add wave -noupdate -format Logic /tb_emac_jb/mii_tx_er
add wave -noupdate -format Logic /tb_emac_jb/mii_crs add wave -noupdate -format Logic /tb_emac_jb/mii_crs
add wave -noupdate -format Logic /tb_emac_jb/mii_col add wave -noupdate -format Logic /tb_emac_jb/mii_col
add wave -noupdate -format Logic /tb_emac_jb/mii_gtx_clk add wave -noupdate -format Logic /tb_emac_jb/mii_gtx_clk
add wave -noupdate -divider {Ethernet MAC}
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal /tb_emac_jb/emac_action
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_err
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_flush_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_flush_rdy
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_free_en
add wave -noupdate -format Literal -radix unsigned /tb_emac_jb/inst_emac_jb/tx_nwords_free
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_flush_ptr
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_cnt_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_cnt_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_cnt
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_ptr_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fill_ptr_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fill_ptr
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_alloc_base
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_alloc_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_ok
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_req_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_commit_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_req
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_alloc_ack
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_en_a
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_en_b
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/host_tx_s
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_out_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_out_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_in_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_in_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_addr_b
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_we_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_out_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_out_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_tag_in_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_data_in_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_ram_addr_a
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_ram_we_a
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_free_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_ptr_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_ptr_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_ptr
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_cnt_set
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_cnt_adv
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_cnt
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_rdy
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_xfer_en
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_data_vld
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_tag
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_remain
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/xfer_odd
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/xfer_remain_en
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/xfer_tx_s
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/piso_din_be
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/piso_din_rdy
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_xfer_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_we
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_full
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_din
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_empty
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_re add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/tx_fifo_re
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_dout add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/tx_fifo_dout
add wave -noupdate -format Logic /tb_emac_jb/mii_tx_clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/host_tx_size
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/host_data_we
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_emac_jb/host_data_reg
add wave -noupdate -format Literal /tb_emac_jb/inst_emac_jb/inter_frame_gap_cnt
add wave -noupdate -format Logic /tb_emac_jb/inst_emac_jb/inter_frame_gap_rdy
add wave -noupdate -divider Shifter
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Literal /tb_emac_jb/shift_sa
add wave -noupdate -format Logic /tb_emac_jb/shift_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/shift_din
add wave -noupdate -format Logic /tb_emac_jb/shift_dout_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/shift_dout
add wave -noupdate -divider PiSo
add wave -noupdate -format Logic /tb_emac_jb/clk
add wave -noupdate -format Logic /tb_emac_jb/piso_din_vld
add wave -noupdate -format Logic /tb_emac_jb/piso_din_rdy
add wave -noupdate -format Literal /tb_emac_jb/piso_din_be
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso_din
add wave -noupdate -format Logic /tb_emac_jb/piso_dout_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso_dout
add wave -noupdate -format Logic /tb_emac_jb/inst_piso/pre_fin
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso/din_reg
add wave -noupdate -format Literal /tb_emac_jb/inst_piso/din_be_reg
add wave -noupdate -format Logic /tb_emac_jb/inst_piso/din_vld_reg
add wave -noupdate -format Literal /tb_emac_jb/inst_piso/shift_cnt_pipe
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso/shift_pipe
add wave -noupdate -format Literal /tb_emac_jb/inst_piso/vld_pipe
add wave -noupdate -format Logic /tb_emac_jb/piso2_din_vld
add wave -noupdate -format Logic /tb_emac_jb/piso2_din_rdy
add wave -noupdate -format Literal /tb_emac_jb/piso2_din_be
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso2_din
add wave -noupdate -format Logic /tb_emac_jb/piso2_dout_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/piso2_dout
add wave -noupdate -format Logic /tb_emac_jb/piso2_enable
add wave -noupdate -format Logic /tb_emac_jb/inst_piso2/pre_fin
add wave -noupdate -format Logic /tb_emac_jb/inst_piso2/rdy
add wave -noupdate -format Literal /tb_emac_jb/inst_piso2/shift_cnt_pipe
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_piso2/shift_pipe
add wave -noupdate -format Literal /tb_emac_jb/inst_piso2/vld_pipe
add wave -noupdate -divider SiPo
add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/clk
add wave -noupdate -format Logic /tb_emac_jb/sipo_enable
add wave -noupdate -format Logic /tb_emac_jb/sipo_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo_din
add wave -noupdate -format Logic /tb_emac_jb/sipo_dout_en
add wave -noupdate -format Logic /tb_emac_jb/sipo_dout_vld
add wave -noupdate -format Literal /tb_emac_jb/sipo_dout_be
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo_dout
add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/pre_fin
add wave -noupdate -format Logic /tb_emac_jb/inst_sipo/abort
add wave -noupdate -format Literal /tb_emac_jb/inst_sipo/shift_cnt_pipe
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_sipo/shift_pipe
add wave -noupdate -format Logic /tb_emac_jb/sipo2_enable
add wave -noupdate -format Logic /tb_emac_jb/sipo2_rst
add wave -noupdate -format Logic /tb_emac_jb/sipo2_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo2_din
add wave -noupdate -format Logic /tb_emac_jb/sipo2_dout_en
add wave -noupdate -format Logic /tb_emac_jb/sipo2_dout_vld
add wave -noupdate -format Literal /tb_emac_jb/sipo2_dout_be
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/sipo2_dout
add wave -noupdate -format Literal /tb_emac_jb/inst_sipo2/shift_cnt_pipe
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_jb/inst_sipo2/shift_pipe
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {12999093 ps} 0} WaveRestoreCursors {{Cursor 1} {19622640 ps} 0} {{Cursor 2} {121551751 ps} 0}
configure wave -namecolwidth 150 configure wave -namecolwidth 150
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
lib/emac/sim/tb_emac_top_jb.wdo
+112 -67
View File
@@ -27,125 +27,170 @@ add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_crs
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_col add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_col
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/dat_o_reg add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/dat_o_reg
add wave -noupdate -format Literal /tb_emac_top_jb/emac_action add wave -noupdate -format Literal /tb_emac_top_jb/emac_action
add wave -noupdate -format Logic /tb_emac_top_jb/dat_o_cnt_rst
add wave -noupdate -format Literal /tb_emac_top_jb/dat_o_cnt
add wave -noupdate -format Literal /tb_emac_top_jb/pkt_count
add wave -noupdate -divider {Packet generator}
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_packets
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/tx_bytes
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_pkt_gen/pkt_data
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nbytes
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_pkt_gen/pkt_nwords
add wave -noupdate -format Literal /tb_emac_top_jb/inst_pkt_gen/pkt_delay
add wave -noupdate -divider RX add wave -noupdate -divider RX
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/rst
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout_vld
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/dout
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_in add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_in
add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out add wave -noupdate -format Literal -radix hexadecimal -expand /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ctrl_out
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_clk add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_full add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_dv
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_we add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx_er
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_rx
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_crs
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_col
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_din add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_din
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_empty
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_re
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_dout add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_we
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_re
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_empty
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mii_fifo_full
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_din add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_dout add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_we add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_we
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_re add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_re
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_empty add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_empty
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_full add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/cmd_fifo_full
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/flush_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fill_ptr add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fill_ptr
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fill_ptr_set add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/commit_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/fill_ptr_adv add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_limit
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_full add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ram_full
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_base add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_base
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_size add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_size
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr_set add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr_set
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr_adv add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_ptr_adv
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt_set add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt_set
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt_adv add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_cnt_adv
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_rdy add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_rdy
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_tag add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_a
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_remain add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_odd add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_remain_en add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_dout_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_en_b
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_din_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout_be
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout_vld
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_dout_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_32bit_rst
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_rst
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout_vld
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count_reg add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/byte_count_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_reg add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_set add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_full
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_clr add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_empty
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_ack add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_we
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/word_count_vld add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_re
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/uncommit_en add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_dout add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/size_fifo_dout
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_dout_be add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/host_s
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_dout_vld add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/xfer_s
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/mii_rx_dv add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/stream_s
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_b add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rst
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_b add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_bsy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_we_a add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_ok
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/ram_addr_a add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/preamble_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_ok
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_rst
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_num_ok
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_addr
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout_vld
add wave -noupdate -format Literal -radix unsigned /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/mac_chk_cnt
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_rx/sipo_8bit_dout
add wave -noupdate -divider TX add wave -noupdate -divider TX
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/clk
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/rst
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/din
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_in add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_in
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_out add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ctrl_out
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_din add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_clk
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_dout add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_we add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx_er
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_tx
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_empty
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_full
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_din add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_dout add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_we add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_we
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_re add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_re
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_empty add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_empty
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_full add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/cmd_fifo_full
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/flush_en add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_pre_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/commit_en add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_bsy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_set
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_base
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_size add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_size
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_a add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_remain
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt_set
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_cnt_adv
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr_set
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_ptr_adv
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ok add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ok
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_req add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_req
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ack add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_ack
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/nwords_free add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/nwords_free
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_base
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_size add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_size
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/alloc_en add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_alloc_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/free_en add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mem_free_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/commit_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/uncommit_en add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/uncommit_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/fill_remain add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_bsy
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_size add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_size
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr_set add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_ptr_adv add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_en
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt_set add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_set
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_cnt_adv add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_rdy add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_a
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_tag add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_a
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_remain add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_odd add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_a
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_remain_en add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_en_b
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_we_b
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_b add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_addr_b
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso_din_be add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_din_b
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso_din_rdy add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ram_dout_b
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/data_vld add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_cnt
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/inter_frame_gap_cnt add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/ifg_idle
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/inter_frame_gap_rdy add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_be
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_rdy
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_din_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_vld
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/piso8_dout_en
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_dout
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_we
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_re
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_empty
add wave -noupdate -format Logic /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/mii_fifo_full
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/stream_s
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/host_s
add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s add wave -noupdate -format Literal /tb_emac_top_jb/inst_emac_top_jb/inst_emac_tx/xfer_s
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {65284974 ps} 0} WaveRestoreCursors {{Cursor 1} {18401055846 ps} 0} {{Cursor 2} {49999375873 ps} 0}
configure wave -namecolwidth 150 configure wave -namecolwidth 150
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
@@ -159,4 +204,4 @@ configure wave -gridperiod 100
configure wave -griddelta 40 configure wave -griddelta 40
configure wave -timeline 1 configure wave -timeline 1
update update
WaveRestoreZoom {0 ps} {262500 ns} WaveRestoreZoom {3250153138 ps} {28560670888 ps}
lib/emac/src/emac_rx.vhd
+177 -56
View File
@@ -44,8 +44,8 @@ ARCHITECTURE behavior OF emac_rx IS
signal mii_fifo_empty : std_logic; signal mii_fifo_empty : std_logic;
signal mii_fifo_full : std_logic; signal mii_fifo_full : std_logic;
signal cmd_fifo_din : unsigned(31 downto 0); signal cmd_fifo_din : unsigned(2*word_ptr_t'length+2 downto 0);
signal cmd_fifo_dout : unsigned(31 downto 0); signal cmd_fifo_dout : unsigned(2*word_ptr_t'length+2 downto 0);
signal cmd_fifo_we : std_logic; signal cmd_fifo_we : std_logic;
signal cmd_fifo_re : std_logic; signal cmd_fifo_re : std_logic;
signal cmd_fifo_empty : std_logic; signal cmd_fifo_empty : std_logic;
@@ -67,6 +67,7 @@ ARCHITECTURE behavior OF emac_rx IS
signal xfer_cnt_set : std_logic; signal xfer_cnt_set : std_logic;
signal xfer_cnt_adv : std_logic; signal xfer_cnt_adv : std_logic;
signal xfer_rdy : std_logic; signal xfer_rdy : std_logic;
signal xfer_vld : std_logic;
signal ram_en_a : std_logic; signal ram_en_a : std_logic;
signal ram_we_a : std_logic; signal ram_we_a : std_logic;
@@ -102,48 +103,98 @@ ARCHITECTURE behavior OF emac_rx IS
signal size_fifo_empty : std_logic; signal size_fifo_empty : std_logic;
signal size_fifo_we : std_logic; signal size_fifo_we : std_logic;
signal size_fifo_re : std_logic; signal size_fifo_re : std_logic;
signal size_fifo_din : unsigned(2*word_ptr_t'length-1 downto 0); signal size_fifo_din : unsigned(2*word_ptr_t'length+2 downto 0);
signal size_fifo_dout : unsigned(2*word_ptr_t'length-1 downto 0); signal size_fifo_dout : unsigned(2*word_ptr_t'length+2 downto 0);
signal reset_pipe : unsigned(31 downto 0); signal reset_pipe : unsigned(31 downto 0);
signal preamble_rst : std_logic;
signal preamble_rdy : std_logic;
signal preamble_bsy : std_logic;
signal preamble_OK : std_logic;
signal mac_chk_rdy : std_logic;
signal mac_chk_BC : std_logic;
signal mac_chk_OK : std_logic;
signal mac_chk_rst : std_logic;
signal mac_chk_num_OK : natural range 0 to 6;
signal mac_chk_num_BC : natural range 0 to 6;
signal mac_chk_cnt : natural range 0 to 5;
signal mac_chk_addr : mac_addr_t;
type host_state_t is (host_init, host_flush, host_idle); type host_state_t is (host_init, host_flush, host_idle);
signal host_s, host_sn : host_state_t; signal host_s, host_sn : host_state_t;
type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_active, xfer_drop, xfer_commit, xfer_free); type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_active, xfer_drop, xfer_commit, xfer_free);
signal xfer_s, xfer_sn : xfer_state_t; signal xfer_s, xfer_sn : xfer_state_t;
type stream_state_t is (stream_init, stream_idle, stream_start, stream_active, stream_stop, stream_finish); type stream_state_t is (stream_init, stream_reset, stream_idle, stream_active, stream_stop, stream_finish);
signal stream_s, stream_sn : stream_state_t; signal stream_s, stream_sn : stream_state_t;
alias cmd_mac_ok_in is cmd_fifo_din(cmd_fifo_din'left);
alias cmd_bcast_in is cmd_fifo_din(cmd_fifo_din'left-1);
alias cmd_invalid_in is cmd_fifo_din(cmd_fifo_din'left-2);
alias cmd_nbytes_in is cmd_fifo_din(word_ptr_t'length-1 downto 0);
alias cmd_base_in is cmd_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length);
alias cmd_mac_ok_out is cmd_fifo_dout(cmd_fifo_dout'left);
alias cmd_bcast_out is cmd_fifo_dout(cmd_fifo_dout'left-1);
alias cmd_invalid_out is cmd_fifo_dout(cmd_fifo_dout'left-2);
alias cmd_nbytes_out is cmd_fifo_dout(word_ptr_t'length-1 downto 0);
alias cmd_base_out is cmd_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length);
alias stream_mac_ok_in is size_fifo_din(size_fifo_din'left);
alias stream_broadcast_in is size_fifo_din(size_fifo_din'left-1);
alias stream_badcrc_in is size_fifo_din(size_fifo_din'left-2);
alias stream_nbytes_in is size_fifo_din(word_ptr_t'length-1 downto 0);
alias stream_nwords_in is size_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length);
alias stream_mac_ok_out is size_fifo_dout(size_fifo_dout'left);
alias stream_broadcast_out is size_fifo_dout(size_fifo_dout'left-1);
alias stream_badcrc_out is size_fifo_dout(size_fifo_dout'left-2);
alias stream_nbytes_out is size_fifo_dout(word_ptr_t'length-1 downto 0);
alias stream_nwords_out is size_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length);
begin begin
ctrl_out.rx_size <= cmd_fifo_dout(31 downto 16); ctrl_out.rx_size <= resize(cmd_nbytes_out, 16);
ctrl_out.pkt_avail <= not cmd_fifo_empty; ctrl_out.pkt_avail <= not cmd_fifo_empty;
ctrl_out.rx_er <= mii_rx_er; ctrl_out.rx_er <= mii_rx_er;
ctrl_out.reset_busy <= reset_en; ctrl_out.reset_busy <= reset_en;
ctrl_out.pkt_bcast <= cmd_bcast_out;
ctrl_out.pkt_mac_match <= cmd_mac_ok_out;
dout <= ram_dout_a; dout <= ram_dout_a;
mii_fifo_din <= sipo_32bit_dout; mii_fifo_din <= sipo_32bit_dout;
mii_fifo_we <= sipo_32bit_dout_vld; mii_fifo_we <= word_count_en and sipo_32bit_dout_vld;
ram_en_a <= '1'; ram_en_a <= '1';
ram_din_a <= (others => '-'); ram_din_a <= (others => '-');
ram_addr_a <= fill_ptr; ram_addr_a <= fill_ptr;
ram_we_a <= '0'; ram_we_a <= '0';
ram_en_b <= '1'; ram_en_b <= '1';
ram_din_b <= mii_fifo_dout; ram_din_b <= mii_fifo_dout;
ram_addr_b <= xfer_ptr; ram_addr_b <= xfer_ptr;
ram_we_b <= xfer_ptr_adv; ram_we_b <= xfer_ptr_adv;
cmd_fifo_we <= commit_en; cmd_fifo_we <= commit_en;
cmd_fifo_re <= ctrl_in.pkt_free_en; cmd_fifo_re <= ctrl_in.pkt_free_en;
cmd_fifo_din <= resize(size_fifo_dout(word_ptr_t'length-1 downto 0), 16) & resize(xfer_base, 16);
cmd_mac_ok_in <= stream_mac_ok_out;
cmd_bcast_in <= stream_broadcast_out;
cmd_invalid_in <= stream_badcrc_out;
cmd_nbytes_in <= stream_nbytes_out;
cmd_base_in <= xfer_base;
size_fifo_din <= word_count & byte_count_reg; stream_nbytes_in <= byte_count_reg;
reset_en <= reset_pipe(reset_pipe'left); stream_nwords_in <= word_count;
stream_mac_ok_in <= mac_chk_OK;
stream_broadcast_in <= mac_chk_BC;
stream_badcrc_in <= '0';
reset_en <= reset_pipe(reset_pipe'left);
------------------------------------------------------------------ ------------------------------------------------------------------
reset_gen: reset_gen:
@@ -167,7 +218,7 @@ fill_pointer:
if rising_edge(clk) then if rising_edge(clk) then
dout_vld <= ctrl_in.pkt_read_en; dout_vld <= ctrl_in.pkt_read_en;
if ctrl_in.pkt_req_en = '1' then if ctrl_in.pkt_req_en = '1' then
fill_ptr <= resize(cmd_fifo_dout(15 downto 0), word_ptr_t'length); fill_ptr <= cmd_base_out;
elsif ctrl_in.pkt_read_en = '1' then elsif ctrl_in.pkt_read_en = '1' then
fill_ptr <= fill_ptr + 1; fill_ptr <= fill_ptr + 1;
end if; end if;
@@ -190,7 +241,7 @@ xfer_state_next:
end process; end process;
xfer_state: xfer_state:
process(xfer_s, size_fifo_empty, mii_fifo_empty, xfer_rdy, xfer_ram_full) process(xfer_s, size_fifo_empty, mii_fifo_empty, xfer_rdy, xfer_vld, xfer_ram_full)
begin begin
commit_en <= '0'; commit_en <= '0';
@@ -241,7 +292,7 @@ xfer_state:
when xfer_free => when xfer_free =>
size_fifo_re <= '1'; size_fifo_re <= '1';
commit_en <= not xfer_ram_full; commit_en <= not xfer_ram_full and xfer_vld;
xfer_sn <= xfer_idle; xfer_sn <= xfer_idle;
when others => when others =>
@@ -274,7 +325,7 @@ xfer_limit_register:
if cmd_fifo_empty = '1' then if cmd_fifo_empty = '1' then
xfer_ram_limit <= xfer_base - 1; xfer_ram_limit <= xfer_base - 1;
else else
xfer_ram_limit <= resize(cmd_fifo_dout(15 downto 0), word_ptr_t'length) - 1; xfer_ram_limit <= cmd_base_out - 1;
end if; end if;
end if; end if;
end if; end if;
@@ -302,8 +353,10 @@ xfer_counter:
if rising_edge(clk) then if rising_edge(clk) then
if xfer_cnt_set = '1' then if xfer_cnt_set = '1' then
xfer_rdy <= '0'; xfer_rdy <= '0';
elsif xfer_size = size_fifo_dout(size_fifo_dout'left downto word_ptr_t'length) then xfer_vld <= '0';
elsif xfer_size = stream_nwords_out then
xfer_rdy <= '1'; xfer_rdy <= '1';
xfer_vld <= stream_mac_ok_out or stream_broadcast_out or ctrl_in.promiscious;
end if; end if;
if xfer_cnt_set = '1' then if xfer_cnt_set = '1' then
xfer_size <= (others => '0'); xfer_size <= (others => '0');
@@ -374,6 +427,65 @@ word_counter:
end if; end if;
end process; end process;
preamble_sync_logic:
process(mii_rx_clk)
begin
if rising_edge(mii_rx_clk) then
if preamble_rst = '1' then
preamble_rdy <= '0';
preamble_bsy <= '0';
preamble_OK <= '0';
elsif sipo_8bit_dout_vld = '1' then
if preamble_bsy = '1' then
if sipo_8bit_dout = X"D5" then
preamble_OK <= '1';
end if;
end if;
if sipo_8bit_dout /= X"55" then
preamble_bsy <= '0';
preamble_rdy <= preamble_bsy;
else
preamble_bsy <= '1';
end if;
end if;
end if;
end process;
mac_check_logic:
process(mii_rx_clk)
begin
if rising_edge(mii_rx_clk) then
if mac_chk_rst = '1' then
mac_chk_rdy <= '0';
mac_chk_OK <= '0';
mac_chk_BC <= '0';
mac_chk_cnt <= 0;
mac_chk_num_OK <= 0;
mac_chk_num_BC <= 0;
mac_chk_addr <= ctrl_in.mac_addr;
elsif mac_chk_rdy = '1' then
if mac_chk_num_OK = 6 then
mac_chk_OK <= '1';
end if;
if mac_chk_num_BC = 6 then
mac_chk_BC <= '1';
end if;
elsif sipo_8bit_dout_vld = '1' then
if sipo_8bit_dout = mac_chk_addr(mac_chk_cnt) then
mac_chk_num_OK <= mac_chk_num_OK + 1;
end if;
if sipo_8bit_dout = X"FF" then
mac_chk_num_BC <= mac_chk_num_BC + 1;
end if;
if mac_chk_cnt /= 5 then
mac_chk_cnt <= mac_chk_cnt + 1;
else
mac_chk_rdy <= '1';
end if;
end if;
end if;
end process;
------------------------------------------------------------------ ------------------------------------------------------------------
stream_state_next: stream_state_next:
process(mii_rx_clk) process(mii_rx_clk)
@@ -388,59 +500,68 @@ stream_state_next:
end process; end process;
stream_state: stream_state:
process(stream_s, sipo_8bit_dout_en, sipo_32bit_dout_en) process(stream_s, reset_en, sipo_8bit_dout_en, sipo_8bit_dout, sipo_32bit_dout_en, sipo_32bit_dout_vld, preamble_rdy, preamble_OK)
begin begin
sipo_32bit_en <= '0'; sipo_32bit_en <= '0';
sipo_32bit_rst <= '0'; sipo_32bit_rst <= reset_en;
sipo_8bit_rst <= '0'; sipo_8bit_rst <= reset_en;
word_count_en <= sipo_32bit_dout_en; word_count_en <= '0';
byte_count_en <= sipo_8bit_dout_en; byte_count_en <= '0';
size_fifo_we <= '0'; size_fifo_we <= '0';
preamble_rst <= reset_en;
mac_chk_rst <= reset_en;
sipo_32bit_en <= sipo_8bit_dout_en;
stream_sn <= stream_s; stream_sn <= stream_s;
case stream_s is case stream_s is
when stream_init => when stream_init =>
sipo_32bit_rst <= '1';
sipo_8bit_rst <= '1';
if sipo_8bit_dout_en = '0' then if sipo_8bit_dout_en = '0' then
stream_sn <= stream_idle; stream_sn <= stream_reset;
end if; end if;
when stream_idle => when stream_reset =>
sipo_32bit_en <= sipo_8bit_dout_en; sipo_32bit_rst <= '1';
if sipo_8bit_dout_en = '1' then sipo_8bit_rst <= '1';
stream_sn <= stream_start; preamble_rst <= '1';
end if; stream_sn <= stream_idle;
when stream_start =>
sipo_32bit_en <= sipo_8bit_dout_en;
if sipo_8bit_dout_en = '1' then
stream_sn <= stream_active;
end if;
when stream_idle =>
sipo_32bit_en <= '0';
if preamble_rdy = '1' then
stream_sn <= stream_init;
if preamble_OK = '1' then
byte_count_en <= '1';
mac_chk_rst <= '1';
sipo_32bit_rst <= '1';
stream_sn <= stream_active;
end if;
end if;
when stream_active => when stream_active =>
sipo_32bit_en <= sipo_8bit_dout_en; word_count_en <= sipo_32bit_dout_en;
byte_count_en <= sipo_8bit_dout_en;
if sipo_8bit_dout_en = '0' then if sipo_8bit_dout_en = '0' then
stream_sn <= stream_stop; stream_sn <= stream_stop;
sipo_8bit_rst <= '1'; sipo_8bit_rst <= '1';
end if; end if;
when stream_stop => when stream_stop =>
sipo_32bit_en <= '0'; word_count_en <= sipo_32bit_dout_en;
byte_count_en <= sipo_8bit_dout_en;
if sipo_32bit_dout_en = '0' then if sipo_32bit_dout_en = '0' then
stream_sn <= stream_finish; stream_sn <= stream_finish;
end if; end if;
when stream_finish => when stream_finish =>
size_fifo_we <= '1'; size_fifo_we <= '1';
stream_sn <= stream_idle; stream_sn <= stream_init;
sipo_32bit_rst <= '1';
when others => when others =>
stream_sn <= stream_idle; stream_sn <= stream_init;
end case; end case;
end process; end process;
@@ -452,7 +573,7 @@ inst_cmd_fifo: entity work.fifo_sync
( (
addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words) addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words)
data_width => cmd_fifo_din'length, data_width => cmd_fifo_din'length,
do_last_read_update => true do_last_read_update => false
) )
PORT MAP PORT MAP
( (
@@ -515,7 +636,7 @@ inst_size_fifo: entity work.fifo_async
GENERIC MAP GENERIC MAP
( (
addr_width => 1, addr_width => 1,
data_width => 2*word_ptr_t'length, data_width => size_fifo_din'length,
do_last_read_update => true do_last_read_update => true
) )
PORT MAP PORT MAP
lib/emac/src/emac_top_jb.vhd
+32 -7
View File
@@ -84,10 +84,12 @@ registers_write:
rx_ctrl_in.pkt_req_en <= '0'; rx_ctrl_in.pkt_req_en <= '0';
rx_ctrl_in.reset <= '0'; rx_ctrl_in.reset <= '0';
if RST_I = '1' then if RST_I = '1' then
rx_int_en <= '0'; rx_int_en <= '0';
tx_int_en <= '0'; tx_int_en <= '0';
tx_ctrl_in.tx_er <= '0'; tx_ctrl_in.tx_er <= '0';
tx_ctrl_in.tx_size <= (others => '0'); tx_ctrl_in.tx_size <= (others => '0');
rx_ctrl_in.mac_addr <= (X"03", X"02", X"01", X"00", X"07", X"06");
rx_ctrl_in.promiscious <= '1';
elsif (STB_I and CYC_I and WE_I) = '1' then elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(5 downto 2) is case ADDR_I(5 downto 2) is
@@ -101,6 +103,7 @@ registers_write:
rx_ctrl_in.pkt_req_en <= DAT_I(16); rx_ctrl_in.pkt_req_en <= DAT_I(16);
tx_int_en <= DAT_I(5); tx_int_en <= DAT_I(5);
rx_int_en <= DAT_I(4); rx_int_en <= DAT_I(4);
rx_ctrl_in.promiscious <= DAT_I(3);
when "0001" => when "0001" =>
tx_ctrl_in.tx_size <= DAT_I(31 downto 16); tx_ctrl_in.tx_size <= DAT_I(31 downto 16);
@@ -109,6 +112,16 @@ registers_write:
tx_din_vld <= '1'; tx_din_vld <= '1';
tx_din <= DAT_I; tx_din <= DAT_I;
when "0100" =>
rx_ctrl_in.mac_addr(0) <= DAT_I(31 downto 24);
rx_ctrl_in.mac_addr(1) <= DAT_I(23 downto 16);
rx_ctrl_in.mac_addr(2) <= DAT_I(15 downto 8);
rx_ctrl_in.mac_addr(3) <= DAT_I(7 downto 0);
when "0101" =>
rx_ctrl_in.mac_addr(4) <= DAT_I(31 downto 24);
rx_ctrl_in.mac_addr(5) <= DAT_I(23 downto 16);
when others => null; when others => null;
end case; end case;
end if; end if;
@@ -129,18 +142,22 @@ registers_read:
ACK_O <= ready; ACK_O <= ready;
DAT_O <= (others => '0'); DAT_O <= (others => '0');
DAT_O(31) <= tx_ctrl_in.tx_er; DAT_O(31) <= tx_ctrl_in.tx_er;
DAT_O(30) <= mii_rx_er; DAT_O(30) <= mii_rx_er; -- remove that
DAT_O(29) <= mii_col; DAT_O(29) <= mii_col; -- remove that
DAT_O(28) <= mii_crs; DAT_O(28) <= mii_crs; -- remove that
DAT_O(27) <= tx_ctrl_out.reset_busy; DAT_O(27) <= tx_ctrl_out.reset_busy;
DAT_O(26) <= tx_ctrl_out.pkt_done; DAT_O(26) <= tx_ctrl_out.pkt_done;
DAT_O(25) <= tx_ctrl_out.pkt_alloc_req; DAT_O(25) <= tx_ctrl_out.pkt_alloc_req;
DAT_O(24) <= tx_ctrl_out.pkt_armed; DAT_O(24) <= tx_ctrl_out.pkt_armed;
DAT_O(23) <= rx_ctrl_out.reset_busy; DAT_O(23) <= rx_ctrl_out.reset_busy;
DAT_O(19) <= rx_ctrl_out.pkt_bcast;
DAT_O(18) <= rx_ctrl_out.pkt_mac_match;
DAT_O(17) <= rx_ctrl_out.pkt_lost; DAT_O(17) <= rx_ctrl_out.pkt_lost;
DAT_O(16) <= rx_ctrl_out.pkt_avail; DAT_O(16) <= rx_ctrl_out.pkt_avail;
DAT_O(5) <= tx_int_en; DAT_O(5) <= tx_int_en;
DAT_O(4) <= rx_int_en; DAT_O(4) <= rx_int_en;
DAT_O(3) <= rx_ctrl_in.promiscious;
when "0001" => when "0001" =>
ACK_O <= '1'; ACK_O <= '1';
DAT_O <= tx_ctrl_out.tx_size & rx_ctrl_out.rx_size; DAT_O <= tx_ctrl_out.tx_size & rx_ctrl_out.rx_size;
@@ -148,6 +165,14 @@ registers_read:
when "0010" => when "0010" =>
rx_ctrl_in.pkt_read_en <= '1'; rx_ctrl_in.pkt_read_en <= '1';
when "0100" =>
ACK_O <= '1';
DAT_O <= rx_ctrl_in.mac_addr(0) & rx_ctrl_in.mac_addr(1) & rx_ctrl_in.mac_addr(2) & rx_ctrl_in.mac_addr(3);
when "0101" =>
ACK_O <= '1';
DAT_O <= rx_ctrl_in.mac_addr(4) & rx_ctrl_in.mac_addr(5) & X"0000";
when others => null; when others => null;
end case; end case;
end if; end if;
lib/emac/src/emac_tx.vhd
+219 -138
View File
@@ -41,8 +41,8 @@ ARCHITECTURE behavior OF emac_tx IS
signal mii_fifo_empty : std_logic; signal mii_fifo_empty : std_logic;
signal mii_fifo_full : std_logic; signal mii_fifo_full : std_logic;
signal cmd_fifo_din : unsigned(35 downto 0); signal cmd_fifo_din : unsigned(2*word_ptr_t'length-1 downto 0);
signal cmd_fifo_dout : unsigned(35 downto 0); signal cmd_fifo_dout : unsigned(2*word_ptr_t'length-1 downto 0);
signal cmd_fifo_we : std_logic; signal cmd_fifo_we : std_logic;
signal cmd_fifo_re : std_logic; signal cmd_fifo_re : std_logic;
signal cmd_fifo_empty : std_logic; signal cmd_fifo_empty : std_logic;
@@ -54,12 +54,12 @@ ARCHITECTURE behavior OF emac_tx IS
signal fill_size : word_ptr_t; signal fill_size : word_ptr_t;
signal fill_cnt : word_ptr_t; signal fill_cnt : word_ptr_t;
signal fill_ptr : word_ptr_t; signal fill_ptr : word_ptr_t;
signal fill_rdy : std_logic; signal fill_pre_rdy : std_logic;
signal fill_cnt_set : std_logic; signal fill_bsy : std_logic;
signal fill_cnt_adv : std_logic;
signal fill_ptr_set : std_logic;
signal fill_ptr_adv : std_logic;
signal fill_remain : unsigned(1 downto 0); signal fill_remain : unsigned(1 downto 0);
signal fill_set : std_logic;
signal fill_en : std_logic;
signal fill_cnt_en : std_logic;
signal alloc_OK : std_logic; signal alloc_OK : std_logic;
signal alloc_req : std_logic; signal alloc_req : std_logic;
@@ -67,59 +67,61 @@ ARCHITECTURE behavior OF emac_tx IS
signal alloc_size : word_ptr_t; signal alloc_size : word_ptr_t;
signal alloc_remain : unsigned(1 downto 0); signal alloc_remain : unsigned(1 downto 0);
signal nwords_free : word_ptr_t;
signal mem_alloc_en : std_logic;
signal mem_free_en : std_logic;
signal commit_en : std_logic; signal commit_en : std_logic;
signal uncommit_en : std_logic; signal uncommit_en : std_logic;
signal mem_alloc_en : std_logic;
signal mem_free_en : std_logic;
signal nwords_free : word_ptr_t;
signal xfer_size : word_ptr_t; signal xfer_size : word_ptr_t;
signal xfer_ptr : word_ptr_t; signal xfer_ptr : word_ptr_t;
signal xfer_cnt : word_ptr_t; signal xfer_cnt : word_ptr_t;
signal xfer_ptr_set : std_logic; signal xfer_set : std_logic;
signal xfer_ptr_adv : std_logic; signal xfer_en : std_logic;
signal xfer_cnt_set : std_logic; signal xfer_sync : unsigned(1 downto 0);
signal xfer_cnt_adv : std_logic; signal xfer_cnt_en : std_logic;
signal xfer_rdy : std_logic; signal xfer_bsy : std_logic;
signal xfer_tag : unsigned(3 downto 0);
signal xfer_remain : unsigned(1 downto 0);
signal xfer_odd : std_logic;
signal xfer_remain_en : std_logic;
signal ram_en_a : std_logic; signal ram_en_a : std_logic;
signal ram_we_a : std_logic; signal ram_we_a : std_logic;
signal ram_addr_a : word_ptr_t; signal ram_addr_a : word_ptr_t;
signal ram_din_a : unsigned(31 downto 0); signal ram_din_a : unsigned(35 downto 0);
signal ram_dout_a : unsigned(31 downto 0); signal ram_dout_a : unsigned(35 downto 0);
signal ram_en_b : std_logic; signal ram_en_b : std_logic;
signal ram_addr_b : word_ptr_t; signal ram_addr_b : word_ptr_t;
signal ram_din_b : unsigned(31 downto 0); signal ram_din_b : unsigned(35 downto 0);
signal ram_dout_b : unsigned(31 downto 0); signal ram_dout_b : unsigned(35 downto 0);
signal piso_din_be : unsigned(3 downto 0); signal piso8_din : unsigned(31 downto 0);
signal piso_din_rdy : std_logic; signal piso8_din_be : unsigned(3 downto 0);
signal data_vld : std_logic; signal piso8_din_rdy : std_logic;
signal piso8_din_vld : std_logic;
signal piso_dout : unsigned(7 downto 0); signal piso8_dout : unsigned(7 downto 0);
signal piso_dout_vld : std_logic; signal piso8_dout_vld : std_logic;
signal piso_10mbps_din_rdy : std_logic; signal piso8_dout_en : std_logic;
signal tx_en : std_logic;
signal reset_pipe : unsigned(31 downto 0); signal piso4_dout_vld : std_logic;
signal piso4_din_rdy : std_logic;
signal piso4_dout : unsigned(3 downto 0);
signal reset_pipe : unsigned(31 downto 0);
subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
-- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps -- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
signal ifg_cnt : ifg_cnt_t;
signal ifg_rdy : std_logic; signal ifg_cnt : ifg_cnt_t;
signal ifg_idle : std_logic; signal ifg_idle : std_logic;
type host_state_t is (host_init, host_flush, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit); type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
signal host_s, host_sn : host_state_t; signal host_s, host_sn : host_state_t;
type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free, xfer_wait); type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free);
signal xfer_s, xfer_sn : xfer_state_t; signal xfer_s, xfer_sn : xfer_state_t;
type stream_state_t is (stream_init, stream_idle, stream_start, stream_preamble0, stream_preamble1, stream_active, stream_crc, stream_stop, stream_finish);
signal stream_s, stream_sn : stream_state_t;
type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0); type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
constant piso_byte_mask_rom : piso_byte_mask_array_t := constant piso_byte_mask_rom : piso_byte_mask_array_t :=
( (
@@ -129,7 +131,16 @@ ARCHITECTURE behavior OF emac_tx IS
"1110" "1110"
); );
signal preamble_en : std_logic;
signal preamble_addr : natural range 0 to 1;
type preamble_t is array (0 to 1) of unsigned(31 downto 0);
constant preamble : preamble_t :=
(
X"55555555",
X"555555D5"
);
begin begin
ctrl_out.pkt_alloc_req <= alloc_req; ctrl_out.pkt_alloc_req <= alloc_req;
@@ -138,26 +149,29 @@ begin
mii_tx_er <= ctrl_in.tx_er; mii_tx_er <= ctrl_in.tx_er;
ram_en_a <= '1'; ram_en_a <= din_vld;
ram_we_a <= fill_ptr_adv; ram_we_a <= fill_bsy;
ram_din_a <= din; ram_din_a(31 downto 0) <= din;
ram_din_a(35 downto 32) <= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111";
ram_addr_a <= fill_ptr; ram_addr_a <= fill_ptr;
piso_din_be <= mii_fifo_dout(35 downto 32); mii_fifo_din <= ram_dout_b;
mii_fifo_re <= piso_din_rdy;
data_vld <= not mii_fifo_empty;
mii_fifo_din(35 downto 32) <= piso_byte_mask_rom(to_integer(xfer_remain)) when xfer_remain_en = '1' else "1111";
mii_fifo_din(31 downto 0) <= ram_dout_b;
piso8_din <= preamble(preamble_addr) when preamble_en = '1' else mii_fifo_dout(31 downto 0);
piso8_din_be <= "1111" when preamble_en = '1' else mii_fifo_dout(35 downto 32);
cmd_fifo_we <= commit_en; cmd_fifo_we <= commit_en;
cmd_fifo_re <= uncommit_en; cmd_fifo_re <= uncommit_en;
cmd_fifo_din <= fill_remain & "01" & resize(fill_size, 16) & resize(fill_base, 16); cmd_fifo_din <= fill_size & fill_base;
ram_en_b <= not mii_fifo_full; ram_en_b <= not mii_fifo_full;
ram_addr_b <= xfer_ptr; ram_addr_b <= xfer_ptr;
xfer_tag <= cmd_fifo_dout(35 downto 32);
reset_en <= reset_pipe(reset_pipe'left); reset_en <= reset_pipe(reset_pipe'left);
mii_fifo_we <= xfer_bsy;
xfer_cnt_en <= xfer_bsy and not mii_fifo_full;
fill_cnt_en <= fill_bsy and din_vld;
------------------------------------------------------------------ ------------------------------------------------------------------
reset_gen: reset_gen:
process(clk) process(clk)
@@ -185,13 +199,11 @@ host_state_next:
end process; end process;
host_state: host_state:
process(host_s, alloc_OK, fill_rdy, din_vld, ctrl_in.pkt_commit_en, alloc_req) process(host_s, alloc_OK, fill_bsy, ctrl_in.pkt_commit_en, alloc_req)
begin begin
fill_cnt_set <= '0'; fill_set <= '0';
fill_cnt_adv <= '0'; fill_en <= '0';
fill_ptr_set <= '0';
fill_ptr_adv <= '0';
commit_en <= '0'; commit_en <= '0';
alloc_ack <= '0'; alloc_ack <= '0';
mem_alloc_en <= '0'; mem_alloc_en <= '0';
@@ -217,18 +229,16 @@ host_state:
end if; end if;
when host_setup => when host_setup =>
fill_set <= '1';
host_sn <= host_arm; host_sn <= host_arm;
fill_cnt_set <= '1';
fill_ptr_set <= '1';
when host_arm => when host_arm =>
fill_en <= '1';
alloc_ack <= '1'; alloc_ack <= '1';
fill_cnt_adv <= '1';
host_sn <= host_fill; host_sn <= host_fill;
when host_fill => when host_fill =>
fill_cnt_adv <= din_vld; fill_en <= '1';
fill_ptr_adv <= not fill_rdy and din_vld;
if alloc_req = '1' then if alloc_req = '1' then
host_sn <= host_alloc; host_sn <= host_alloc;
elsif ctrl_in.pkt_commit_en = '1' then elsif ctrl_in.pkt_commit_en = '1' then
@@ -265,10 +275,6 @@ alloc_request_logic:
ctrl_out.tx_size <= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16); ctrl_out.tx_size <= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16);
elsif alloc_ack = '1' then elsif alloc_ack = '1' then
alloc_req <= '0'; alloc_req <= '0';
if alloc_OK = '1' then
fill_size <= alloc_size;
fill_remain <= alloc_remain;
end if;
end if; end if;
end if; end if;
end process; end process;
@@ -333,14 +339,23 @@ fill_counter:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if fill_cnt_set = '1' then if fill_set = '1' then
fill_rdy <= '0'; fill_bsy <= '0';
fill_cnt <= fill_size; fill_pre_rdy <= '0';
elsif fill_cnt_adv = '1' then fill_cnt <= alloc_size;
if fill_cnt /= 0 then fill_size <= alloc_size;
fill_cnt <= fill_cnt - 1; fill_remain <= alloc_remain;
else elsif fill_en = '1' then
fill_rdy <= '1'; fill_bsy <= '1';
if fill_cnt_en = '1' or fill_bsy = '0' then
if fill_cnt /= 1 then
fill_cnt <= fill_cnt - 1;
else
fill_pre_rdy <= '1';
end if;
if fill_pre_rdy = '1' then
fill_bsy <= '0';
end if;
end if; end if;
end if; end if;
end if; end if;
@@ -350,9 +365,9 @@ fill_pointer:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if fill_ptr_set = '1' then if fill_set = '1' then
fill_ptr <= fill_base; fill_ptr <= fill_base;
elsif fill_ptr_adv = '1' then elsif fill_cnt_en = '1' then
fill_ptr <= fill_ptr + 1; fill_ptr <= fill_ptr + 1;
end if; end if;
end if; end if;
@@ -374,15 +389,11 @@ xfer_state_next:
end process; end process;
xfer_state: xfer_state:
process(xfer_s, cmd_fifo_empty, xfer_odd, xfer_rdy, ifg_rdy, mem_alloc_en, mii_fifo_full) process(xfer_s, cmd_fifo_empty, xfer_bsy, xfer_sync, mem_alloc_en)
begin begin
xfer_cnt_set <= '0'; xfer_set <= '0';
xfer_cnt_adv <= '0'; xfer_en <= '0';
xfer_ptr_set <= '0';
xfer_ptr_adv <= '0';
xfer_remain_en <= '0';
mii_fifo_we <= '0';
mem_free_en <= '0'; mem_free_en <= '0';
uncommit_en <= '0'; uncommit_en <= '0';
@@ -399,32 +410,17 @@ xfer_state:
end if; end if;
when xfer_setup => when xfer_setup =>
xfer_ptr_set <= '1'; xfer_set <= '1';
xfer_cnt_set <= '1';
xfer_sn <= xfer_arm; xfer_sn <= xfer_arm;
when xfer_arm => when xfer_arm =>
xfer_cnt_adv <= '1'; xfer_en <= '1';
xfer_sn <= xfer_wait; xfer_sn <= xfer_active;
when xfer_wait =>
if ifg_rdy = '1' then
xfer_sn <= xfer_active;
xfer_cnt_adv <= '1';
xfer_ptr_adv <= '1';
end if;
when xfer_active => when xfer_active =>
mii_fifo_we <= '1'; xfer_en <= '1';
xfer_cnt_adv <= not mii_fifo_full; if xfer_bsy = '0' then
xfer_ptr_adv <= not mii_fifo_full; xfer_sn <= xfer_uncommit;
if xfer_rdy = '1' then
xfer_remain_en <= xfer_odd;
xfer_cnt_adv <= '0';
xfer_ptr_adv <= '0';
if mii_fifo_full = '0' then
xfer_sn <= xfer_uncommit;
end if;
end if; end if;
when xfer_uncommit => when xfer_uncommit =>
@@ -435,7 +431,7 @@ xfer_state:
end if; end if;
when xfer_free => when xfer_free =>
if ifg_rdy = '0' then if xfer_sync(1) = '1' then
xfer_sn <= xfer_idle; xfer_sn <= xfer_idle;
end if; end if;
@@ -450,7 +446,8 @@ interframe_gap_ready:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
ifg_rdy <= ifg_idle; xfer_sync(1) <= xfer_sync(0);
xfer_sync(0) <= mii_fifo_empty;
end if; end if;
end process; end process;
@@ -460,8 +457,9 @@ interframe_gap_counter:
begin begin
if rising_edge(mii_tx_clk) then if rising_edge(mii_tx_clk) then
ifg_idle <= '0'; ifg_idle <= '0';
if reset_en = '1' or tx_en = '1' then if reset_en = '1' or piso8_dout_vld = '1' then
ifg_cnt <= ifg_cnt_t'high; ifg_cnt <= ifg_cnt_t'high;
ifg_idle <= '1';
elsif ifg_cnt /= 0 then elsif ifg_cnt /= 0 then
ifg_cnt <= ifg_cnt - 1; ifg_cnt <= ifg_cnt - 1;
else else
@@ -475,16 +473,19 @@ xfer_counter:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if xfer_cnt_set = '1' then xfer_bsy <= '0';
if xfer_set = '1' then
xfer_cnt <= cmd_fifo_dout(cmd_fifo_dout'left downto word_ptr_t'length);
xfer_size <= (others => '0'); xfer_size <= (others => '0');
xfer_rdy <= '0'; elsif xfer_en = '1' then
xfer_cnt <= cmd_fifo_dout(xfer_ptr'left+16 downto 16); xfer_bsy <= '1';
elsif xfer_cnt_adv = '1' then if xfer_cnt_en = '1' or xfer_bsy = '0' then
if xfer_cnt /= 0 then if xfer_cnt /= 0 then
xfer_cnt <= xfer_cnt - 1; xfer_cnt <= xfer_cnt - 1;
xfer_size <= xfer_size + 1; xfer_size <= xfer_size + 1;
else else
xfer_rdy <= '1'; xfer_bsy <= '0';
end if;
end if; end if;
end if; end if;
end if; end if;
@@ -495,26 +496,104 @@ xfer_pointer:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if xfer_ptr_set = '1' then if xfer_set = '1' then
xfer_ptr <= cmd_fifo_dout(xfer_ptr'left downto 0); xfer_ptr <= cmd_fifo_dout(xfer_ptr'left downto 0);
xfer_remain <= xfer_tag(3 downto 2); elsif xfer_en = '1' then
xfer_odd <= '0'; if xfer_bsy = '0' or xfer_cnt_en = '1' then
if xfer_tag(3 downto 2) /= "00" then xfer_ptr <= xfer_ptr + 1;
xfer_odd <= '1';
end if; end if;
elsif xfer_ptr_adv = '1' then
xfer_ptr <= xfer_ptr + 1;
end if; end if;
end if; end if;
end process; end process;
------------------------------------------------------------------
stream_state_next:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
if reset_en = '1' then
stream_s <= stream_init;
else
stream_s <= stream_sn;
end if;
end if;
end process;
stream_state:
process(stream_s, ifg_idle, mii_fifo_empty, piso8_din_rdy, piso8_dout_vld)
begin
piso8_din_vld <= '0';
mii_fifo_re <= '0';
preamble_en <= '0';
preamble_addr <= 0;
stream_sn <= stream_s;
case stream_s is
when stream_init =>
if mii_fifo_empty = '1' then
stream_sn <= stream_idle;
end if;
when stream_idle =>
if mii_fifo_empty = '0' and piso8_din_rdy = '1' then
stream_sn <= stream_start;
end if;
when stream_start =>
stream_sn <= stream_preamble0;
when stream_preamble0 =>
preamble_addr <= 0;
preamble_en <= '1';
piso8_din_vld <= '1';
if piso8_din_rdy = '1' then
stream_sn <= stream_preamble1;
end if;
when stream_preamble1 =>
preamble_addr <= 1;
preamble_en <= '1';
piso8_din_vld <= '1';
if piso8_din_rdy = '1' then
stream_sn <= stream_active;
end if;
when stream_active =>
piso8_din_vld <= not mii_fifo_empty;
mii_fifo_re <= piso8_din_rdy;
if mii_fifo_empty = '1' then
stream_sn <= stream_crc;
end if;
when stream_crc =>
stream_sn <= stream_stop;
when stream_stop =>
if piso8_dout_vld = '0' then
stream_sn <= stream_finish;
end if;
when stream_finish =>
if ifg_idle = '0' then
stream_sn <= stream_idle;
end if;
when others =>
stream_sn <= stream_idle;
end case;
end process;
------------------------------------------------------------------ ------------------------------------------------------------------
inst_ram : entity work.dpram_1w1r inst_ram : entity work.dpram_1w1r
GENERIC MAP GENERIC MAP
( (
addr_width => RAM_ADDR_WIDTH, addr_width => RAM_ADDR_WIDTH,
data_width => 32 data_width => ram_din_a'length
) )
PORT MAP PORT MAP
( (
@@ -574,7 +653,7 @@ inst_mii_fifo: entity work.fifo_async
data_r => mii_fifo_dout data_r => mii_fifo_dout
); );
inst_piso : entity work.piso inst_piso8 : entity work.piso
GENERIC MAP GENERIC MAP
( (
data_width_in => 32, data_width_in => 32,
@@ -585,17 +664,19 @@ inst_piso : entity work.piso
( (
rst => reset_en, rst => reset_en,
clk => mii_tx_clk, clk => mii_tx_clk,
din_vld => data_vld, din_vld => piso8_din_vld,
din_rdy => piso_din_rdy, din_rdy => piso8_din_rdy,
din_be => piso_din_be, din_be => piso8_din_be,
din => mii_fifo_dout(31 downto 0), din => piso8_din,
dout_vld => piso_dout_vld, dout_vld => piso8_dout_vld,
dout_en => piso_10mbps_din_rdy, dout_en => piso8_dout_en,
dout => piso_dout dout => piso8_dout
); );
inst_piso_10mbps : entity work.piso piso8_dout_en <= piso4_din_rdy and ifg_idle;
inst_piso4 : entity work.piso
GENERIC MAP GENERIC MAP
( (
data_width_in => 8, data_width_in => 8,
@@ -606,17 +687,17 @@ inst_piso_10mbps : entity work.piso
( (
rst => reset_en, rst => reset_en,
clk => mii_tx_clk, clk => mii_tx_clk,
din_vld => piso_dout_vld, din_vld => piso8_dout_vld,
din_rdy => piso_10mbps_din_rdy, din_rdy => piso4_din_rdy,
din_be => "11", din_be => "11",
din => piso_dout, din => piso8_dout,
dout_vld => tx_en, dout_vld => piso4_dout_vld,
dout_en => '1', dout_en => '1',
dout => mii_tx(3 downto 0) dout => piso4_dout
); );
mii_tx_en <= tx_en; mii_tx_en <= piso4_dout_vld;
mii_tx(7 downto 4) <= "0000"; mii_tx <= "0000" & piso4_dout;
end behavior; end behavior;
lib/emac/src/emac_types.vhd
+5
View File
@@ -12,6 +12,7 @@ use IEEE.MATH_REAL.ALL;
package emac_types is package emac_types is
-- Constants -- Constants
type mac_addr_t is array (0 to 5) of unsigned (7 downto 0);
-- Types -- Types
type tx_ctrl_in_t is record type tx_ctrl_in_t is record
@@ -35,12 +36,16 @@ package emac_types is
pkt_read_en : std_logic; pkt_read_en : std_logic;
pkt_req_en : std_logic; pkt_req_en : std_logic;
pkt_free_en : std_logic; pkt_free_en : std_logic;
mac_addr : mac_addr_t;
promiscious : std_logic;
end record; end record;
type rx_ctrl_out_t is record type rx_ctrl_out_t is record
rx_er : std_logic; rx_er : std_logic;
pkt_avail : std_logic; pkt_avail : std_logic;
pkt_lost : std_logic; pkt_lost : std_logic;
pkt_bcast : std_logic;
pkt_mac_match : std_logic;
rx_size : unsigned(15 downto 0); rx_size : unsigned(15 downto 0);
reset_busy : std_logic; reset_busy : std_logic;
end record; end record;
lib/emac/src/piso.vhd
+3 -1
View File
@@ -88,8 +88,10 @@ begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
shift_cnt_pipe <= (others => '1'); shift_cnt_pipe <= (others => '1');
elsif (din_vld = '1' and din_vld_reg = '0') then
shift_cnt_pipe <= (others => '0');
elsif dout_en = '1' then elsif dout_en = '1' then
if (pre_fin = '1' and din_vld_reg = '1') or (din_vld = '1' and din_vld_reg = '0') then if (pre_fin = '1' and din_vld_reg = '1') then
shift_cnt_pipe <= (others => '0'); shift_cnt_pipe <= (others => '0');
else else
shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1'; shift_cnt_pipe <= shift_cnt_pipe(shift_cnt_pipe'left-1 downto 0) & '1';
lib/emac/src/pkt_gen.vhd
+194 -111
View File
@@ -51,33 +51,37 @@ ARCHITECTURE behavior OF pkt_gen IS
signal xfer_size : word_ptr_t; signal xfer_size : word_ptr_t;
signal xfer_ptr : word_ptr_t; signal xfer_ptr : word_ptr_t;
signal xfer_cnt : word_ptr_t; signal xfer_cnt : word_ptr_t;
signal xfer_ptr_set : std_logic; signal xfer_set : std_logic;
signal xfer_ptr_adv : std_logic; signal xfer_en : std_logic;
signal xfer_cnt_set : std_logic; signal xfer_sync : unsigned(1 downto 0);
signal xfer_cnt_adv : std_logic; signal xfer_cnt_en : std_logic;
signal xfer_rdy : std_logic; signal xfer_bsy : std_logic;
signal xfer_tag : unsigned(3 downto 0); signal xfer_pre_rdy : std_logic;
signal xfer_remain : unsigned(1 downto 0); signal uncommit_en : std_logic;
signal xfer_odd : std_logic;
signal xfer_remain_en : std_logic;
signal commit_en : std_logic;
signal piso_din_be : unsigned(3 downto 0); signal piso8_din : unsigned(31 downto 0);
signal piso_din_rdy : std_logic; signal piso8_din_be : unsigned(3 downto 0);
signal data_vld : std_logic; signal piso8_din_rdy : std_logic;
signal piso8_din_vld : std_logic;
signal piso_dout : unsigned(7 downto 0); signal piso8_dout : unsigned(7 downto 0);
signal piso_dout_vld : std_logic; signal piso8_dout_vld : std_logic;
signal piso_10mbps_din_rdy : std_logic; signal piso8_dout_en : std_logic;
signal piso4_din_rdy : std_logic;
signal tx_en : std_logic; signal tx_en : std_logic;
subtype inter_frame_gap_cnt_t is natural; subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
signal inter_frame_gap_cnt : inter_frame_gap_cnt_t; -- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
signal inter_frame_gap_rdy : std_logic;
signal ifg_cnt : ifg_cnt_t;
signal ifg_idle : std_logic;
type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_wait, xfer_active, xfer_uncommit, xfer_free); type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free);
signal xfer_s, xfer_sn : xfer_state_t; signal xfer_s, xfer_sn : xfer_state_t;
type stream_state_t is (stream_init, stream_idle, stream_start, stream_preamble0, stream_preamble1, stream_active, stream_crc, stream_stop, stream_finish);
signal stream_s, stream_sn : stream_state_t;
type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0); type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
constant piso_byte_mask_rom : piso_byte_mask_array_t := constant piso_byte_mask_rom : piso_byte_mask_array_t :=
( (
@@ -87,17 +91,28 @@ ARCHITECTURE behavior OF pkt_gen IS
"1110" "1110"
); );
signal preamble_en : std_logic;
signal preamble_addr : natural range 0 to 1;
type preamble_t is array (0 to 1) of unsigned(31 downto 0);
constant preamble : preamble_t :=
(
X"55555555",
X"555555D5"
);
begin begin
mii_tx_er <= '0'; mii_tx_er <= '0';
piso_din_be <= mii_fifo_dout(35 downto 32); piso8_din <= preamble(preamble_addr) when preamble_en = '1' else mii_fifo_dout(31 downto 0);
mii_fifo_re <= piso_din_rdy; piso8_din_be <= "1111" when preamble_en = '1' else mii_fifo_dout(35 downto 32);
data_vld <= not mii_fifo_empty;
mii_fifo_we <= xfer_bsy;
mii_fifo_din(35 downto 32) <= piso_byte_mask_rom(to_integer(xfer_remain)) when xfer_remain_en = '1' else "1111"; xfer_cnt_en <= xfer_bsy and not mii_fifo_full;
mii_fifo_din(35 downto 32) <= piso_byte_mask_rom(to_integer(pkt_nbytes(1 downto 0))) when xfer_pre_rdy = '1' else "1111";
mii_fifo_din(31 downto 0) <= pkt_data; mii_fifo_din(31 downto 0) <= pkt_data;
------------------------------------------------------------------ ------------------------------------------------------------------
-- Transfer stuff -- Transfer stuff
@@ -115,16 +130,12 @@ xfer_state_next:
end process; end process;
xfer_state: xfer_state:
process(xfer_s, xfer_odd, xfer_rdy, inter_frame_gap_rdy, mii_fifo_full) process(xfer_s, xfer_bsy, xfer_sync)
begin begin
xfer_cnt_set <= '0'; uncommit_en <= '0';
xfer_cnt_adv <= '0'; xfer_set <= '0';
xfer_ptr_set <= '0'; xfer_en <= '0';
xfer_ptr_adv <= '0';
xfer_remain_en <= '0';
mii_fifo_we <= '0';
commit_en <= '0';
xfer_sn <= xfer_s; xfer_sn <= xfer_s;
@@ -134,40 +145,28 @@ xfer_state:
xfer_sn <= xfer_idle; xfer_sn <= xfer_idle;
when xfer_idle => when xfer_idle =>
xfer_ptr_set <= '1'; xfer_sn <= xfer_setup;
xfer_cnt_set <= '1';
xfer_sn <= xfer_wait;
when xfer_wait =>
if inter_frame_gap_rdy = '1' then
xfer_sn <= xfer_setup;
xfer_cnt_adv <= '1';
end if;
when xfer_setup => when xfer_setup =>
xfer_cnt_adv <= '1'; xfer_set <= '1';
xfer_ptr_adv <= '1'; xfer_sn <= xfer_arm;
when xfer_arm =>
xfer_en <= '1';
xfer_sn <= xfer_active; xfer_sn <= xfer_active;
when xfer_active => when xfer_active =>
mii_fifo_we <= '1'; xfer_en <= '1';
xfer_cnt_adv <= not mii_fifo_full; if xfer_bsy = '0' then
xfer_ptr_adv <= not mii_fifo_full; xfer_sn <= xfer_uncommit;
if xfer_rdy = '1' then
xfer_remain_en <= xfer_odd;
xfer_cnt_adv <= '0';
xfer_ptr_adv <= '0';
if mii_fifo_full = '0' then
xfer_sn <= xfer_uncommit;
end if;
end if; end if;
when xfer_uncommit => when xfer_uncommit =>
commit_en <= '1'; uncommit_en <= '1';
xfer_sn <= xfer_free; xfer_sn <= xfer_free;
when xfer_free => when xfer_free =>
if inter_frame_gap_rdy = '0' then if xfer_sync(1) = '1' then
xfer_sn <= xfer_idle; xfer_sn <= xfer_idle;
end if; end if;
@@ -177,6 +176,33 @@ xfer_state:
end process; end process;
------------------------------------------------------------------
interframe_gap_ready:
process(clk)
begin
if rising_edge(clk) then
xfer_sync(1) <= xfer_sync(0);
xfer_sync(0) <= mii_fifo_empty;
end if;
end process;
------------------------------------------------------------------
interframe_gap_counter:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
ifg_idle <= '0';
if rst = '1' or piso8_dout_vld = '1' then
ifg_cnt <= ifg_cnt_t'high;
ifg_idle <= '1';
elsif ifg_cnt /= 0 then
ifg_cnt <= ifg_cnt - 1;
else
ifg_idle <= '1';
end if;
end if;
end process;
------------------------------------------------------------------ ------------------------------------------------------------------
pkt_params: pkt_params:
process(clk) process(clk)
@@ -195,7 +221,7 @@ pkt_params:
seed2 := 12586901; seed2 := 12586901;
tx_packets <= 0; tx_packets <= 0;
tx_bytes <= 0; tx_bytes <= 0;
elsif commit_en = '1' then elsif uncommit_en = '1' then
uniform(seed1, seed2, krand); uniform(seed1, seed2, krand);
size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length); size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length);
delay := natural(1.0E6*f_sysclk*(PKT_DLY_MIN + (PKT_DLY_MAX-PKT_DLY_MIN)*krand)); delay := natural(1.0E6*f_sysclk*(PKT_DLY_MIN + (PKT_DLY_MAX-PKT_DLY_MIN)*krand));
@@ -212,54 +238,28 @@ pkt_params:
end if; end if;
end process; end process;
------------------------------------------------------------------
interframe_gap_counter:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
if rst = '1' then
inter_frame_gap_rdy <= '1';
elsif tx_en = '1' then
inter_frame_gap_rdy <= '0';
inter_frame_gap_cnt <= pkt_delay;
elsif inter_frame_gap_cnt /= 0 then
inter_frame_gap_cnt <= inter_frame_gap_cnt - 1;
else
inter_frame_gap_rdy <= '1';
end if;
end if;
end process;
------------------------------------------------------------------ ------------------------------------------------------------------
xfer_counter: xfer_counter:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if xfer_cnt_set = '1' then if xfer_set = '1' then
xfer_size <= (others => '0');
xfer_rdy <= '0';
xfer_cnt <= pkt_nwords; xfer_cnt <= pkt_nwords;
elsif xfer_cnt_adv = '1' then xfer_size <= (others => '0');
if xfer_cnt /= 0 then xfer_bsy <= '0';
xfer_cnt <= xfer_cnt - 1; xfer_pre_rdy <= '0';
xfer_size <= xfer_size + 1; elsif xfer_en = '1' then
else xfer_bsy <= '1';
xfer_rdy <= '1'; if xfer_cnt_en = '1' or xfer_bsy = '0' then
end if; if xfer_cnt /= 1 then
end if; xfer_cnt <= xfer_cnt - 1;
end if; xfer_size <= xfer_size + 1;
else
end process; xfer_pre_rdy <= '1';
end if;
xfer_pointer: if xfer_pre_rdy = '1' then
process(clk) xfer_bsy <= '0';
begin end if;
if rising_edge(clk) then
if xfer_ptr_set = '1' then
xfer_remain <= pkt_nbytes(1 downto 0);
xfer_odd <= '0';
if xfer_tag(3 downto 2) /= "00" then
xfer_odd <= '1';
end if; end if;
end if; end if;
end if; end if;
@@ -272,9 +272,9 @@ pkt_data_gen:
variable data : unsigned(7 downto 0); variable data : unsigned(7 downto 0);
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if xfer_set = '1' then
data := (others => '0'); data := (others => '0');
elsif xfer_cnt_adv = '1' then elsif xfer_cnt_en = '1' or xfer_bsy = '0' then
pkt_data(7 downto 0) <= data; pkt_data(7 downto 0) <= data;
data := data + 1; data := data + 1;
pkt_data(15 downto 8) <= data; pkt_data(15 downto 8) <= data;
@@ -288,6 +288,87 @@ pkt_data_gen:
end process; end process;
------------------------------------------------------------------
stream_state_next:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
if rst = '1' then
stream_s <= stream_init;
else
stream_s <= stream_sn;
end if;
end if;
end process;
stream_state:
process(stream_s, ifg_idle, mii_fifo_empty, piso8_din_rdy, piso8_dout_vld)
begin
piso8_din_vld <= '0';
mii_fifo_re <= '0';
preamble_en <= '0';
preamble_addr <= 0;
stream_sn <= stream_s;
case stream_s is
when stream_init =>
if mii_fifo_empty = '1' then
stream_sn <= stream_idle;
end if;
when stream_idle =>
if mii_fifo_empty = '0' and piso8_din_rdy = '1' then
stream_sn <= stream_start;
end if;
when stream_start =>
stream_sn <= stream_preamble0;
when stream_preamble0 =>
preamble_addr <= 0;
preamble_en <= '1';
piso8_din_vld <= '1';
if piso8_din_rdy = '1' then
stream_sn <= stream_preamble1;
end if;
when stream_preamble1 =>
preamble_addr <= 1;
preamble_en <= '1';
piso8_din_vld <= '1';
if piso8_din_rdy = '1' then
stream_sn <= stream_active;
end if;
when stream_active =>
piso8_din_vld <= not mii_fifo_empty;
mii_fifo_re <= piso8_din_rdy;
if mii_fifo_empty = '1' then
stream_sn <= stream_crc;
end if;
when stream_crc =>
stream_sn <= stream_stop;
when stream_stop =>
if piso8_dout_vld = '0' then
stream_sn <= stream_finish;
end if;
when stream_finish =>
if ifg_idle = '0' then
stream_sn <= stream_idle;
end if;
when others =>
stream_sn <= stream_idle;
end case;
end process;
------------------------------------------------------------------ ------------------------------------------------------------------
-- Instantiate synchronous FIFO -- Instantiate synchronous FIFO
inst_mii_fifo: entity work.fifo_async inst_mii_fifo: entity work.fifo_async
@@ -323,16 +404,18 @@ inst_piso : entity work.piso
( (
rst => rst, rst => rst,
clk => mii_tx_clk, clk => mii_tx_clk,
din_vld => data_vld, din_vld => piso8_din_vld,
din_rdy => piso_din_rdy, din_rdy => piso8_din_rdy,
din_be => piso_din_be, din_be => piso8_din_be,
din => mii_fifo_dout(31 downto 0), din => piso8_din,
dout_vld => piso_dout_vld, dout_vld => piso8_dout_vld,
dout_en => piso_10mbps_din_rdy, dout_en => piso8_dout_en,
dout => piso_dout dout => piso8_dout
); );
piso8_dout_en <= piso4_din_rdy and ifg_idle;
inst_piso_10mbps : entity work.piso inst_piso_10mbps : entity work.piso
GENERIC MAP GENERIC MAP
( (
@@ -344,10 +427,10 @@ inst_piso_10mbps : entity work.piso
( (
rst => rst, rst => rst,
clk => mii_tx_clk, clk => mii_tx_clk,
din_vld => piso_dout_vld, din_vld => piso8_dout_vld,
din_rdy => piso_10mbps_din_rdy, din_rdy => piso4_din_rdy,
din_be => "11", din_be => "11",
din => piso_dout, din => piso8_dout,
dout_vld => tx_en, dout_vld => tx_en,
dout_en => '1', dout_en => '1',
dout => mii_tx(3 downto 0) dout => mii_tx(3 downto 0)
lib/emac/src/tb_emac_top_jb.vhd
+48 -48
View File
@@ -415,11 +415,11 @@ STIMULUS: process
emac_alloc (1004); emac_alloc (1004);
for i in 1 to 10 loop for i in 1 to 10 loop
for j in 1 to 500 loop for j in 1 to 100 loop
emac_alloc (72); emac_alloc (72);
emac_write (72); emac_write (72);
end loop; end loop;
wait for 2 ms; wait for 1 ms;
end loop; end loop;
wait until rising_edge(mii_tx_clk) and mii_tx_en = '0'; wait until rising_edge(mii_tx_clk) and mii_tx_en = '0';
@@ -427,11 +427,11 @@ STIMULUS: process
loop_back_en <= '1'; loop_back_en <= '1';
emac_alloc (72); emac_alloc (74);
emac_write (72); emac_write (74);
emac_alloc (104); emac_alloc (105);
emac_write (104); emac_write (105);
emac_read (0); emac_read (0);
emac_free; emac_free;
@@ -439,14 +439,14 @@ STIMULUS: process
emac_read (0); emac_read (0);
emac_free; emac_free;
emac_alloc (104); emac_alloc (103);
emac_write (104); emac_write (103);
emac_read (0); emac_read (0);
emac_free; emac_free;
emac_alloc (72); emac_alloc (71);
emac_write (72); emac_write (71);
emac_read (0); emac_read (0);
emac_free; emac_free;
@@ -454,8 +454,8 @@ STIMULUS: process
emac_alloc (82); emac_alloc (82);
emac_write (82); emac_write (82);
emac_alloc (82); emac_alloc (86);
emac_write (82); emac_write (86);
emac_read (0); emac_read (0);
emac_free; emac_free;
@@ -463,44 +463,44 @@ STIMULUS: process
emac_read (0); emac_read (0);
emac_free; emac_free;
emac_alloc (77);
emac_write (77);
emac_alloc (99);
emac_write (99);
emac_alloc (65);
emac_write (65);
emac_alloc (321);
emac_write (321);
emac_read (0);
emac_free;
emac_alloc (1111);
emac_write (1111);
emac_read (0);
emac_free;
emac_alloc (73);
emac_write (73);
emac_alloc (107);
emac_write (107);
emac_alloc (83);
emac_write (83);
emac_read (0);
emac_free;
emac_alloc (72); emac_alloc (72);
emac_write (72); emac_write (72);
emac_alloc (104); emac_alloc (1003);
emac_write (104); emac_write (1003);
emac_alloc (82);
emac_write (82);
emac_alloc (72);
emac_write (72);
emac_read (0);
emac_free;
emac_alloc (104);
emac_write (104);
emac_read (0);
emac_free;
emac_alloc (72);
emac_write (72);
emac_alloc (104);
emac_write (104);
emac_alloc (82);
emac_write (82);
emac_read (0);
emac_free;
emac_alloc (72);
emac_write (72);
emac_alloc (104);
emac_write (104);
emac_read (0); emac_read (0);
emac_free; emac_free;
@@ -529,7 +529,7 @@ STIMULUS: process
pktgen_rst <= '0'; pktgen_rst <= '0';
pkt_count <= 0; pkt_count <= 0;
for i in 1 to 500 loop for i in 1 to 500 loop
wait for 7 us; wait for 10 us;
emac_read (0); emac_read (0);
emac_free; emac_free;
pkt_count <= pkt_count + 1; pkt_count <= pkt_count + 1;