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- cleaned up NOPs

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1094 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-16 17:16:22 +00:00
parent 4e66c8c1c8
commit f541f84db1
1 changed files with 8 additions and 6 deletions
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lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+8 -6
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@@ -485,6 +485,7 @@ proc_stage_ID_EX_1:
begin begin
if rising_edge(clk_1) then if rising_edge(clk_1) then
if stage_rst(1) = '1' then if stage_rst(1) = '1' then
EX_stage.nop <= '1';
EX_stage.op <= op_nop; EX_stage.op <= op_nop;
EX_stage.IR <= (others => '0'); EX_stage.IR <= (others => '0');
EX_stage.ctrl <= ctrl_lines_default; EX_stage.ctrl <= ctrl_lines_default;
@@ -492,15 +493,16 @@ proc_stage_ID_EX_1:
EX_stage.epc <= (others => '0'); EX_stage.epc <= (others => '0');
EX_stage.pcn <= (others => '0'); EX_stage.pcn <= (others => '0');
EX_stage.events_in <= events_clr; EX_stage.events_in <= events_clr;
EX_stage.nop <= '1'; EX_stage.reg_a <= (others => '0');
EX_stage.reg_b <= (others => '0');
elsif sdu.EX_stall = '0' then elsif sdu.EX_stall = '0' then
EX_stage.nop <= sdu.EX_nop;
EX_stage.reg_a <= ID_stage.reg_a; EX_stage.reg_a <= ID_stage.reg_a;
EX_stage.reg_b <= ID_stage.reg_b; EX_stage.reg_b <= ID_stage.reg_b;
EX_stage.events_in <= ID_stage.events; EX_stage.events_in <= ID_stage.events;
EX_stage.op <= ID_stage.op; EX_stage.op <= ID_stage.op;
EX_stage.ctrl <= ID_stage.ctrl; EX_stage.ctrl <= ID_stage.ctrl;
EX_stage.reg_write <= ID_stage.reg_write; EX_stage.reg_write <= ID_stage.reg_write;
EX_stage.nop <= sdu.EX_nop;
EX_stage.IR <= ID_stage.IR; EX_stage.IR <= ID_stage.IR;
EX_stage.pcn <= ID_stage.pcn; EX_stage.pcn <= ID_stage.pcn;
EX_stage.epc <= ID_stage.epc; EX_stage.epc <= ID_stage.epc;
@@ -751,18 +753,19 @@ proc_stage_MEM_n:
begin begin
if rising_edge(clk_1) then if rising_edge(clk_1) then
if stage_rst(2) = '1' then if stage_rst(2) = '1' then
MEM_stage.nop <= '1';
MEM_stage.op <= op_nop;
MEM_stage.va <= (others => '0'); MEM_stage.va <= (others => '0');
MEM_stage.pcn <= (others => '0'); MEM_stage.pcn <= (others => '0');
MEM_stage.ex_result <= (others => '0'); MEM_stage.ex_result <= (others => '0');
MEM_stage.epc <= (others => '0'); MEM_stage.epc <= (others => '0');
MEM_stage.op <= op_nop;
MEM_stage.wreg_we <= '0'; MEM_stage.wreg_we <= '0';
MEM_stage.reg_wptr <= (others => '0'); MEM_stage.reg_wptr <= (others => '0');
MEM_stage.ctrl <= ctrl_lines_default; MEM_stage.ctrl <= ctrl_lines_default;
MEM_stage.pa_off <= (others => '0'); MEM_stage.pa_off <= (others => '0');
MEM_stage.events_in <= events_clr; MEM_stage.events_in <= events_clr;
MEM_stage.nop <= '1';
elsif sdu.MEM_stall = '0' then elsif sdu.MEM_stall = '0' then
MEM_stage.nop <= sdu.MEM_nop;
MEM_stage.events_in <= EX_stage.events; MEM_stage.events_in <= EX_stage.events;
MEM_stage.op <= EX_stage.op; MEM_stage.op <= EX_stage.op;
MEM_stage.wreg_we <= EX_stage.wreg_we; MEM_stage.wreg_we <= EX_stage.wreg_we;
@@ -772,7 +775,6 @@ proc_stage_MEM_n:
end if; end if;
MEM_stage.pa_off <= EX_stage.pa_off; MEM_stage.pa_off <= EX_stage.pa_off;
MEM_stage.reg_wptr <= EX_stage.reg_wptr; MEM_stage.reg_wptr <= EX_stage.reg_wptr;
MEM_stage.nop <= sdu.MEM_nop;
if MEM_stage.reg_wptr = EX_stage.reg_wptr then if MEM_stage.reg_wptr = EX_stage.reg_wptr then
if (EX_stage.ctrl.dmem_en and MEM_stage.ctrl.dmem_en) = '1' then if (EX_stage.ctrl.dmem_en and MEM_stage.ctrl.dmem_en) = '1' then
MEM_stage.ex_result <= MEM_stage.data; MEM_stage.ex_result <= MEM_stage.data;
@@ -855,13 +857,13 @@ proc_stage_WB_p:
WB_stage.data <= (others => '0'); WB_stage.data <= (others => '0');
WB_stage.events <= events_clr; WB_stage.events <= events_clr;
WB_stage.bd <= '0'; WB_stage.bd <= '0';
WB_stage.exc <= '0';
elsif sdu.WB_stall = '0' then elsif sdu.WB_stall = '0' then
WB_stage.nop <= sdu.WB_nop; WB_stage.nop <= sdu.WB_nop;
WB_stage.op <= MEM_stage.op; WB_stage.op <= MEM_stage.op;
WB_stage.wreg_we <= MEM_stage.wreg_we; WB_stage.wreg_we <= MEM_stage.wreg_we;
WB_stage.reg_wptr <= MEM_stage.reg_wptr; WB_stage.reg_wptr <= MEM_stage.reg_wptr;
WB_stage.data <= MEM_stage.data; WB_stage.data <= MEM_stage.data;
WB_stage.exc <= '0';
WB_stage.exc <= MEM_stage.exc; WB_stage.exc <= MEM_stage.exc;
if MEM_stage.exc = '1' then if MEM_stage.exc = '1' then
WB_stage.events <= MEM_stage.events; WB_stage.events <= MEM_stage.events;