diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
index 7ec5b80..8f15ecb 100644
--- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
@@ -485,6 +485,7 @@ proc_stage_ID_EX_1:
 	begin
 		if rising_edge(clk_1) then
 			if stage_rst(1) = '1' then
+				EX_stage.nop					<= '1';
 				EX_stage.op						<= op_nop;
 				EX_stage.IR						<= (others => '0');
 				EX_stage.ctrl					<= ctrl_lines_default;
@@ -492,15 +493,16 @@ proc_stage_ID_EX_1:
 				EX_stage.epc					<= (others => '0');
 				EX_stage.pcn					<= (others => '0');
 				EX_stage.events_in				<= events_clr;
-				EX_stage.nop					<= '1';
+				EX_stage.reg_a			<= (others => '0');
+				EX_stage.reg_b			<= (others => '0');
 			elsif sdu.EX_stall = '0' then
+				EX_stage.nop					<= sdu.EX_nop;
 				EX_stage.reg_a			<= ID_stage.reg_a;
 				EX_stage.reg_b			<= ID_stage.reg_b;
 				EX_stage.events_in		<= ID_stage.events;
 				EX_stage.op				<= ID_stage.op;
 				EX_stage.ctrl			<= ID_stage.ctrl;
 				EX_stage.reg_write		<= ID_stage.reg_write;
-				EX_stage.nop			<= sdu.EX_nop;
 				EX_stage.IR				<= ID_stage.IR;
 				EX_stage.pcn			<= ID_stage.pcn;
 				EX_stage.epc			<= ID_stage.epc;
@@ -751,18 +753,19 @@ proc_stage_MEM_n:
 	begin
 		if rising_edge(clk_1) then
 			if stage_rst(2) = '1' then
+				MEM_stage.nop			<= '1';
+				MEM_stage.op			<= op_nop;
 				MEM_stage.va			<= (others => '0');
 				MEM_stage.pcn			<= (others => '0');
 				MEM_stage.ex_result	<= (others => '0');
 				MEM_stage.epc			<= (others => '0');
-				MEM_stage.op			<= op_nop;
 				MEM_stage.wreg_we		<= '0';
 				MEM_stage.reg_wptr	<= (others => '0');
 				MEM_stage.ctrl			<= ctrl_lines_default;
 				MEM_stage.pa_off		<= (others => '0');
 				MEM_stage.events_in	<= events_clr;
-				MEM_stage.nop			<= '1';
 			elsif sdu.MEM_stall = '0' then
+				MEM_stage.nop			<= sdu.MEM_nop;
 				MEM_stage.events_in		<= EX_stage.events;
 				MEM_stage.op			<= EX_stage.op;
 				MEM_stage.wreg_we		<= EX_stage.wreg_we;
@@ -772,7 +775,6 @@ proc_stage_MEM_n:
 				end if;	
 				MEM_stage.pa_off		<= EX_stage.pa_off;
 				MEM_stage.reg_wptr		<= EX_stage.reg_wptr;
-				MEM_stage.nop			<= sdu.MEM_nop;
 				if MEM_stage.reg_wptr = EX_stage.reg_wptr then
 					if (EX_stage.ctrl.dmem_en and MEM_stage.ctrl.dmem_en) = '1' then
 						MEM_stage.ex_result	<= MEM_stage.data;
@@ -855,13 +857,13 @@ proc_stage_WB_p:
 				WB_stage.data			<= (others => '0');
 				WB_stage.events		<= events_clr;
 				WB_stage.bd				<= '0';
+				WB_stage.exc			<= '0';
 			elsif sdu.WB_stall = '0' then
 				WB_stage.nop			<= sdu.WB_nop;
 				WB_stage.op				<= MEM_stage.op;
 				WB_stage.wreg_we		<= MEM_stage.wreg_we;
 				WB_stage.reg_wptr		<= MEM_stage.reg_wptr;
 				WB_stage.data			<= MEM_stage.data;
-				WB_stage.exc			<= '0';
 				WB_stage.exc			<= MEM_stage.exc;
 				if MEM_stage.exc = '1' then
 					WB_stage.events			<= MEM_stage.events;