diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
index c8a0fc0..534232b 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config.vhd
@@ -54,18 +54,18 @@ package sdram_config is
 
 	-- DDR-SDR TIMING constants ------------------------------------------------------------------
 	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
-	constant REFRESH_INTERVAL	: real := 7.8125E-6; -- [s]
+	constant REFRESH_INTERVAL	: real := 7.8125E3; -- [ns]
 
 	-- These values are for your SDRAM part (see datasheet) 
 	constant TCAS : positive	:= 2;			-- CAS latency [clocks]
-	constant TRP  : real		:= 20.0E-9;		-- precharge command period [s]
-	constant TRAS : real		:= 45.0E-9;		-- active to precharge delay [s]
-	constant TRFC : real		:= 75.0E-9;		-- auto refresh command period [s]
+	constant TRP  : real		:= 20.0;		-- precharge command period [ns]
+	constant TRAS : real		:= 45.0;		-- active to precharge delay [ns]
+	constant TRFC : real		:= 75.0;		-- auto refresh command period [ns]
 	constant TMRD : positive	:= 2;			-- load mode register command cylce time [clocks]
-	constant TRCD : real		:= 20.0E-9;		-- active to read or write delay [s]
-	constant TWR  : real		:= 15.0E-9;		-- write recovery time [s]
+	constant TRCD : real		:= 20.0;		-- active to read or write delay [ns]
+	constant TWR  : real		:= 15.0;		-- write recovery time [ns]
 
-	constant PWR_UP_WAIT		: real := 1.0E-6; -- [s]
+	constant PWR_UP_WAIT		: real := 1.0E3; -- [ns]
 	
 	subtype user_tag_t is unsigned(3 downto 0);
 	
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
index fcb28a4..0c7102a 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
@@ -113,16 +113,16 @@ package sdram_types is
 		wait_cycle	: natural;
 	end record init_seq_t;	
 	
-	function to_cycles(T_s : real; f_hz : natural) return natural;
+	function to_cycles(T_ns : real; f_hz : natural) return natural;
 	
 end sdram_types;
 
 package body sdram_types is
 
-	function to_cycles(T_s : real; f_hz : natural) return natural is
+	function to_cycles(T_ns : real; f_hz : natural) return natural is
 	begin
 		
-		return natural(0.5 + T_s*real(f_hz));
+		return natural(0.5 + 1.0E-9*T_ns*real(f_hz));
 
 	end to_cycles;	
 
diff --git a/projects/mips_sys/src/sdram_config.vhd b/projects/mips_sys/src/sdram_config.vhd
index d679457..c964e6b 100644
--- a/projects/mips_sys/src/sdram_config.vhd
+++ b/projects/mips_sys/src/sdram_config.vhd
@@ -54,18 +54,18 @@ package sdram_config is
 	
 	-- DDR-SDR TIMING constants ------------------------------------------------------------------
 	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
-	constant REFRESH_INTERVAL	: real := 7.8125E-6; -- [s]
+	constant REFRESH_INTERVAL	: real := 7.8125E3; -- [ns]
 
 	-- These values are for your SDRAM part (see datasheet) 
-	constant TCAS : positive  := 2;   -- CAS latency [clocks]
-	constant TRP  : real		:= 20.0E-9;		-- precharge command period [s]
-	constant TRAS : real		:= 45.0E-9;		-- active to precharge delay [s]
-	constant TRFC : real		:= 75.0E-9;		-- auto refresh command period [s]
+	constant TCAS : positive	:= 2;		   -- CAS latency [clocks]
+	constant TRP  : real		:= 20.0;		-- precharge command period [ns]
+	constant TRAS : real		:= 45.0;		-- active to precharge delay [ns]
+	constant TRFC : real		:= 75.0;		-- auto refresh command period [ns]
 	constant TMRD : positive	:= 2;			-- load mode register command cylce time [clocks]
-	constant TRCD : real		:= 20.0E-9;		-- active to read or write delay [s]
-	constant TWR  : real		:= 15.0E-9;		-- write recovery time [s]
+	constant TRCD : real		:= 20.0;		-- active to read or write delay [ns]
+	constant TWR  : real		:= 15.0;		-- write recovery time [ns]
 
-	constant PWR_UP_WAIT		: real := 220.0E-6; -- [s]
+	constant PWR_UP_WAIT		: real := 220.0E3; -- [ns]
 
 	subtype user_tag_t is unsigned(3 downto 0);
 
diff --git a/projects/mips_sys/src/sdram_config_sim.vhd b/projects/mips_sys/src/sdram_config_sim.vhd
index ccbfbbb..5067520 100644
--- a/projects/mips_sys/src/sdram_config_sim.vhd
+++ b/projects/mips_sys/src/sdram_config_sim.vhd
@@ -54,18 +54,18 @@ package sdram_config is
 	
 	-- DDR-SDR TIMING constants ------------------------------------------------------------------
 	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh 
-	constant REFRESH_INTERVAL	: real := 7.8125E-6; -- [s]
+	constant REFRESH_INTERVAL	: real := 7.8125E3; -- [ns]
 
 	-- These values are for your SDRAM part (see datasheet) 
-	constant TCAS : positive  := 2;   -- CAS latency [clocks]
-	constant TRP  : real		:= 20.0E-9;		-- precharge command period [s]
-	constant TRAS : real		:= 45.0E-9;		-- active to precharge delay [s]
-	constant TRFC : real		:= 75.0E-9;		-- auto refresh command period [s]
+	constant TCAS : positive	:= 2;   		-- CAS latency [clocks]
+	constant TRP  : real		:= 20.0;		-- precharge command period [ns]
+	constant TRAS : real		:= 45.0;		-- active to precharge delay [ns]
+	constant TRFC : real		:= 75.0;		-- auto refresh command period [ns]
 	constant TMRD : positive	:= 2;			-- load mode register command cylce time [clocks]
-	constant TRCD : real		:= 20.0E-9;		-- active to read or write delay [s]
-	constant TWR  : real		:= 15.0E-9;		-- write recovery time [s]
+	constant TRCD : real		:= 20.0;		-- active to read or write delay [ns]
+	constant TWR  : real		:= 15.0;		-- write recovery time [ns]
 
-	constant PWR_UP_WAIT		: real := 22.0E-6; -- [s]
+	constant PWR_UP_WAIT		: real := 22.0E3; -- [ns]
 
 	subtype user_tag_t is unsigned(3 downto 0);