- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1427 cc03376c-175c-47c8-b038-4cd826a8556b

projects/ml402_test_01/main.vhd

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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    21:31:55 09/24/05
+-- Design Name:    
+-- Module Name:    main - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity main is
+    Port ( sys_clk_in : in std_logic;
+           sys_rst_in : in std_logic;
+           led : out std_logic_vector(0 to 4);
+           btn : in std_logic_vector(0 to 4));
+end main;
+
+architecture Behavioral of main is
+
+COMPONENT test_comp
+PORT(
+	rst : IN std_logic;
+	clk : IN std_logic;
+	btn : IN std_logic_vector(0 to 4);
+	led : OUT std_logic_vector(0 to 4)
+	);
+END COMPONENT;
+
+begin
+
+inst_test_comp: test_comp
+PORT MAP(
+	rst => sys_rst_in,
+	clk => sys_clk_in,
+	led => led,
+	btn => btn
+);
+
+end Behavioral;