diff --git a/projects/ml402_test_01/_impact.cmd b/projects/ml402_test_01/_impact.cmd new file mode 100644 index 0000000..28c9886 --- /dev/null +++ b/projects/ml402_test_01/_impact.cmd @@ -0,0 +1,36 @@ +setPreference -pref UserLevel:NOVICE +setPreference -pref MessageLevel:DETAILED +setPreference -pref ConcurrentMode:FALSE +setPreference -pref UseHighz:FALSE +setPreference -pref ConfigOnFailure:STOP +setPreference -pref StartupCLock:AUTO_CORRECTION +setPreference -pref AutoSignature:FALSE +setPreference -pref KeepSVF:FALSE +setPreference -pref svfUseTime:FALSE +setPreference -pref UserLevel:NOVICE +setPreference -pref MessageLevel:DETAILED +setPreference -pref ConcurrentMode:FALSE +setPreference -pref UseHighz:FALSE +setPreference -pref ConfigOnFailure:STOP +setPreference -pref StartupCLock:AUTO_CORRECTION +setPreference -pref AutoSignature:FALSE +setPreference -pref KeepSVF:FALSE +setPreference -pref svfUseTime:FALSE +setMode -bs +setMode -cf +setMode -cf +setAttribute -configdevice -attr path -value "e:\work\xilinxise\projects\ml402_test_01" +setMode -cf +setAttribute -configdevice -attr size -value "268435456" +setAttribute -configdevice -attr reseveSize -value "0" +setAttribute -configdevice -attr name -value "XCCACE256-I" +addCollection -name "test_01" +addDesign -version 0 -name "rev0" +addDeviceChain -index 0 +setCurrentDesign -version 0 +addDevice -position 1 -file "E:\work\XilinxISE\Projects\ml402_test_01\main.bit" +setAttribute -configdevice -attr path -value "e:\work\xilinxise\projects\ml402_test_01" +setMode -cf +generate -active test_01 +setMode -pff +setMode -bsfile diff --git a/projects/ml402_test_01/bitgen.ut b/projects/ml402_test_01/bitgen.ut new file mode 100644 index 0000000..b5b2502 --- /dev/null +++ b/projects/ml402_test_01/bitgen.ut @@ -0,0 +1,34 @@ + +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g InitPin:Pullup +-g CsPin:Pullup +-g DinPin:Pullup +-g BusyPin:Pullup +-g RdWrPin:Pullup +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullNone +-g UserID:0xFFFFFFFF +-g DCMShutDown:Disable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g Encrypt:No diff --git a/projects/ml402_test_01/main.lso b/projects/ml402_test_01/main.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/ml402_test_01/main.lso @@ -0,0 +1 @@ +work diff --git a/projects/ml402_test_01/main.prj b/projects/ml402_test_01/main.prj new file mode 100644 index 0000000..fb568b8 --- /dev/null +++ b/projects/ml402_test_01/main.prj @@ -0,0 +1,2 @@ +vhdl work "test_comp.vhd" +vhdl work "main.vhd" diff --git a/projects/ml402_test_01/main.ut b/projects/ml402_test_01/main.ut new file mode 100644 index 0000000..b5b2502 --- /dev/null +++ b/projects/ml402_test_01/main.ut @@ -0,0 +1,34 @@ + +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g InitPin:Pullup +-g CsPin:Pullup +-g DinPin:Pullup +-g BusyPin:Pullup +-g RdWrPin:Pullup +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullNone +-g UserID:0xFFFFFFFF +-g DCMShutDown:Disable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g Encrypt:No diff --git a/projects/ml402_test_01/main.vhd b/projects/ml402_test_01/main.vhd new file mode 100644 index 0000000..352cea5 --- /dev/null +++ b/projects/ml402_test_01/main.vhd @@ -0,0 +1,58 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:31:55 09/24/05 +-- Design Name: +-- Module Name: main - Behavioral +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity main is + Port ( sys_clk_in : in std_logic; + sys_rst_in : in std_logic; + led : out std_logic_vector(0 to 4); + btn : in std_logic_vector(0 to 4)); +end main; + +architecture Behavioral of main is + +COMPONENT test_comp +PORT( + rst : IN std_logic; + clk : IN std_logic; + btn : IN std_logic_vector(0 to 4); + led : OUT std_logic_vector(0 to 4) + ); +END COMPONENT; + +begin + +inst_test_comp: test_comp +PORT MAP( + rst => sys_rst_in, + clk => sys_clk_in, + led => led, + btn => btn +); + +end Behavioral; diff --git a/projects/ml402_test_01/system.ucf b/projects/ml402_test_01/system.ucf new file mode 100644 index 0000000..34fe34c --- /dev/null +++ b/projects/ml402_test_01/system.ucf @@ -0,0 +1,52 @@ +# +# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR +# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION +# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION +# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS +# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE. +# +# (c) Copyright 2005 Xilinx, Inc. +# All rights reserved. +# + +# Bus clock nets +NET sys_clk_in TNM_NET = "sys_clk_in"; +TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %; + +NET sys_clk_in LOC = AE14; +NET sys_clk_in IOSTANDARD = LVCMOS33; +NET sys_rst_in LOC = D6; +NET sys_rst_in PULLUP; +NET sys_rst_in TIG; + +//////////////////////////////////////////////////////////////////////////// +// Buttons, LEDs, and DIP Switches +//////////////////////////////////////////////////////////////////////////// + +# North-East-South-West-Center LEDs +NET led<0> LOC = C6; # C LED +NET led<1> LOC = F9; # W LED +NET led<2> LOC = A5; # S LED +NET led<3> LOC = E10; # E LED +NET led<4> LOC = E2; # N LED +# North-East-South-West-Center Buttons +NET btn<0> LOC = B6; # C Button +NET btn<1> LOC = E9; # W Button +NET btn<2> LOC = A6; # S Button +NET btn<3> LOC = F10; # E Button +NET btn<4> LOC = E7; # N Button + +NET "led<*>" TIG; +NET "led<*>" SLEW = SLOW; +NET "led<*>" DRIVE = 2; + +NET "btn<*>" TIG; +NET "btn<*>" SLEW = SLOW; diff --git a/projects/ml402_test_01/test_comp.lso b/projects/ml402_test_01/test_comp.lso new file mode 100644 index 0000000..22de730 --- /dev/null +++ b/projects/ml402_test_01/test_comp.lso @@ -0,0 +1 @@ +work diff --git a/projects/ml402_test_01/test_comp.prj b/projects/ml402_test_01/test_comp.prj new file mode 100644 index 0000000..878af9c --- /dev/null +++ b/projects/ml402_test_01/test_comp.prj @@ -0,0 +1 @@ +vhdl work "test_comp.vhd" diff --git a/projects/ml402_test_01/test_comp.ut b/projects/ml402_test_01/test_comp.ut new file mode 100644 index 0000000..a36c295 --- /dev/null +++ b/projects/ml402_test_01/test_comp.ut @@ -0,0 +1,34 @@ + +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g InitPin:Pullup +-g CsPin:Pullup +-g DinPin:Pullup +-g BusyPin:Pullup +-g RdWrPin:Pullup +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullUp +-g UserID:0xFFFFFFFF +-g DCMShutDown:Disable +-g DCIUpdateMode:AsRequired +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No +-g Encrypt:No diff --git a/projects/ml402_test_01/test_comp.vhd b/projects/ml402_test_01/test_comp.vhd new file mode 100644 index 0000000..d7462c5 --- /dev/null +++ b/projects/ml402_test_01/test_comp.vhd @@ -0,0 +1,69 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:44:36 09/24/05 +-- Design Name: +-- Module Name: test_comp - Behavioral +-- Project Name: +-- Target Device: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +---- Uncomment the following library declaration if instantiating +---- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity test_comp is + Port ( clk : in std_logic; + rst : in std_logic; + led : out std_logic_vector(0 to 4); + btn : in std_logic_vector(0 to 4)); +end test_comp; + +architecture Behavioral of test_comp is + +begin + +-- Reset logic +reset_action: process(rst, clk, btn) +begin + if clk'event and clk = '1' then + if (rst = '0') then + led(0 to 4) <= (0 to 4 => '0'); + else + if btn(0) = '1' then + led(0) <= '1'; + end if; + if btn(1) = '1' then + led(1) <= '1'; + end if; + if btn(2) = '1' then + led(2) <= '1'; + end if; + if btn(3) = '1' then + led(3) <= '1'; + end if; + if btn(4) = '1' then + led(4) <= '1'; + end if; +-- led <= btn; + end if; + end if; +end process; + + +end Behavioral;