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git-svn-id: http://moon:8086/svn/vhdl/trunk@1426 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-21 11:45:58 +00:00
parent d0c4a3d800
commit 010c1d2b65
19 changed files with 821 additions and 0 deletions
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projects/piso_sipo/sim/tb_piso.fdo
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## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sun Apr 08 17:18:15 Westeuropäische Sommerzeit 2007
##
vlib work
vcom -explicit -93 "../src/piso.vhd"
vcom -explicit -93 "../src/tb_piso.vhd"
vsim -t 1ps -lib work tb_piso_vhd
do tb_piso.wdo
view wave
view structure
view signals
run 5us
projects/piso_sipo/sim/tb_piso.wdo
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_piso_vhd/rst
add wave -noupdate -format Logic /tb_piso_vhd/prdyo
add wave -noupdate -format Logic /tb_piso_vhd/pvi
add wave -noupdate -format Literal -radix hexadecimal /tb_piso_vhd/pdi
add wave -noupdate -format Logic /tb_piso_vhd/sso
add wave -noupdate -format Logic /tb_piso_vhd/sdo
add wave -noupdate -format Literal /tb_piso_vhd/data
add wave -noupdate -format Logic /tb_piso_vhd/uut/srdyi
add wave -noupdate -format Logic /tb_piso_vhd/rst
add wave -noupdate -format Logic /tb_piso_vhd/prdyo
add wave -noupdate -format Logic /tb_piso_vhd/pvi
add wave -noupdate -format Literal -radix hexadecimal /tb_piso_vhd/pdi
add wave -noupdate -format Logic /tb_piso_vhd/sso
add wave -noupdate -format Logic /tb_piso_vhd/sdo
add wave -noupdate -format Literal /tb_piso_vhd/data
add wave -noupdate -format Logic /tb_piso_vhd/uut/srdyi
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {330000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {5250 ns}
projects/piso_sipo/sim/tb_sipo.fdo
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## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sun Apr 08 17:18:15 Westeuropäische Sommerzeit 2007
##
vlib work
vcom -explicit -93 "../src/piso.vhd"
vcom -explicit -93 "../src/sipo.vhd"
vcom -explicit -93 "../src/tb_sipo.vhd"
vsim -t 1ps -lib work tb_sipo_vhd
do tb_sipo.wdo
view wave
view structure
view signals
run 20us
projects/piso_sipo/sim/tb_sipo.wdo
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_sipo_vhd/rst
add wave -noupdate -format Literal /tb_sipo_vhd/width
add wave -noupdate -divider {Parallel IN}
add wave -noupdate -format Literal /tb_sipo_vhd/inst_piso/sstate
add wave -noupdate -format Logic /tb_sipo_vhd/clk
add wave -noupdate -format Literal -radix hexadecimal /tb_sipo_vhd/pdi
add wave -noupdate -format Logic /tb_sipo_vhd/pvi
add wave -noupdate -format Logic /tb_sipo_vhd/prdyo
add wave -noupdate -divider {Serial OUT}
add wave -noupdate -format Logic /tb_sipo_vhd/clk
add wave -noupdate -format Logic /tb_sipo_vhd/sdo
add wave -noupdate -format Logic /tb_sipo_vhd/sso
add wave -noupdate -format Logic /tb_sipo_vhd/inst_piso/srdyi
add wave -noupdate -divider {Serial IN}
add wave -noupdate -format Literal /tb_sipo_vhd/uut/sstate
add wave -noupdate -format Logic /tb_sipo_vhd/clk
add wave -noupdate -format Logic /tb_sipo_vhd/sdi
add wave -noupdate -format Logic /tb_sipo_vhd/ssi
add wave -noupdate -format Logic /tb_sipo_vhd/uut/srdyo
add wave -noupdate -divider {Parallel OUT}
add wave -noupdate -format Logic /tb_sipo_vhd/clk
add wave -noupdate -format Logic /tb_sipo_vhd/pvo
add wave -noupdate -format Literal -radix hexadecimal /tb_sipo_vhd/pdo
add wave -noupdate -format Logic /tb_sipo_vhd/uut/prdyi
add wave -noupdate -divider Debug
add wave -noupdate -format Literal -radix hexadecimal /tb_sipo_vhd/data_out
add wave -noupdate -format Literal -radix hexadecimal /tb_sipo_vhd/data
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {111661 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 79
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {328126 ps}
projects/piso_sipo/src/piso.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:26:08 04/08/2007
-- Design Name:
-- Module Name: piso - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity piso is
Generic ( width : integer := 8 );
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
pdi : in UNSIGNED (width-1 downto 0);
pvi : in STD_LOGIC;
prdyo : out STD_LOGIC;
sdo : out STD_LOGIC;
sso : out STD_LOGIC;
srdyi : in STD_LOGIC
);
end piso;
architecture Behavioral of piso is
type sstate_t is (reset, idle, ready, sync, active);
constant idle_pol : std_logic := '0';
signal reg : UNSIGNED (width-1 downto 0);
signal shift_en, counter_srst, counter_rdy : std_logic;
signal sstate, sstate_next : sstate_t;
begin
par_in:
process (rst, clk, pvi, reg, shift_en)
begin
if rst = '1' then
reg <= (others => idle_pol);
elsif rising_edge(clk) then
if pvi = '1' then
reg <= pdi;
elsif shift_en = '1' then
reg <= reg(width-2 downto 0) & idle_pol;
end if;
end if;
sdo <= reg(width-1);
end process;
counter:
process (rst, counter_srst, clk)
variable counter : integer range 0 to width-1;
begin
if rst = '1' then
counter_rdy <= '0';
elsif rising_edge(clk) then
if counter_srst = '1' then
counter := width-4;
counter_rdy <= '0';
elsif counter /= 0 then
counter := counter - 1;
else
counter_rdy <= '1';
end if;
end if;
end process;
ser_sm:
process (rst, clk, pvi, sstate, counter_rdy, srdyi)
begin
sstate_next <= sstate;
prdyo <= '0';
sso <= '0';
shift_en <= '0';
counter_srst <= '1';
case sstate is
when reset =>
sstate_next <= idle;
when idle =>
sstate_next <= ready;
when ready =>
prdyo <= srdyi;
if pvi = '1' then
sstate_next <= sync;
end if;
when sync =>
sso <= '1';
sstate_next <= active;
shift_en <= '1';
when active =>
shift_en <= '1';
counter_srst <= '0';
if counter_rdy = '1' then
sstate_next <= idle;
end if;
when others =>
sstate_next <= idle;
end case;
end process;
state_proc:
process (rst, clk, sstate_next)
begin
if rst = '1' then
sstate <= reset;
elsif rising_edge(clk) then
sstate <= sstate_next;
end if;
end process;
end Behavioral;
projects/piso_sipo/src/sipo.vhd
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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:55:49 04/08/2007
-- Design Name:
-- Module Name: sipo - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sipo is
Generic ( width : integer := 8 );
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
srdyo : out STD_LOGIC;
sdi : in STD_LOGIC;
ssi : in STD_LOGIC;
prdyi : in STD_LOGIC;
pvo : out STD_LOGIC;
pdo : out UNSIGNED (width-1 downto 0)
);
end sipo;
architecture Behavioral of sipo is
type sstate_t is (reset, idle, ready, sync, active);
constant idle_pol : std_logic := '0';
signal reg : UNSIGNED (width-1 downto 0);
signal pvalid, shift_en, counter_srst, counter_rdy : std_logic;
signal sstate, sstate_next : sstate_t;
begin
par_out:
process (rst, clk, sdi, reg, shift_en, pvalid)
begin
if rst = '1' then
reg <= (others => idle_pol);
pvo <= '0';
elsif rising_edge(clk) then
if shift_en = '1' then
reg <= reg(width-2 downto 0) & sdi;
end if;
pvo <= pvalid;
end if;
pdo <= reg;
end process;
counter:
process (rst, clk, counter_srst)
variable counter : integer range 0 to width-1;
begin
if rst = '1' then
counter_rdy <= '0';
elsif rising_edge(clk) then
if counter_srst = '1' then
counter := width-4;
counter_rdy <= '0';
elsif counter /= 0 then
counter := counter - 1;
else
counter_rdy <= '1';
end if;
end if;
end process;
ser_sm:
process (rst, clk, ssi, sstate, counter_rdy, prdyi)
begin
sstate_next <= sstate;
shift_en <= '1';
pvalid <= '0';
counter_srst <= ssi;
srdyo <= '0';
case sstate is
when reset =>
sstate_next <= idle;
when idle =>
sstate_next <= ready;
when ready =>
srdyo <= prdyi;
if ssi = '1' then
sstate_next <= active;
end if;
when active =>
if counter_rdy = '1' then
sstate_next <= sync;
end if;
when sync =>
pvalid <= '1';
sstate_next <= idle;
when others =>
sstate_next <= idle;
end case;
end process;
state_proc:
process (rst, clk, sstate_next)
begin
if rst = '1' then
sstate <= reset;
elsif rising_edge(clk) then
sstate <= sstate_next;
end if;
end process;
end Behavioral;
projects/piso_sipo/src/tb_piso.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:08:52 04/08/2007
-- Design Name: piso
-- Module Name: tb_piso.vhd
-- Project Name: piso_sipo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: piso
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY tb_piso_vhd IS
GENERIC ( width : integer := 8);
END tb_piso_vhd;
ARCHITECTURE behavior OF tb_piso_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT piso
GENERIC ( width : integer );
PORT(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
pdi : in UNSIGNED (width-1 downto 0);
pvi : in STD_LOGIC;
prdyo : out STD_LOGIC;
sdo : out STD_LOGIC;
sso : out STD_LOGIC;
srdyi : in STD_LOGIC
);
END COMPONENT;
CONSTANT CLK_PERIOD : time := 10 ns;
--Inputs
SIGNAL rst : std_logic := '1';
SIGNAL clk : std_logic := '1';
SIGNAL pvi : std_logic := '0';
SIGNAL srdyi : std_logic := '0';
SIGNAL pdi : UNSIGNED(width-1 downto 0) := (others=>'0');
--Outputs
SIGNAL prdyo : std_logic;
SIGNAL sdo : std_logic;
SIGNAL sso : std_logic;
SIGNAL data : integer := 0;
BEGIN
clk_gen:
PROCESS
BEGIN
wait for CLK_PERIOD/2;
clk <= not clk;
END PROCESS;
-- Instantiate the Unit Under Test (UUT)
uut: piso
GENERIC MAP( width => width )
PORT MAP(
rst => rst,
clk => clk,
pdi => pdi,
pvi => pvi,
prdyo => prdyo,
sdo => sdo,
sso => sso,
srdyi => srdyi
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
rst <= '0';
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
tb_srdy : process (rst, clk, sso)
variable count : integer := 0;
begin
if rst = '1' then
srdyi <= '0';
count := 20;
elsif rising_edge(clk) then
if srdyi = '1' then
if sso = '1' then
srdyi <= '0';
end if;
else
if count /= 0 then
count := count - 1;
else
srdyi <= '1';
count := 20;
end if;
end if;
end if;
end process;
tb_sig : process (rst, clk, prdyo)
begin
if rst = '1' then
data <= 0;
elsif rising_edge(clk) then
if prdyo = '1' then
data <= data + 1;
end if;
end if;
pdi <= to_unsigned(data, pdi'length);
pvi <= prdyo;
end process;
projects/piso_sipo/src/tb_sipo.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:08:52 04/08/2007
-- Design Name: piso
-- Module Name: tb_piso.vhd
-- Project Name: piso_sipo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: piso
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
ENTITY tb_sipo_vhd IS
GENERIC ( width : integer := 8);
END tb_sipo_vhd;
ARCHITECTURE behavior OF tb_sipo_vhd IS
-- Component Declaration for PISO
COMPONENT piso
GENERIC ( width : integer );
PORT(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
pdi : in UNSIGNED (width-1 downto 0);
pvi : in STD_LOGIC;
prdyo : out STD_LOGIC;
sdo : out STD_LOGIC;
sso : out STD_LOGIC;
srdyi : in STD_LOGIC
);
END COMPONENT;
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sipo
GENERIC ( width : integer );
PORT(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
srdyo : out STD_LOGIC;
sdi : in STD_LOGIC;
ssi : in STD_LOGIC;
prdyi : in STD_LOGIC;
pvo : out STD_LOGIC;
pdo : out UNSIGNED (width-1 downto 0)
);
END COMPONENT;
CONSTANT CLK_PERIOD : time := 10 ns;
--Inputs
SIGNAL rst : std_logic := '1';
SIGNAL clk : std_logic := '1';
SIGNAL sdi : std_logic := '0';
SIGNAL ssi : std_logic := '0';
SIGNAL pvi : std_logic := '0';
SIGNAL srdyi : std_logic := '1';
SIGNAL prdyi : std_logic := '1';
SIGNAL pdi : UNSIGNED(width-1 downto 0) := (others=>'0');
--Outputs
SIGNAL srdyo : std_logic;
SIGNAL prdyo : std_logic;
SIGNAL sdo : std_logic;
SIGNAL sso : std_logic;
SIGNAL pvo : std_logic;
SIGNAL pdo : UNSIGNED(width-1 downto 0);
SIGNAL data : integer := 0;
SIGNAL data_out : UNSIGNED(width-1 downto 0);
BEGIN
clk_gen:
PROCESS
BEGIN
wait for CLK_PERIOD/2;
clk <= not clk;
END PROCESS;
-- Instantiate the Unit Under Test (UUT)
inst_piso: piso
GENERIC MAP( width => width )
PORT MAP(
rst => rst,
clk => clk,
pdi => pdi,
pvi => pvi,
prdyo => prdyo,
sdo => sdo,
sso => sso,
srdyi => srdyi
);
uut: sipo
GENERIC MAP( width => width )
PORT MAP(
rst => rst,
clk => clk,
srdyo => srdyo,
sdi => sdi,
ssi => ssi,
pvo => pvo,
pdo => pdo,
prdyi => prdyi
);
tb_prdy : process (rst, clk, pvo)
variable count : integer := 0;
begin
if rst = '1' then
prdyi <= '0';
count := 10;
elsif rising_edge(clk) then
if pvo = '1' then
prdyi <= pdi(0);
end if;
if count /= 0 then
count := count - 1;
else
count := 53;
prdyi <= '1';
end if;
end if;
end process;
sdi <= sdo;
ssi <= sso;
srdyi <= srdyo;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
rst <= '0';
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
tb_sig : process (rst, clk, prdyo)
begin
if rst = '1' then
data <= 85;
elsif rising_edge(clk) then
if prdyo = '1' then
data <= data + 1;
end if;
end if;
pdi <= to_unsigned(data, pdi'length);
pvi <= prdyo;
end process;
tb_data : process (rst, clk, pvo)
begin
if rst = '1' then
data_out <= (others => '0');
elsif rising_edge(clk) then
if pvo = '1' then
data_out <= pdo;
end if;
end if;
end process;
END;
projects/piso_sipo/syn/ise/project/pepExtractor.prj
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work "H:/work/vhdl/projects/piso_sipo/src/piso.vhd"
projects/piso_sipo/syn/ise/project/piso.lso
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work
projects/piso_sipo/syn/ise/project/piso.prj
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vhdl work "../src/piso.vhd"
projects/piso_sipo/syn/ise/project/piso.xst
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set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn piso.prj
-ifmt mixed
-ofn piso
-ofmt NGC
-p xc4vsx35-10-ff668
-top piso
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso piso.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/piso_sipo/syn/ise/project/piso_sipo.ise
BIN
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Binary file not shown.
projects/piso_sipo/syn/ise/project/piso_vhdl.prj
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vhdl work "W:\vhdl\projects\piso_sipo\src\piso.vhd"
projects/piso_sipo/syn/ise/project/prjname.lso
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work
projects/piso_sipo/syn/ise/project/sipo.lso
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work
projects/piso_sipo/syn/ise/project/sipo.prj
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vhdl work "../src/sipo.vhd"
projects/piso_sipo/syn/ise/project/sipo.xst
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set -tmpdir "./xst/projnav.tmp"
set -xsthdpdir "./xst"
run
-ifn sipo.prj
-ifmt mixed
-ofn sipo
-ofmt NGC
-p xc4vsx35-10-ff668
-top sipo
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-lso sipo.lso
-keep_hierarchy NO
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style lut
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract YES
-resource_sharing YES
-async_to_sync NO
-use_dsp48 auto
-iobuf YES
-max_fanout 500
-bufg 32
-bufr 24
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projects/piso_sipo/syn/ise/project/sipo_vhdl.prj
+1
View File
@@ -0,0 +1 @@
vhdl work "W:\vhdl\projects\piso_sipo\src\sipo.vhd"