- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1414 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
File diff suppressed because it is too large
Load Diff
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Load Diff
@@ -0,0 +1,318 @@
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-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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||||
-- This file: The ROM file for use in your VHDL design
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||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
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||||
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-----------------------------------------------------------------------
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LIBRARY ieee;
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||||
use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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library work;
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use work.cpu_pkg.all;
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-- JASM_ROM_INSERT_HERE
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||||
ENTITY xrom IS
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||||
Port (
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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||||
addr : in dmem_addr_t;
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||||
dout : out dmem_data_t
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||||
);
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||||
END xrom;
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||||
|
||||
ARCHITECTURE counter OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from counter.jsm
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||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"4A", -- 0x00
|
||||
X"2D", -- 0x01
|
||||
X"43", -- 0x02
|
||||
X"50", -- 0x03
|
||||
X"55", -- 0x04
|
||||
X"20", -- 0x05
|
||||
X"56", -- 0x06
|
||||
X"31", -- 0x07
|
||||
X"2E", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end counter;
|
||||
|
||||
@@ -0,0 +1,414 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from counter.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"4A", -- 0x00
|
||||
X"2D", -- 0x01
|
||||
X"43", -- 0x02
|
||||
X"50", -- 0x03
|
||||
X"55", -- 0x04
|
||||
X"20", -- 0x05
|
||||
X"56", -- 0x06
|
||||
X"31", -- 0x07
|
||||
X"2E", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -0,0 +1,107 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: cpu_embedded using cpu_core and rom
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.numeric_std.ALL;
|
||||
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
entity cpu_embedded is
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0);
|
||||
io_sel : out STD_LOGIC
|
||||
);
|
||||
end cpu_embedded;
|
||||
|
||||
architecture rtl of cpu_embedded is
|
||||
|
||||
signal rom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0);
|
||||
signal rom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
|
||||
COMPONENT cpu
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0);
|
||||
instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0);
|
||||
xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0);
|
||||
io_sel : out STD_LOGIC
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
|
||||
COMPONENT irom
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
begin
|
||||
|
||||
inst_cpu: cpu
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
int_in => int_in,
|
||||
int_ack => int_ack,
|
||||
xmem_we => xmem_we,
|
||||
xmem_re => xmem_re,
|
||||
instr_din => rom_data,
|
||||
instr_addr => rom_addr,
|
||||
xmem_din => xmem_din,
|
||||
xmem_dout => xmem_dout,
|
||||
xmem_addr => xmem_addr,
|
||||
io_sel => io_sel
|
||||
);
|
||||
|
||||
inst_irom: irom
|
||||
PORT MAP(
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
addr => rom_addr,
|
||||
dout => rom_data
|
||||
);
|
||||
|
||||
end rtl;
|
||||
@@ -0,0 +1,405 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE sdr_test OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 342) of inst_t;
|
||||
|
||||
-- Assembled from sdr_test.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"002", -- 0x000: JMP 0x002
|
||||
"111111" & X"000", -- 0x001: RETI
|
||||
"111011" & X"0B1", -- 0x002: CALL 0x0B1
|
||||
"000011" & X"000", -- 0x003: MOV R00, 0x00
|
||||
"100100" & X"010", -- 0x004: XOUT (0x01), R00
|
||||
"000011" & X"010", -- 0x005: MOV R00, 0x01
|
||||
"111011" & X"0CE", -- 0x006: CALL 0x0CE
|
||||
"101000" & X"070", -- 0x007: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x008: XOUT (0x01), R00
|
||||
"011001" & X"800", -- 0x009: AND R00, 0x80
|
||||
"110010" & X"007", -- 0x00A: JNZ 0x007
|
||||
"000011" & X"001", -- 0x00B: MOV R01, 0x00
|
||||
"111011" & X"0D3", -- 0x00C: CALL 0x0D3
|
||||
"101000" & X"040", -- 0x00D: XIN R00, (0x04)
|
||||
"011011" & X"100", -- 0x00E: OR R00, 0x10
|
||||
"100100" & X"040", -- 0x00F: XOUT (0x04), R00
|
||||
"111011" & X"129", -- 0x010: CALL 0x129
|
||||
"011011" & X"200", -- 0x011: OR R00, 0x20
|
||||
"100100" & X"040", -- 0x012: XOUT (0x04), R00
|
||||
"111011" & X"129", -- 0x013: CALL 0x129
|
||||
"011001" & X"EF0", -- 0x014: AND R00, 0xEF
|
||||
"100100" & X"040", -- 0x015: XOUT (0x04), R00
|
||||
"111011" & X"129", -- 0x016: CALL 0x129
|
||||
"011001" & X"CF0", -- 0x017: AND R00, 0xCF
|
||||
"100100" & X"040", -- 0x018: XOUT (0x04), R00
|
||||
"110000" & X"01A", -- 0x019: JMP 0x01A
|
||||
"000011" & X"010", -- 0x01A: MOV R00, 0x01
|
||||
"111011" & X"0CE", -- 0x01B: CALL 0x0CE
|
||||
"000011" & X"0B1", -- 0x01C: MOV R01, 0x0B
|
||||
"111011" & X"0D3", -- 0x01D: CALL 0x0D3
|
||||
"111011" & X"07F", -- 0x01E: CALL 0x07F
|
||||
"000011" & X"800", -- 0x01F: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x020: MOV R15, 0x08
|
||||
"000111" & X"000", -- 0x021: MOVX (R00), 0x00
|
||||
"010001" & X"010", -- 0x022: INC R00
|
||||
"010101" & X"01F", -- 0x023: DEC R15
|
||||
"110010" & X"021", -- 0x024: JNZ 0x021
|
||||
"101000" & X"0A0", -- 0x025: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x026: CMP R00, 0xFF
|
||||
"111001" & X"031", -- 0x027: JEQ 0x031
|
||||
"101000" & X"070", -- 0x028: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x029: XOUT (0x01), R00
|
||||
"011001" & X"020", -- 0x02A: AND R00, 0x02
|
||||
"110010" & X"028", -- 0x02B: JNZ 0x028
|
||||
"000011" & X"070", -- 0x02C: MOV R00, 0x07
|
||||
"100101" & X"020", -- 0x02D: XOUT (R00), 0x02
|
||||
"000011" & X"020", -- 0x02E: MOV R00, 0x02
|
||||
"111011" & X"086", -- 0x02F: CALL 0x086
|
||||
"110000" & X"025", -- 0x030: JMP 0x025
|
||||
"111011" & X"096", -- 0x031: CALL 0x096
|
||||
"111011" & X"122", -- 0x032: CALL 0x122
|
||||
"000011" & X"010", -- 0x033: MOV R00, 0x01
|
||||
"111011" & X"0CE", -- 0x034: CALL 0x0CE
|
||||
"000011" & X"1A1", -- 0x035: MOV R01, 0x1A
|
||||
"111011" & X"0D3", -- 0x036: CALL 0x0D3
|
||||
"111011" & X"07F", -- 0x037: CALL 0x07F
|
||||
"000011" & X"000", -- 0x038: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x039: MOVC (0x00), R00
|
||||
"101000" & X"0A0", -- 0x03A: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x03B: CMP R00, 0xFF
|
||||
"111001" & X"051", -- 0x03C: JEQ 0x051
|
||||
"001010" & X"001", -- 0x03D: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x03E: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x03F: MOV R15, 0x08
|
||||
"000110" & X"001", -- 0x040: MOVX (R01), R00
|
||||
"010001" & X"010", -- 0x041: INC R00
|
||||
"010001" & X"011", -- 0x042: INC R01
|
||||
"010101" & X"01F", -- 0x043: DEC R15
|
||||
"110010" & X"040", -- 0x044: JNZ 0x040
|
||||
"101000" & X"070", -- 0x045: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x046: XOUT (0x01), R00
|
||||
"011001" & X"020", -- 0x047: AND R00, 0x02
|
||||
"110010" & X"045", -- 0x048: JNZ 0x045
|
||||
"000011" & X"070", -- 0x049: MOV R00, 0x07
|
||||
"100101" & X"020", -- 0x04A: XOUT (R00), 0x02
|
||||
"000011" & X"020", -- 0x04B: MOV R00, 0x02
|
||||
"111011" & X"086", -- 0x04C: CALL 0x086
|
||||
"001010" & X"000", -- 0x04D: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x04E: INC R00
|
||||
"001101" & X"000", -- 0x04F: MOVC (0x00), R00
|
||||
"110000" & X"03A", -- 0x050: JMP 0x03A
|
||||
"111011" & X"096", -- 0x051: CALL 0x096
|
||||
"111011" & X"122", -- 0x052: CALL 0x122
|
||||
"000011" & X"010", -- 0x053: MOV R00, 0x01
|
||||
"111011" & X"0CE", -- 0x054: CALL 0x0CE
|
||||
"000011" & X"281", -- 0x055: MOV R01, 0x28
|
||||
"111011" & X"0D3", -- 0x056: CALL 0x0D3
|
||||
"111011" & X"07F", -- 0x057: CALL 0x07F
|
||||
"000011" & X"000", -- 0x058: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x059: MOVC (0x00), R00
|
||||
"101000" & X"0A0", -- 0x05A: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x05B: CMP R00, 0xFF
|
||||
"111001" & X"073", -- 0x05C: JEQ 0x073
|
||||
"000011" & X"070", -- 0x05D: MOV R00, 0x07
|
||||
"100101" & X"010", -- 0x05E: XOUT (R00), 0x01
|
||||
"101000" & X"070", -- 0x05F: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x060: XOUT (0x01), R00
|
||||
"011001" & X"010", -- 0x061: AND R00, 0x01
|
||||
"110010" & X"05F", -- 0x062: JNZ 0x05F
|
||||
"001010" & X"001", -- 0x063: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x064: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x065: MOV R15, 0x08
|
||||
"000100" & X"002", -- 0x066: MOVX R02, (R00)
|
||||
"001110" & X"012", -- 0x067: CMP R02, R01
|
||||
"111010" & X"078", -- 0x068: JNE 0x078
|
||||
"010001" & X"010", -- 0x069: INC R00
|
||||
"010001" & X"011", -- 0x06A: INC R01
|
||||
"010101" & X"01F", -- 0x06B: DEC R15
|
||||
"110010" & X"066", -- 0x06C: JNZ 0x066
|
||||
"000011" & X"020", -- 0x06D: MOV R00, 0x02
|
||||
"111011" & X"086", -- 0x06E: CALL 0x086
|
||||
"001010" & X"000", -- 0x06F: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x070: INC R00
|
||||
"001101" & X"000", -- 0x071: MOVC (0x00), R00
|
||||
"110000" & X"05A", -- 0x072: JMP 0x05A
|
||||
"000011" & X"C00", -- 0x073: MOV R00, 0xC0
|
||||
"111011" & X"0CE", -- 0x074: CALL 0x0CE
|
||||
"000011" & X"361", -- 0x075: MOV R01, 0x36
|
||||
"111011" & X"0D3", -- 0x076: CALL 0x0D3
|
||||
"110000" & X"07D", -- 0x077: JMP 0x07D
|
||||
"000011" & X"C00", -- 0x078: MOV R00, 0xC0
|
||||
"111011" & X"0CE", -- 0x079: CALL 0x0CE
|
||||
"000011" & X"401", -- 0x07A: MOV R01, 0x40
|
||||
"111011" & X"0D3", -- 0x07B: CALL 0x0D3
|
||||
"110000" & X"07D", -- 0x07C: JMP 0x07D
|
||||
"111011" & X"122", -- 0x07D: CALL 0x122
|
||||
"110000" & X"01A", -- 0x07E: JMP 0x01A
|
||||
"111100" & X"000", -- 0x07F: PUSH R00
|
||||
"000011" & X"000", -- 0x080: MOV R00, 0x00
|
||||
"100100" & X"080", -- 0x081: XOUT (0x08), R00
|
||||
"100100" & X"090", -- 0x082: XOUT (0x09), R00
|
||||
"100100" & X"0A0", -- 0x083: XOUT (0x0A), R00
|
||||
"111101" & X"000", -- 0x084: POP R00
|
||||
"111110" & X"000", -- 0x085: RET
|
||||
"111100" & X"001", -- 0x086: PUSH R01
|
||||
"111100" & X"002", -- 0x087: PUSH R02
|
||||
"111100" & X"003", -- 0x088: PUSH R03
|
||||
"101000" & X"081", -- 0x089: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x08A: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x08B: XIN R03, (0x0A)
|
||||
"010000" & X"001", -- 0x08C: ADD R01, R00
|
||||
"010011" & X"002", -- 0x08D: ADDC R02, 0x00
|
||||
"010011" & X"003", -- 0x08E: ADDC R03, 0x00
|
||||
"100100" & X"081", -- 0x08F: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x090: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x091: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x092: POP R03
|
||||
"111101" & X"002", -- 0x093: POP R02
|
||||
"111101" & X"001", -- 0x094: POP R01
|
||||
"111110" & X"000", -- 0x095: RET
|
||||
"000011" & X"C00", -- 0x096: MOV R00, 0xC0
|
||||
"111011" & X"0CE", -- 0x097: CALL 0x0CE
|
||||
"101000" & X"0A0", -- 0x098: XIN R00, (0x0A)
|
||||
"111011" & X"09F", -- 0x099: CALL 0x09F
|
||||
"101000" & X"090", -- 0x09A: XIN R00, (0x09)
|
||||
"111011" & X"09F", -- 0x09B: CALL 0x09F
|
||||
"101000" & X"080", -- 0x09C: XIN R00, (0x08)
|
||||
"111011" & X"09F", -- 0x09D: CALL 0x09F
|
||||
"111110" & X"000", -- 0x09E: RET
|
||||
"111011" & X"0AA", -- 0x09F: CALL 0x0AA
|
||||
"111011" & X"0E5", -- 0x0A0: CALL 0x0E5
|
||||
"000010" & X"010", -- 0x0A1: MOV R00, R01
|
||||
"111011" & X"0E5", -- 0x0A2: CALL 0x0E5
|
||||
"111110" & X"000", -- 0x0A3: RET
|
||||
"011001" & X"0F0", -- 0x0A4: AND R00, 0x0F
|
||||
"001111" & X"0A0", -- 0x0A5: CMP R00, 0x0A
|
||||
"110101" & X"0A8", -- 0x0A6: JLT 0x0A8
|
||||
"010001" & X"070", -- 0x0A7: ADD R00, 0x07
|
||||
"010001" & X"300", -- 0x0A8: ADD R00, 0x30
|
||||
"111110" & X"000", -- 0x0A9: RET
|
||||
"111100" & X"000", -- 0x0AA: PUSH R00
|
||||
"111011" & X"0A4", -- 0x0AB: CALL 0x0A4
|
||||
"000010" & X"001", -- 0x0AC: MOV R01, R00
|
||||
"111101" & X"000", -- 0x0AD: POP R00
|
||||
"101010" & X"000", -- 0x0AE: SWAP R00
|
||||
"111011" & X"0A4", -- 0x0AF: CALL 0x0A4
|
||||
"111110" & X"000", -- 0x0B0: RET
|
||||
"000011" & X"002", -- 0x0B1: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x0B2: MOV R00, 0x03
|
||||
"111011" & X"0FD", -- 0x0B3: CALL 0x0FD
|
||||
"111011" & X"130", -- 0x0B4: CALL 0x130
|
||||
"000011" & X"002", -- 0x0B5: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x0B6: MOV R00, 0x03
|
||||
"111011" & X"0FD", -- 0x0B7: CALL 0x0FD
|
||||
"111011" & X"130", -- 0x0B8: CALL 0x130
|
||||
"000011" & X"002", -- 0x0B9: MOV R02, 0x00
|
||||
"000011" & X"020", -- 0x0BA: MOV R00, 0x02
|
||||
"111011" & X"0FD", -- 0x0BB: CALL 0x0FD
|
||||
"111011" & X"137", -- 0x0BC: CALL 0x137
|
||||
"000011" & X"280", -- 0x0BD: MOV R00, 0x28
|
||||
"111011" & X"0CE", -- 0x0BE: CALL 0x0CE
|
||||
"000011" & X"0C0", -- 0x0BF: MOV R00, 0x0C
|
||||
"111011" & X"0CE", -- 0x0C0: CALL 0x0CE
|
||||
"000011" & X"060", -- 0x0C1: MOV R00, 0x06
|
||||
"111011" & X"0CE", -- 0x0C2: CALL 0x0CE
|
||||
"000011" & X"010", -- 0x0C3: MOV R00, 0x01
|
||||
"111011" & X"0CE", -- 0x0C4: CALL 0x0CE
|
||||
"111110" & X"000", -- 0x0C5: RET
|
||||
"111100" & X"000", -- 0x0C6: PUSH R00
|
||||
"111011" & X"0F1", -- 0x0C7: CALL 0x0F1
|
||||
"011001" & X"800", -- 0x0C8: AND R00, 0x80
|
||||
"110001" & X"0CC", -- 0x0C9: JZ 0x0CC
|
||||
"111011" & X"14E", -- 0x0CA: CALL 0x14E
|
||||
"110000" & X"0C7", -- 0x0CB: JMP 0x0C7
|
||||
"111101" & X"000", -- 0x0CC: POP R00
|
||||
"111110" & X"000", -- 0x0CD: RET
|
||||
"111100" & X"002", -- 0x0CE: PUSH R02
|
||||
"000011" & X"002", -- 0x0CF: MOV R02, 0x00
|
||||
"111011" & X"0EA", -- 0x0D0: CALL 0x0EA
|
||||
"111101" & X"002", -- 0x0D1: POP R02
|
||||
"111110" & X"000", -- 0x0D2: RET
|
||||
"111100" & X"000", -- 0x0D3: PUSH R00
|
||||
"000100" & X"010", -- 0x0D4: MOVX R00, (R01)
|
||||
"010001" & X"011", -- 0x0D5: INC R01
|
||||
"001111" & X"000", -- 0x0D6: TST R00
|
||||
"110001" & X"0DA", -- 0x0D7: JZ 0x0DA
|
||||
"111011" & X"0E5", -- 0x0D8: CALL 0x0E5
|
||||
"110000" & X"0D4", -- 0x0D9: JMP 0x0D4
|
||||
"111101" & X"000", -- 0x0DA: POP R00
|
||||
"111110" & X"000", -- 0x0DB: RET
|
||||
"111100" & X"000", -- 0x0DC: PUSH R00
|
||||
"001001" & X"010", -- 0x0DD: MOVC R00, (R01)
|
||||
"010001" & X"011", -- 0x0DE: INC R01
|
||||
"001111" & X"000", -- 0x0DF: TST R00
|
||||
"110001" & X"0E3", -- 0x0E0: JZ 0x0E3
|
||||
"111011" & X"0E5", -- 0x0E1: CALL 0x0E5
|
||||
"110000" & X"0DD", -- 0x0E2: JMP 0x0DD
|
||||
"111101" & X"000", -- 0x0E3: POP R00
|
||||
"111110" & X"000", -- 0x0E4: RET
|
||||
"111100" & X"002", -- 0x0E5: PUSH R02
|
||||
"000011" & X"402", -- 0x0E6: MOV R02, 0x40
|
||||
"111011" & X"0EA", -- 0x0E7: CALL 0x0EA
|
||||
"111101" & X"002", -- 0x0E8: POP R02
|
||||
"111110" & X"000", -- 0x0E9: RET
|
||||
"111011" & X"0C6", -- 0x0EA: CALL 0x0C6
|
||||
"111100" & X"000", -- 0x0EB: PUSH R00
|
||||
"101010" & X"000", -- 0x0EC: SWAP R00
|
||||
"111011" & X"0FD", -- 0x0ED: CALL 0x0FD
|
||||
"111101" & X"000", -- 0x0EE: POP R00
|
||||
"111011" & X"0FD", -- 0x0EF: CALL 0x0FD
|
||||
"111110" & X"000", -- 0x0F0: RET
|
||||
"111100" & X"002", -- 0x0F1: PUSH R02
|
||||
"000011" & X"002", -- 0x0F2: MOV R02, 0x00
|
||||
"111011" & X"0F6", -- 0x0F3: CALL 0x0F6
|
||||
"111101" & X"002", -- 0x0F4: POP R02
|
||||
"111110" & X"000", -- 0x0F5: RET
|
||||
"111011" & X"110", -- 0x0F6: CALL 0x110
|
||||
"101010" & X"000", -- 0x0F7: SWAP R00
|
||||
"111100" & X"000", -- 0x0F8: PUSH R00
|
||||
"111011" & X"110", -- 0x0F9: CALL 0x110
|
||||
"111101" & X"002", -- 0x0FA: POP R02
|
||||
"011010" & X"020", -- 0x0FB: OR R00, R02
|
||||
"111110" & X"000", -- 0x0FC: RET
|
||||
"111100" & X"001", -- 0x0FD: PUSH R01
|
||||
"011001" & X"0F0", -- 0x0FE: AND R00, 0x0F
|
||||
"000010" & X"001", -- 0x0FF: MOV R01, R00
|
||||
"011010" & X"021", -- 0x100: OR R01, R02
|
||||
"100100" & X"031", -- 0x101: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x102: CALL 0x14E
|
||||
"000010" & X"001", -- 0x103: MOV R01, R00
|
||||
"011010" & X"021", -- 0x104: OR R01, R02
|
||||
"011011" & X"801", -- 0x105: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x106: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x107: CALL 0x14E
|
||||
"000010" & X"001", -- 0x108: MOV R01, R00
|
||||
"011010" & X"021", -- 0x109: OR R01, R02
|
||||
"100100" & X"031", -- 0x10A: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x10B: CALL 0x14E
|
||||
"011011" & X"201", -- 0x10C: OR R01, 0x20
|
||||
"100100" & X"031", -- 0x10D: XOUT (0x03), R01
|
||||
"111101" & X"001", -- 0x10E: POP R01
|
||||
"111110" & X"000", -- 0x10F: RET
|
||||
"111100" & X"001", -- 0x110: PUSH R01
|
||||
"000011" & X"201", -- 0x111: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x112: OR R01, R02
|
||||
"100100" & X"031", -- 0x113: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x114: CALL 0x14E
|
||||
"000011" & X"201", -- 0x115: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x116: OR R01, R02
|
||||
"011011" & X"801", -- 0x117: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x118: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x119: CALL 0x14E
|
||||
"101000" & X"030", -- 0x11A: XIN R00, (0x03)
|
||||
"011001" & X"0F0", -- 0x11B: AND R00, 0x0F
|
||||
"000011" & X"201", -- 0x11C: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x11D: OR R01, R02
|
||||
"100100" & X"031", -- 0x11E: XOUT (0x03), R01
|
||||
"111011" & X"14E", -- 0x11F: CALL 0x14E
|
||||
"111101" & X"001", -- 0x120: POP R01
|
||||
"111110" & X"000", -- 0x121: RET
|
||||
"111100" & X"00F", -- 0x122: PUSH R15
|
||||
"000011" & X"0AF", -- 0x123: MOV R15, 0x0A
|
||||
"111011" & X"129", -- 0x124: CALL 0x129
|
||||
"010101" & X"01F", -- 0x125: DEC R15
|
||||
"110010" & X"124", -- 0x126: JNZ 0x124
|
||||
"111101" & X"00F", -- 0x127: POP R15
|
||||
"111110" & X"000", -- 0x128: RET
|
||||
"111100" & X"00F", -- 0x129: PUSH R15
|
||||
"000011" & X"0AF", -- 0x12A: MOV R15, 0x0A
|
||||
"111011" & X"130", -- 0x12B: CALL 0x130
|
||||
"010101" & X"01F", -- 0x12C: DEC R15
|
||||
"110010" & X"12B", -- 0x12D: JNZ 0x12B
|
||||
"111101" & X"00F", -- 0x12E: POP R15
|
||||
"111110" & X"000", -- 0x12F: RET
|
||||
"111100" & X"00F", -- 0x130: PUSH R15
|
||||
"000011" & X"0AF", -- 0x131: MOV R15, 0x0A
|
||||
"111011" & X"137", -- 0x132: CALL 0x137
|
||||
"010101" & X"01F", -- 0x133: DEC R15
|
||||
"110010" & X"132", -- 0x134: JNZ 0x132
|
||||
"111101" & X"00F", -- 0x135: POP R15
|
||||
"111110" & X"000", -- 0x136: RET
|
||||
"111100" & X"00F", -- 0x137: PUSH R15
|
||||
"000011" & X"0AF", -- 0x138: MOV R15, 0x0A
|
||||
"111011" & X"13E", -- 0x139: CALL 0x13E
|
||||
"010101" & X"01F", -- 0x13A: DEC R15
|
||||
"110010" & X"139", -- 0x13B: JNZ 0x139
|
||||
"111101" & X"00F", -- 0x13C: POP R15
|
||||
"111110" & X"000", -- 0x13D: RET
|
||||
"111100" & X"00F", -- 0x13E: PUSH R15
|
||||
"000011" & X"0AF", -- 0x13F: MOV R15, 0x0A
|
||||
"111011" & X"145", -- 0x140: CALL 0x145
|
||||
"010101" & X"01F", -- 0x141: DEC R15
|
||||
"110010" & X"140", -- 0x142: JNZ 0x140
|
||||
"111101" & X"00F", -- 0x143: POP R15
|
||||
"111110" & X"000", -- 0x144: RET
|
||||
"111100" & X"00F", -- 0x145: PUSH R15
|
||||
"000011" & X"63F", -- 0x146: MOV R15, 0x63
|
||||
"000000" & X"000", -- 0x147: NOP
|
||||
"000000" & X"000", -- 0x148: NOP
|
||||
"000000" & X"000", -- 0x149: NOP
|
||||
"010101" & X"01F", -- 0x14A: DEC R15
|
||||
"110010" & X"147", -- 0x14B: JNZ 0x147
|
||||
"111101" & X"00F", -- 0x14C: POP R15
|
||||
"111110" & X"000", -- 0x14D: RET
|
||||
"111100" & X"00F", -- 0x14E: PUSH R15
|
||||
"000011" & X"09F", -- 0x14F: MOV R15, 0x09
|
||||
"000000" & X"000", -- 0x150: NOP
|
||||
"000000" & X"000", -- 0x151: NOP
|
||||
"000000" & X"000", -- 0x152: NOP
|
||||
"010101" & X"01F", -- 0x153: DEC R15
|
||||
"110010" & X"150", -- 0x154: JNZ 0x150
|
||||
"111101" & X"00F", -- 0x155: POP R15
|
||||
"111110" & X"000" -- 0x156: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdr_test;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,172 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE sdr_test_short OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 110) of inst_t;
|
||||
|
||||
-- Assembled from sdr_test_short.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"002", -- 0x000: JMP 0x002
|
||||
"111111" & X"000", -- 0x001: RETI
|
||||
"000011" & X"000", -- 0x002: MOV R00, 0x00
|
||||
"100100" & X"010", -- 0x003: XOUT (0x01), R00
|
||||
"101000" & X"040", -- 0x004: XIN R00, (0x04)
|
||||
"011001" & X"CF0", -- 0x005: AND R00, 0xCF
|
||||
"100100" & X"040", -- 0x006: XOUT (0x04), R00
|
||||
"101000" & X"070", -- 0x007: XIN R00, (0x07)
|
||||
"011001" & X"800", -- 0x008: AND R00, 0x80
|
||||
"110010" & X"007", -- 0x009: JNZ 0x007
|
||||
"110000" & X"00B", -- 0x00A: JMP 0x00B
|
||||
"111011" & X"058", -- 0x00B: CALL 0x058
|
||||
"000011" & X"800", -- 0x00C: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x00D: MOV R15, 0x08
|
||||
"000111" & X"000", -- 0x00E: MOVX (R00), 0x00
|
||||
"010001" & X"010", -- 0x00F: INC R00
|
||||
"010101" & X"01F", -- 0x010: DEC R15
|
||||
"110010" & X"00E", -- 0x011: JNZ 0x00E
|
||||
"101000" & X"080", -- 0x012: XIN R00, (0x08)
|
||||
"001111" & X"080", -- 0x013: CMP R00, 0x08
|
||||
"111001" & X"01D", -- 0x014: JEQ 0x01D
|
||||
"101000" & X"070", -- 0x015: XIN R00, (0x07)
|
||||
"011001" & X"020", -- 0x016: AND R00, 0x02
|
||||
"110010" & X"015", -- 0x017: JNZ 0x015
|
||||
"000011" & X"070", -- 0x018: MOV R00, 0x07
|
||||
"100101" & X"020", -- 0x019: XOUT (R00), 0x02
|
||||
"000011" & X"020", -- 0x01A: MOV R00, 0x02
|
||||
"111011" & X"05F", -- 0x01B: CALL 0x05F
|
||||
"110000" & X"012", -- 0x01C: JMP 0x012
|
||||
"111011" & X"058", -- 0x01D: CALL 0x058
|
||||
"000011" & X"000", -- 0x01E: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x01F: MOVC (0x00), R00
|
||||
"101000" & X"080", -- 0x020: XIN R00, (0x08)
|
||||
"001111" & X"080", -- 0x021: CMP R00, 0x08
|
||||
"111001" & X"037", -- 0x022: JEQ 0x037
|
||||
"001010" & X"001", -- 0x023: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x024: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x025: MOV R15, 0x08
|
||||
"000110" & X"001", -- 0x026: MOVX (R01), R00
|
||||
"010001" & X"010", -- 0x027: INC R00
|
||||
"010001" & X"011", -- 0x028: INC R01
|
||||
"010101" & X"01F", -- 0x029: DEC R15
|
||||
"110010" & X"026", -- 0x02A: JNZ 0x026
|
||||
"101000" & X"070", -- 0x02B: XIN R00, (0x07)
|
||||
"011001" & X"020", -- 0x02C: AND R00, 0x02
|
||||
"110010" & X"02B", -- 0x02D: JNZ 0x02B
|
||||
"000000" & X"000", -- 0x02E: NOP
|
||||
"000011" & X"070", -- 0x02F: MOV R00, 0x07
|
||||
"100101" & X"020", -- 0x030: XOUT (R00), 0x02
|
||||
"000011" & X"020", -- 0x031: MOV R00, 0x02
|
||||
"111011" & X"05F", -- 0x032: CALL 0x05F
|
||||
"001010" & X"000", -- 0x033: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x034: INC R00
|
||||
"001101" & X"000", -- 0x035: MOVC (0x00), R00
|
||||
"110000" & X"020", -- 0x036: JMP 0x020
|
||||
"111011" & X"058", -- 0x037: CALL 0x058
|
||||
"000011" & X"000", -- 0x038: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x039: MOVC (0x00), R00
|
||||
"101000" & X"080", -- 0x03A: XIN R00, (0x08)
|
||||
"001111" & X"080", -- 0x03B: CMP R00, 0x08
|
||||
"111001" & X"052", -- 0x03C: JEQ 0x052
|
||||
"000011" & X"070", -- 0x03D: MOV R00, 0x07
|
||||
"100101" & X"010", -- 0x03E: XOUT (R00), 0x01
|
||||
"101000" & X"070", -- 0x03F: XIN R00, (0x07)
|
||||
"011001" & X"010", -- 0x040: AND R00, 0x01
|
||||
"110010" & X"03F", -- 0x041: JNZ 0x03F
|
||||
"001010" & X"001", -- 0x042: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x043: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x044: MOV R15, 0x08
|
||||
"000100" & X"002", -- 0x045: MOVX R02, (R00)
|
||||
"001110" & X"012", -- 0x046: CMP R02, R01
|
||||
"111010" & X"053", -- 0x047: JNE 0x053
|
||||
"010001" & X"010", -- 0x048: INC R00
|
||||
"010001" & X"011", -- 0x049: INC R01
|
||||
"010101" & X"01F", -- 0x04A: DEC R15
|
||||
"110010" & X"045", -- 0x04B: JNZ 0x045
|
||||
"000011" & X"020", -- 0x04C: MOV R00, 0x02
|
||||
"111011" & X"05F", -- 0x04D: CALL 0x05F
|
||||
"001010" & X"000", -- 0x04E: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x04F: INC R00
|
||||
"001101" & X"000", -- 0x050: MOVC (0x00), R00
|
||||
"110000" & X"03A", -- 0x051: JMP 0x03A
|
||||
"110000" & X"057", -- 0x052: JMP 0x057
|
||||
"101000" & X"040", -- 0x053: XIN R00, (0x04)
|
||||
"011011" & X"100", -- 0x054: OR R00, 0x10
|
||||
"100100" & X"040", -- 0x055: XOUT (0x04), R00
|
||||
"110000" & X"057", -- 0x056: JMP 0x057
|
||||
"110000" & X"057", -- 0x057: JMP 0x057
|
||||
"111100" & X"000", -- 0x058: PUSH R00
|
||||
"000011" & X"000", -- 0x059: MOV R00, 0x00
|
||||
"100100" & X"080", -- 0x05A: XOUT (0x08), R00
|
||||
"100100" & X"090", -- 0x05B: XOUT (0x09), R00
|
||||
"100100" & X"0A0", -- 0x05C: XOUT (0x0A), R00
|
||||
"111101" & X"000", -- 0x05D: POP R00
|
||||
"111110" & X"000", -- 0x05E: RET
|
||||
"111100" & X"001", -- 0x05F: PUSH R01
|
||||
"111100" & X"002", -- 0x060: PUSH R02
|
||||
"111100" & X"003", -- 0x061: PUSH R03
|
||||
"101000" & X"081", -- 0x062: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x063: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x064: XIN R03, (0x0A)
|
||||
"010000" & X"001", -- 0x065: ADD R01, R00
|
||||
"010011" & X"002", -- 0x066: ADDC R02, 0x00
|
||||
"010011" & X"003", -- 0x067: ADDC R03, 0x00
|
||||
"100100" & X"081", -- 0x068: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x069: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x06A: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x06B: POP R03
|
||||
"111101" & X"002", -- 0x06C: POP R02
|
||||
"111101" & X"001", -- 0x06D: POP R01
|
||||
"111110" & X"000" -- 0x06E: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdr_test_short;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,317 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE sdr_test_short OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from sdr_test_short.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"00", -- 0x00
|
||||
X"00", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"00", -- 0x03
|
||||
X"00", -- 0x04
|
||||
X"00", -- 0x05
|
||||
X"00", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdr_test_short;
|
||||
|
||||
@@ -0,0 +1,413 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from sdr_test_short.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"00", -- 0x00
|
||||
X"00", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"00", -- 0x03
|
||||
X"00", -- 0x04
|
||||
X"00", -- 0x05
|
||||
X"00", -- 0x06
|
||||
X"00", -- 0x07
|
||||
X"00", -- 0x08
|
||||
X"00", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"00", -- 0x0B
|
||||
X"00", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"00", -- 0x0E
|
||||
X"00", -- 0x0F
|
||||
X"00", -- 0x10
|
||||
X"00", -- 0x11
|
||||
X"00", -- 0x12
|
||||
X"00", -- 0x13
|
||||
X"00", -- 0x14
|
||||
X"00", -- 0x15
|
||||
X"00", -- 0x16
|
||||
X"00", -- 0x17
|
||||
X"00", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"00", -- 0x1A
|
||||
X"00", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"00", -- 0x1D
|
||||
X"00", -- 0x1E
|
||||
X"00", -- 0x1F
|
||||
X"00", -- 0x20
|
||||
X"00", -- 0x21
|
||||
X"00", -- 0x22
|
||||
X"00", -- 0x23
|
||||
X"00", -- 0x24
|
||||
X"00", -- 0x25
|
||||
X"00", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"00", -- 0x28
|
||||
X"00", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"00", -- 0x2B
|
||||
X"00", -- 0x2C
|
||||
X"00", -- 0x2D
|
||||
X"00", -- 0x2E
|
||||
X"00", -- 0x2F
|
||||
X"00", -- 0x30
|
||||
X"00", -- 0x31
|
||||
X"00", -- 0x32
|
||||
X"00", -- 0x33
|
||||
X"00", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"00", -- 0x36
|
||||
X"00", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"00", -- 0x39
|
||||
X"00", -- 0x3A
|
||||
X"00", -- 0x3B
|
||||
X"00", -- 0x3C
|
||||
X"00", -- 0x3D
|
||||
X"00", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"00", -- 0x40
|
||||
X"00", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"00", -- 0x43
|
||||
X"00", -- 0x44
|
||||
X"00", -- 0x45
|
||||
X"00", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"00", -- 0x48
|
||||
X"00", -- 0x49
|
||||
X"00", -- 0x4A
|
||||
X"00", -- 0x4B
|
||||
X"00", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"00", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -0,0 +1,318 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE sdr_test OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from sdr_test.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"53", -- 0x00
|
||||
X"44", -- 0x01
|
||||
X"52", -- 0x02
|
||||
X"41", -- 0x03
|
||||
X"4D", -- 0x04
|
||||
X"20", -- 0x05
|
||||
X"54", -- 0x06
|
||||
X"65", -- 0x07
|
||||
X"73", -- 0x08
|
||||
X"74", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"43", -- 0x0B
|
||||
X"6C", -- 0x0C
|
||||
X"65", -- 0x0D
|
||||
X"61", -- 0x0E
|
||||
X"72", -- 0x0F
|
||||
X"69", -- 0x10
|
||||
X"6E", -- 0x11
|
||||
X"67", -- 0x12
|
||||
X"20", -- 0x13
|
||||
X"53", -- 0x14
|
||||
X"44", -- 0x15
|
||||
X"52", -- 0x16
|
||||
X"41", -- 0x17
|
||||
X"4D", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"57", -- 0x1A
|
||||
X"72", -- 0x1B
|
||||
X"69", -- 0x1C
|
||||
X"74", -- 0x1D
|
||||
X"69", -- 0x1E
|
||||
X"6E", -- 0x1F
|
||||
X"67", -- 0x20
|
||||
X"20", -- 0x21
|
||||
X"53", -- 0x22
|
||||
X"44", -- 0x23
|
||||
X"52", -- 0x24
|
||||
X"41", -- 0x25
|
||||
X"4D", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"52", -- 0x28
|
||||
X"65", -- 0x29
|
||||
X"61", -- 0x2A
|
||||
X"64", -- 0x2B
|
||||
X"69", -- 0x2C
|
||||
X"6E", -- 0x2D
|
||||
X"67", -- 0x2E
|
||||
X"20", -- 0x2F
|
||||
X"53", -- 0x30
|
||||
X"44", -- 0x31
|
||||
X"52", -- 0x32
|
||||
X"41", -- 0x33
|
||||
X"4D", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"56", -- 0x36
|
||||
X"65", -- 0x37
|
||||
X"72", -- 0x38
|
||||
X"69", -- 0x39
|
||||
X"66", -- 0x3A
|
||||
X"79", -- 0x3B
|
||||
X"20", -- 0x3C
|
||||
X"4F", -- 0x3D
|
||||
X"4B", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"56", -- 0x40
|
||||
X"65", -- 0x41
|
||||
X"72", -- 0x42
|
||||
X"69", -- 0x43
|
||||
X"66", -- 0x44
|
||||
X"79", -- 0x45
|
||||
X"20", -- 0x46
|
||||
X"46", -- 0x47
|
||||
X"61", -- 0x48
|
||||
X"69", -- 0x49
|
||||
X"6C", -- 0x4A
|
||||
X"65", -- 0x4B
|
||||
X"64", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdr_test;
|
||||
|
||||
@@ -0,0 +1,414 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from sdr_test.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"53", -- 0x00
|
||||
X"44", -- 0x01
|
||||
X"52", -- 0x02
|
||||
X"41", -- 0x03
|
||||
X"4D", -- 0x04
|
||||
X"20", -- 0x05
|
||||
X"54", -- 0x06
|
||||
X"65", -- 0x07
|
||||
X"73", -- 0x08
|
||||
X"74", -- 0x09
|
||||
X"00", -- 0x0A
|
||||
X"43", -- 0x0B
|
||||
X"6C", -- 0x0C
|
||||
X"65", -- 0x0D
|
||||
X"61", -- 0x0E
|
||||
X"72", -- 0x0F
|
||||
X"69", -- 0x10
|
||||
X"6E", -- 0x11
|
||||
X"67", -- 0x12
|
||||
X"20", -- 0x13
|
||||
X"53", -- 0x14
|
||||
X"44", -- 0x15
|
||||
X"52", -- 0x16
|
||||
X"41", -- 0x17
|
||||
X"4D", -- 0x18
|
||||
X"00", -- 0x19
|
||||
X"57", -- 0x1A
|
||||
X"72", -- 0x1B
|
||||
X"69", -- 0x1C
|
||||
X"74", -- 0x1D
|
||||
X"69", -- 0x1E
|
||||
X"6E", -- 0x1F
|
||||
X"67", -- 0x20
|
||||
X"20", -- 0x21
|
||||
X"53", -- 0x22
|
||||
X"44", -- 0x23
|
||||
X"52", -- 0x24
|
||||
X"41", -- 0x25
|
||||
X"4D", -- 0x26
|
||||
X"00", -- 0x27
|
||||
X"52", -- 0x28
|
||||
X"65", -- 0x29
|
||||
X"61", -- 0x2A
|
||||
X"64", -- 0x2B
|
||||
X"69", -- 0x2C
|
||||
X"6E", -- 0x2D
|
||||
X"67", -- 0x2E
|
||||
X"20", -- 0x2F
|
||||
X"53", -- 0x30
|
||||
X"44", -- 0x31
|
||||
X"52", -- 0x32
|
||||
X"41", -- 0x33
|
||||
X"4D", -- 0x34
|
||||
X"00", -- 0x35
|
||||
X"56", -- 0x36
|
||||
X"65", -- 0x37
|
||||
X"72", -- 0x38
|
||||
X"69", -- 0x39
|
||||
X"66", -- 0x3A
|
||||
X"79", -- 0x3B
|
||||
X"20", -- 0x3C
|
||||
X"4F", -- 0x3D
|
||||
X"4B", -- 0x3E
|
||||
X"00", -- 0x3F
|
||||
X"56", -- 0x40
|
||||
X"65", -- 0x41
|
||||
X"72", -- 0x42
|
||||
X"69", -- 0x43
|
||||
X"66", -- 0x44
|
||||
X"79", -- 0x45
|
||||
X"20", -- 0x46
|
||||
X"46", -- 0x47
|
||||
X"61", -- 0x48
|
||||
X"69", -- 0x49
|
||||
X"6C", -- 0x4A
|
||||
X"65", -- 0x4B
|
||||
X"64", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -0,0 +1,74 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: SDRAM controller
|
||||
-- This file: User SDRAM component adjustments
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
package sdram_config is
|
||||
|
||||
constant DDR_DATA_WIDTH : positive := 32; -- External DDR-SDRAM Module data bus width
|
||||
constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module
|
||||
constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM
|
||||
constant DDR_ROW_ADDR_WIDTH : positive := 13; --
|
||||
constant DDR_COL_ADDR_WIDTH : positive := 9; --
|
||||
|
||||
constant LMR_REG_BASE : natural := 0;
|
||||
constant LMR_REG_EXTENDED : natural := 1;
|
||||
constant LMR_OP_NORMAL : natural := 0;
|
||||
constant LMR_OP_RES_DLL : natural := 2;
|
||||
constant LMR_BT_SEQ : natural := 0;
|
||||
constant LMR_BT_ILVD : natural := 1;
|
||||
constant LMR_BL2 : natural := 1;
|
||||
constant LMR_BL4 : natural := 2;
|
||||
constant LMR_BL8 : natural := 3;
|
||||
constant LMR_CL2 : natural := 2;
|
||||
constant LMR_CL3 : natural := 3;
|
||||
constant LMR_CL2_5 : natural := 6;
|
||||
|
||||
-- DDR SDRAM Hardware defined constants
|
||||
constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet)
|
||||
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
|
||||
constant ENABLE_PRE_ALL : std_logic := '1';
|
||||
constant ENABLE_AUTO_PRE : std_logic := '0';
|
||||
|
||||
-- DDR-SDR TIMING constants ------------------------------------------------------------------
|
||||
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh
|
||||
constant REFRESH_INTERVAL : real := 7.8125; -- us
|
||||
|
||||
-- These values are for your SDRAM part (see datasheet)
|
||||
constant TCAS : positive := 2; -- CAS latency [clocks]
|
||||
constant TRP : positive := 2; -- precharge command period
|
||||
constant TRAS : positive := 5; -- active to precharge delay
|
||||
constant TRFC : positive := 8; -- auto refresh command period
|
||||
constant TMRD : positive := 2; -- load mode register command cylce time
|
||||
constant TRCD : positive := 2; -- active to read or write delay !
|
||||
constant TWR : positive := 2; -- write recovery time
|
||||
|
||||
constant PWR_UP_WAIT : natural := 220; -- µs
|
||||
|
||||
subtype user_tag_t is unsigned(3 downto 0);
|
||||
|
||||
----------------------------------------------------------------------------------------------
|
||||
|
||||
end sdram_config;
|
||||
@@ -0,0 +1,575 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE sdram_test OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 513) of inst_t;
|
||||
|
||||
-- Assembled from sdram_test.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"007", -- 0x000: JMP 0x007
|
||||
"111100" & X"000", -- 0x001: PUSH R00
|
||||
"101000" & X"040", -- 0x002: XIN R00, (0x04)
|
||||
"011011" & X"100", -- 0x003: OR R00, 0x10
|
||||
"100100" & X"040", -- 0x004: XOUT (0x04), R00
|
||||
"111101" & X"000", -- 0x005: POP R00
|
||||
"111111" & X"000", -- 0x006: RETI
|
||||
"111011" & X"128", -- 0x007: CALL 0x128
|
||||
"000011" & X"000", -- 0x008: MOV R00, 0x00
|
||||
"100100" & X"010", -- 0x009: XOUT (0x01), R00
|
||||
"000011" & X"040", -- 0x00A: MOV R00, 0x04
|
||||
"100100" & X"040", -- 0x00B: XOUT (0x04), R00
|
||||
"101001" & X"030", -- 0x00C: CIN R00, (0x03)
|
||||
"011011" & X"050", -- 0x00D: OR R00, 0x05
|
||||
"100110" & X"030", -- 0x00E: COUT (0x03), R00
|
||||
"000011" & X"010", -- 0x00F: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x010: CALL 0x145
|
||||
"000011" & X"000", -- 0x011: MOV R00, 0x00
|
||||
"000011" & X"C01", -- 0x012: MOV R01, 0xC0
|
||||
"100100" & X"101", -- 0x013: XOUT (0x10), R01
|
||||
"100100" & X"111", -- 0x014: XOUT (0x11), R01
|
||||
"100100" & X"121", -- 0x015: XOUT (0x12), R01
|
||||
"111011" & X"1B9", -- 0x016: CALL 0x1B9
|
||||
"111011" & X"19E", -- 0x017: CALL 0x19E
|
||||
"000011" & X"031", -- 0x018: MOV R01, 0x03
|
||||
"111011" & X"14A", -- 0x019: CALL 0x14A
|
||||
"000011" & X"031", -- 0x01A: MOV R01, 0x03
|
||||
"111011" & X"1AA", -- 0x01B: CALL 0x1AA
|
||||
"000011" & X"001", -- 0x01C: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x01D: CALL 0x1B6
|
||||
"101000" & X"040", -- 0x01E: XIN R00, (0x04)
|
||||
"011011" & X"100", -- 0x01F: OR R00, 0x10
|
||||
"100100" & X"040", -- 0x020: XOUT (0x04), R00
|
||||
"111011" & X"1C6", -- 0x021: CALL 0x1C6
|
||||
"011011" & X"200", -- 0x022: OR R00, 0x20
|
||||
"100100" & X"040", -- 0x023: XOUT (0x04), R00
|
||||
"111011" & X"1C6", -- 0x024: CALL 0x1C6
|
||||
"011001" & X"EF0", -- 0x025: AND R00, 0xEF
|
||||
"100100" & X"040", -- 0x026: XOUT (0x04), R00
|
||||
"111011" & X"1C6", -- 0x027: CALL 0x1C6
|
||||
"011001" & X"CF0", -- 0x028: AND R00, 0xCF
|
||||
"100100" & X"040", -- 0x029: XOUT (0x04), R00
|
||||
"000011" & X"010", -- 0x02A: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x02B: CALL 0x145
|
||||
"000011" & X"0E1", -- 0x02C: MOV R01, 0x0E
|
||||
"111011" & X"14A", -- 0x02D: CALL 0x14A
|
||||
"000011" & X"0E1", -- 0x02E: MOV R01, 0x0E
|
||||
"111011" & X"1B3", -- 0x02F: CALL 0x1B3
|
||||
"000011" & X"001", -- 0x030: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x031: CALL 0x1B6
|
||||
"111011" & X"0CC", -- 0x032: CALL 0x0CC
|
||||
"000011" & X"800", -- 0x033: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x034: MOV R15, 0x08
|
||||
"000111" & X"000", -- 0x035: MOVX (R00), 0x00
|
||||
"010001" & X"010", -- 0x036: INC R00
|
||||
"010101" & X"01F", -- 0x037: DEC R15
|
||||
"110010" & X"035", -- 0x038: JNZ 0x035
|
||||
"101000" & X"0A0", -- 0x039: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x03A: CMP R00, 0xFF
|
||||
"111001" & X"04B", -- 0x03B: JEQ 0x04B
|
||||
"000011" & X"082", -- 0x03C: MOV R02, 0x08
|
||||
"101000" & X"070", -- 0x03D: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x03E: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x03F: AND R00, 0x04
|
||||
"110010" & X"03D", -- 0x040: JNZ 0x03D
|
||||
"000011" & X"100", -- 0x041: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x042: XOUT (0x07), R00
|
||||
"010101" & X"022", -- 0x043: SUB R02, 0x02
|
||||
"110010" & X"03D", -- 0x044: JNZ 0x03D
|
||||
"111011" & X"0AB", -- 0x045: CALL 0x0AB
|
||||
"000011" & X"060", -- 0x046: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x047: XOUT (0x07), R00
|
||||
"000011" & X"080", -- 0x048: MOV R00, 0x08
|
||||
"111011" & X"0D3", -- 0x049: CALL 0x0D3
|
||||
"110000" & X"039", -- 0x04A: JMP 0x039
|
||||
"111011" & X"0E3", -- 0x04B: CALL 0x0E3
|
||||
"111011" & X"1BF", -- 0x04C: CALL 0x1BF
|
||||
"110000" & X"04E", -- 0x04D: JMP 0x04E
|
||||
"000011" & X"010", -- 0x04E: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x04F: CALL 0x145
|
||||
"000011" & X"1D1", -- 0x050: MOV R01, 0x1D
|
||||
"111011" & X"14A", -- 0x051: CALL 0x14A
|
||||
"000011" & X"1D1", -- 0x052: MOV R01, 0x1D
|
||||
"111011" & X"1B3", -- 0x053: CALL 0x1B3
|
||||
"000011" & X"001", -- 0x054: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x055: CALL 0x1B6
|
||||
"111011" & X"0CC", -- 0x056: CALL 0x0CC
|
||||
"000011" & X"000", -- 0x057: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x058: MOVC (0x00), R00
|
||||
"101000" & X"0A0", -- 0x059: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x05A: CMP R00, 0xFF
|
||||
"111001" & X"076", -- 0x05B: JEQ 0x076
|
||||
"000011" & X"082", -- 0x05C: MOV R02, 0x08
|
||||
"001010" & X"001", -- 0x05D: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x05E: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x05F: MOV R15, 0x08
|
||||
"000110" & X"001", -- 0x060: MOVX (R01), R00
|
||||
"010001" & X"010", -- 0x061: INC R00
|
||||
"010001" & X"011", -- 0x062: INC R01
|
||||
"010101" & X"01F", -- 0x063: DEC R15
|
||||
"110010" & X"060", -- 0x064: JNZ 0x060
|
||||
"101000" & X"070", -- 0x065: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x066: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x067: AND R00, 0x04
|
||||
"110010" & X"065", -- 0x068: JNZ 0x065
|
||||
"000011" & X"100", -- 0x069: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x06A: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x06B: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x06C: INC R00
|
||||
"001101" & X"000", -- 0x06D: MOVC (0x00), R00
|
||||
"010101" & X"022", -- 0x06E: SUB R02, 0x02
|
||||
"110010" & X"05D", -- 0x06F: JNZ 0x05D
|
||||
"111011" & X"0AB", -- 0x070: CALL 0x0AB
|
||||
"000011" & X"060", -- 0x071: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x072: XOUT (0x07), R00
|
||||
"000011" & X"080", -- 0x073: MOV R00, 0x08
|
||||
"111011" & X"0D3", -- 0x074: CALL 0x0D3
|
||||
"110000" & X"059", -- 0x075: JMP 0x059
|
||||
"111011" & X"0E3", -- 0x076: CALL 0x0E3
|
||||
"111011" & X"1BF", -- 0x077: CALL 0x1BF
|
||||
"000011" & X"010", -- 0x078: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x079: CALL 0x145
|
||||
"000011" & X"2B1", -- 0x07A: MOV R01, 0x2B
|
||||
"111011" & X"14A", -- 0x07B: CALL 0x14A
|
||||
"000011" & X"2B1", -- 0x07C: MOV R01, 0x2B
|
||||
"111011" & X"1B3", -- 0x07D: CALL 0x1B3
|
||||
"000011" & X"001", -- 0x07E: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x07F: CALL 0x1B6
|
||||
"111011" & X"0CC", -- 0x080: CALL 0x0CC
|
||||
"000011" & X"000", -- 0x081: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x082: MOVC (0x00), R00
|
||||
"101000" & X"0A0", -- 0x083: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x084: CMP R00, 0xFF
|
||||
"111001" & X"0B3", -- 0x085: JEQ 0x0B3
|
||||
"111011" & X"0AB", -- 0x086: CALL 0x0AB
|
||||
"000011" & X"050", -- 0x087: MOV R00, 0x05
|
||||
"100100" & X"070", -- 0x088: XOUT (0x07), R00
|
||||
"000011" & X"083", -- 0x089: MOV R03, 0x08
|
||||
"101000" & X"070", -- 0x08A: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x08B: XOUT (0x01), R00
|
||||
"011001" & X"200", -- 0x08C: AND R00, 0x20
|
||||
"110010" & X"08A", -- 0x08D: JNZ 0x08A
|
||||
"001010" & X"001", -- 0x08E: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x08F: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x090: MOV R15, 0x08
|
||||
"000100" & X"002", -- 0x091: MOVX R02, (R00)
|
||||
"001110" & X"012", -- 0x092: CMP R02, R01
|
||||
"111010" & X"0BF", -- 0x093: JNE 0x0BF
|
||||
"010001" & X"010", -- 0x094: INC R00
|
||||
"010001" & X"011", -- 0x095: INC R01
|
||||
"010101" & X"01F", -- 0x096: DEC R15
|
||||
"110010" & X"091", -- 0x097: JNZ 0x091
|
||||
"000011" & X"200", -- 0x098: MOV R00, 0x20
|
||||
"100100" & X"070", -- 0x099: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x09A: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x09B: INC R00
|
||||
"001101" & X"000", -- 0x09C: MOVC (0x00), R00
|
||||
"010101" & X"023", -- 0x09D: SUB R03, 0x02
|
||||
"110010" & X"08A", -- 0x09E: JNZ 0x08A
|
||||
"000011" & X"080", -- 0x09F: MOV R00, 0x08
|
||||
"111011" & X"0D3", -- 0x0A0: CALL 0x0D3
|
||||
"110000" & X"083", -- 0x0A1: JMP 0x083
|
||||
"111100" & X"000", -- 0x0A2: PUSH R00
|
||||
"000011" & X"800", -- 0x0A3: MOV R00, 0x80
|
||||
"100100" & X"070", -- 0x0A4: XOUT (0x07), R00
|
||||
"101000" & X"070", -- 0x0A5: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x0A6: XOUT (0x01), R00
|
||||
"011001" & X"800", -- 0x0A7: AND R00, 0x80
|
||||
"110001" & X"0A5", -- 0x0A8: JZ 0x0A5
|
||||
"111101" & X"000", -- 0x0A9: POP R00
|
||||
"111110" & X"000", -- 0x0AA: RET
|
||||
"111011" & X"0A2", -- 0x0AB: CALL 0x0A2
|
||||
"111100" & X"000", -- 0x0AC: PUSH R00
|
||||
"101000" & X"070", -- 0x0AD: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x0AE: XOUT (0x01), R00
|
||||
"011001" & X"010", -- 0x0AF: AND R00, 0x01
|
||||
"110010" & X"0AD", -- 0x0B0: JNZ 0x0AD
|
||||
"111101" & X"000", -- 0x0B1: POP R00
|
||||
"111110" & X"000", -- 0x0B2: RET
|
||||
"000011" & X"010", -- 0x0B3: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x0B4: CALL 0x145
|
||||
"000011" & X"391", -- 0x0B5: MOV R01, 0x39
|
||||
"111011" & X"14A", -- 0x0B6: CALL 0x14A
|
||||
"000011" & X"C00", -- 0x0B7: MOV R00, 0xC0
|
||||
"111011" & X"145", -- 0x0B8: CALL 0x145
|
||||
"111011" & X"0EE", -- 0x0B9: CALL 0x0EE
|
||||
"000011" & X"391", -- 0x0BA: MOV R01, 0x39
|
||||
"111011" & X"1B3", -- 0x0BB: CALL 0x1B3
|
||||
"000011" & X"001", -- 0x0BC: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x0BD: CALL 0x1B6
|
||||
"110000" & X"0CA", -- 0x0BE: JMP 0x0CA
|
||||
"000011" & X"010", -- 0x0BF: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x0C0: CALL 0x145
|
||||
"000011" & X"431", -- 0x0C1: MOV R01, 0x43
|
||||
"111011" & X"14A", -- 0x0C2: CALL 0x14A
|
||||
"111011" & X"0EE", -- 0x0C3: CALL 0x0EE
|
||||
"111011" & X"106", -- 0x0C4: CALL 0x106
|
||||
"000011" & X"431", -- 0x0C5: MOV R01, 0x43
|
||||
"111011" & X"1B3", -- 0x0C6: CALL 0x1B3
|
||||
"000011" & X"001", -- 0x0C7: MOV R01, 0x00
|
||||
"111011" & X"1B6", -- 0x0C8: CALL 0x1B6
|
||||
"110000" & X"0CA", -- 0x0C9: JMP 0x0CA
|
||||
"111011" & X"1BF", -- 0x0CA: CALL 0x1BF
|
||||
"110000" & X"02A", -- 0x0CB: JMP 0x02A
|
||||
"111100" & X"000", -- 0x0CC: PUSH R00
|
||||
"000011" & X"000", -- 0x0CD: MOV R00, 0x00
|
||||
"100100" & X"080", -- 0x0CE: XOUT (0x08), R00
|
||||
"100100" & X"090", -- 0x0CF: XOUT (0x09), R00
|
||||
"100100" & X"0A0", -- 0x0D0: XOUT (0x0A), R00
|
||||
"111101" & X"000", -- 0x0D1: POP R00
|
||||
"111110" & X"000", -- 0x0D2: RET
|
||||
"111100" & X"001", -- 0x0D3: PUSH R01
|
||||
"111100" & X"002", -- 0x0D4: PUSH R02
|
||||
"111100" & X"003", -- 0x0D5: PUSH R03
|
||||
"101000" & X"081", -- 0x0D6: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x0D7: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x0D8: XIN R03, (0x0A)
|
||||
"010000" & X"001", -- 0x0D9: ADD R01, R00
|
||||
"010011" & X"002", -- 0x0DA: ADDC R02, 0x00
|
||||
"010011" & X"003", -- 0x0DB: ADDC R03, 0x00
|
||||
"100100" & X"081", -- 0x0DC: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x0DD: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x0DE: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x0DF: POP R03
|
||||
"111101" & X"002", -- 0x0E0: POP R02
|
||||
"111101" & X"001", -- 0x0E1: POP R01
|
||||
"111110" & X"000", -- 0x0E2: RET
|
||||
"000011" & X"C00", -- 0x0E3: MOV R00, 0xC0
|
||||
"111011" & X"145", -- 0x0E4: CALL 0x145
|
||||
"111011" & X"0EE", -- 0x0E5: CALL 0x0EE
|
||||
"111110" & X"000", -- 0x0E6: RET
|
||||
"111100" & X"001", -- 0x0E7: PUSH R01
|
||||
"111011" & X"121", -- 0x0E8: CALL 0x121
|
||||
"111011" & X"15C", -- 0x0E9: CALL 0x15C
|
||||
"000010" & X"010", -- 0x0EA: MOV R00, R01
|
||||
"111011" & X"15C", -- 0x0EB: CALL 0x15C
|
||||
"111101" & X"001", -- 0x0EC: POP R01
|
||||
"111110" & X"000", -- 0x0ED: RET
|
||||
"111100" & X"000", -- 0x0EE: PUSH R00
|
||||
"101000" & X"0A0", -- 0x0EF: XIN R00, (0x0A)
|
||||
"111011" & X"0E7", -- 0x0F0: CALL 0x0E7
|
||||
"101000" & X"090", -- 0x0F1: XIN R00, (0x09)
|
||||
"111011" & X"0E7", -- 0x0F2: CALL 0x0E7
|
||||
"101000" & X"080", -- 0x0F3: XIN R00, (0x08)
|
||||
"111011" & X"0E7", -- 0x0F4: CALL 0x0E7
|
||||
"111101" & X"000", -- 0x0F5: POP R00
|
||||
"111110" & X"000", -- 0x0F6: RET
|
||||
"111100" & X"000", -- 0x0F7: PUSH R00
|
||||
"010001" & X"031", -- 0x0F8: ADD R01, 0x03
|
||||
"001001" & X"010", -- 0x0F9: MOVC R00, (R01)
|
||||
"111011" & X"0E7", -- 0x0FA: CALL 0x0E7
|
||||
"010101" & X"011", -- 0x0FB: DEC R01
|
||||
"001001" & X"010", -- 0x0FC: MOVC R00, (R01)
|
||||
"111011" & X"0E7", -- 0x0FD: CALL 0x0E7
|
||||
"010101" & X"011", -- 0x0FE: DEC R01
|
||||
"001001" & X"010", -- 0x0FF: MOVC R00, (R01)
|
||||
"111011" & X"0E7", -- 0x100: CALL 0x0E7
|
||||
"010101" & X"011", -- 0x101: DEC R01
|
||||
"001001" & X"010", -- 0x102: MOVC R00, (R01)
|
||||
"111011" & X"0E7", -- 0x103: CALL 0x0E7
|
||||
"111101" & X"000", -- 0x104: POP R00
|
||||
"111110" & X"000", -- 0x105: RET
|
||||
"111100" & X"000", -- 0x106: PUSH R00
|
||||
"000011" & X"C00", -- 0x107: MOV R00, 0xC0
|
||||
"111011" & X"145", -- 0x108: CALL 0x145
|
||||
"000101" & X"870", -- 0x109: MOVX R00, (0x87)
|
||||
"111011" & X"0E7", -- 0x10A: CALL 0x0E7
|
||||
"000101" & X"860", -- 0x10B: MOVX R00, (0x86)
|
||||
"111011" & X"0E7", -- 0x10C: CALL 0x0E7
|
||||
"000101" & X"850", -- 0x10D: MOVX R00, (0x85)
|
||||
"111011" & X"0E7", -- 0x10E: CALL 0x0E7
|
||||
"000101" & X"840", -- 0x10F: MOVX R00, (0x84)
|
||||
"111011" & X"0E7", -- 0x110: CALL 0x0E7
|
||||
"000101" & X"830", -- 0x111: MOVX R00, (0x83)
|
||||
"111011" & X"0E7", -- 0x112: CALL 0x0E7
|
||||
"000101" & X"820", -- 0x113: MOVX R00, (0x82)
|
||||
"111011" & X"0E7", -- 0x114: CALL 0x0E7
|
||||
"000101" & X"810", -- 0x115: MOVX R00, (0x81)
|
||||
"111011" & X"0E7", -- 0x116: CALL 0x0E7
|
||||
"000101" & X"800", -- 0x117: MOVX R00, (0x80)
|
||||
"111011" & X"0E7", -- 0x118: CALL 0x0E7
|
||||
"111101" & X"000", -- 0x119: POP R00
|
||||
"111110" & X"000", -- 0x11A: RET
|
||||
"011001" & X"0F0", -- 0x11B: AND R00, 0x0F
|
||||
"001111" & X"0A0", -- 0x11C: CMP R00, 0x0A
|
||||
"110101" & X"11F", -- 0x11D: JLT 0x11F
|
||||
"010001" & X"070", -- 0x11E: ADD R00, 0x07
|
||||
"010001" & X"300", -- 0x11F: ADD R00, 0x30
|
||||
"111110" & X"000", -- 0x120: RET
|
||||
"111100" & X"000", -- 0x121: PUSH R00
|
||||
"111011" & X"11B", -- 0x122: CALL 0x11B
|
||||
"000010" & X"001", -- 0x123: MOV R01, R00
|
||||
"111101" & X"000", -- 0x124: POP R00
|
||||
"101010" & X"000", -- 0x125: SWAP R00
|
||||
"111011" & X"11B", -- 0x126: CALL 0x11B
|
||||
"111110" & X"000", -- 0x127: RET
|
||||
"000011" & X"002", -- 0x128: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x129: MOV R00, 0x03
|
||||
"111011" & X"174", -- 0x12A: CALL 0x174
|
||||
"111011" & X"1CD", -- 0x12B: CALL 0x1CD
|
||||
"000011" & X"002", -- 0x12C: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x12D: MOV R00, 0x03
|
||||
"111011" & X"174", -- 0x12E: CALL 0x174
|
||||
"111011" & X"1CD", -- 0x12F: CALL 0x1CD
|
||||
"000011" & X"002", -- 0x130: MOV R02, 0x00
|
||||
"000011" & X"020", -- 0x131: MOV R00, 0x02
|
||||
"111011" & X"174", -- 0x132: CALL 0x174
|
||||
"111011" & X"1D4", -- 0x133: CALL 0x1D4
|
||||
"000011" & X"280", -- 0x134: MOV R00, 0x28
|
||||
"111011" & X"145", -- 0x135: CALL 0x145
|
||||
"000011" & X"0C0", -- 0x136: MOV R00, 0x0C
|
||||
"111011" & X"145", -- 0x137: CALL 0x145
|
||||
"000011" & X"060", -- 0x138: MOV R00, 0x06
|
||||
"111011" & X"145", -- 0x139: CALL 0x145
|
||||
"000011" & X"010", -- 0x13A: MOV R00, 0x01
|
||||
"111011" & X"145", -- 0x13B: CALL 0x145
|
||||
"111110" & X"000", -- 0x13C: RET
|
||||
"111100" & X"000", -- 0x13D: PUSH R00
|
||||
"111011" & X"168", -- 0x13E: CALL 0x168
|
||||
"011001" & X"800", -- 0x13F: AND R00, 0x80
|
||||
"110001" & X"143", -- 0x140: JZ 0x143
|
||||
"111011" & X"1EB", -- 0x141: CALL 0x1EB
|
||||
"110000" & X"13E", -- 0x142: JMP 0x13E
|
||||
"111101" & X"000", -- 0x143: POP R00
|
||||
"111110" & X"000", -- 0x144: RET
|
||||
"111100" & X"002", -- 0x145: PUSH R02
|
||||
"000011" & X"002", -- 0x146: MOV R02, 0x00
|
||||
"111011" & X"161", -- 0x147: CALL 0x161
|
||||
"111101" & X"002", -- 0x148: POP R02
|
||||
"111110" & X"000", -- 0x149: RET
|
||||
"111100" & X"000", -- 0x14A: PUSH R00
|
||||
"000100" & X"010", -- 0x14B: MOVX R00, (R01)
|
||||
"010001" & X"011", -- 0x14C: INC R01
|
||||
"001111" & X"000", -- 0x14D: TST R00
|
||||
"110001" & X"151", -- 0x14E: JZ 0x151
|
||||
"111011" & X"15C", -- 0x14F: CALL 0x15C
|
||||
"110000" & X"14B", -- 0x150: JMP 0x14B
|
||||
"111101" & X"000", -- 0x151: POP R00
|
||||
"111110" & X"000", -- 0x152: RET
|
||||
"111100" & X"000", -- 0x153: PUSH R00
|
||||
"001001" & X"010", -- 0x154: MOVC R00, (R01)
|
||||
"010001" & X"011", -- 0x155: INC R01
|
||||
"001111" & X"000", -- 0x156: TST R00
|
||||
"110001" & X"15A", -- 0x157: JZ 0x15A
|
||||
"111011" & X"15C", -- 0x158: CALL 0x15C
|
||||
"110000" & X"154", -- 0x159: JMP 0x154
|
||||
"111101" & X"000", -- 0x15A: POP R00
|
||||
"111110" & X"000", -- 0x15B: RET
|
||||
"111100" & X"002", -- 0x15C: PUSH R02
|
||||
"000011" & X"402", -- 0x15D: MOV R02, 0x40
|
||||
"111011" & X"161", -- 0x15E: CALL 0x161
|
||||
"111101" & X"002", -- 0x15F: POP R02
|
||||
"111110" & X"000", -- 0x160: RET
|
||||
"111011" & X"13D", -- 0x161: CALL 0x13D
|
||||
"111100" & X"000", -- 0x162: PUSH R00
|
||||
"101010" & X"000", -- 0x163: SWAP R00
|
||||
"111011" & X"174", -- 0x164: CALL 0x174
|
||||
"111101" & X"000", -- 0x165: POP R00
|
||||
"111011" & X"174", -- 0x166: CALL 0x174
|
||||
"111110" & X"000", -- 0x167: RET
|
||||
"111100" & X"002", -- 0x168: PUSH R02
|
||||
"000011" & X"002", -- 0x169: MOV R02, 0x00
|
||||
"111011" & X"16D", -- 0x16A: CALL 0x16D
|
||||
"111101" & X"002", -- 0x16B: POP R02
|
||||
"111110" & X"000", -- 0x16C: RET
|
||||
"111011" & X"187", -- 0x16D: CALL 0x187
|
||||
"101010" & X"000", -- 0x16E: SWAP R00
|
||||
"111100" & X"000", -- 0x16F: PUSH R00
|
||||
"111011" & X"187", -- 0x170: CALL 0x187
|
||||
"111101" & X"002", -- 0x171: POP R02
|
||||
"011010" & X"020", -- 0x172: OR R00, R02
|
||||
"111110" & X"000", -- 0x173: RET
|
||||
"111100" & X"001", -- 0x174: PUSH R01
|
||||
"011001" & X"0F0", -- 0x175: AND R00, 0x0F
|
||||
"000010" & X"001", -- 0x176: MOV R01, R00
|
||||
"011010" & X"021", -- 0x177: OR R01, R02
|
||||
"100100" & X"031", -- 0x178: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x179: CALL 0x1EB
|
||||
"000010" & X"001", -- 0x17A: MOV R01, R00
|
||||
"011010" & X"021", -- 0x17B: OR R01, R02
|
||||
"011011" & X"801", -- 0x17C: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x17D: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x17E: CALL 0x1EB
|
||||
"000010" & X"001", -- 0x17F: MOV R01, R00
|
||||
"011010" & X"021", -- 0x180: OR R01, R02
|
||||
"100100" & X"031", -- 0x181: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x182: CALL 0x1EB
|
||||
"011011" & X"201", -- 0x183: OR R01, 0x20
|
||||
"100100" & X"031", -- 0x184: XOUT (0x03), R01
|
||||
"111101" & X"001", -- 0x185: POP R01
|
||||
"111110" & X"000", -- 0x186: RET
|
||||
"111100" & X"001", -- 0x187: PUSH R01
|
||||
"000011" & X"201", -- 0x188: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x189: OR R01, R02
|
||||
"100100" & X"031", -- 0x18A: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x18B: CALL 0x1EB
|
||||
"000011" & X"201", -- 0x18C: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x18D: OR R01, R02
|
||||
"011011" & X"801", -- 0x18E: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x18F: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x190: CALL 0x1EB
|
||||
"101000" & X"030", -- 0x191: XIN R00, (0x03)
|
||||
"011001" & X"0F0", -- 0x192: AND R00, 0x0F
|
||||
"000011" & X"201", -- 0x193: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x194: OR R01, R02
|
||||
"100100" & X"031", -- 0x195: XOUT (0x03), R01
|
||||
"111011" & X"1EB", -- 0x196: CALL 0x1EB
|
||||
"111101" & X"001", -- 0x197: POP R01
|
||||
"111110" & X"000", -- 0x198: RET
|
||||
"111100" & X"000", -- 0x199: PUSH R00
|
||||
"000011" & X"020", -- 0x19A: MOV R00, 0x02
|
||||
"100100" & X"0E0", -- 0x19B: XOUT (0x0E), R00
|
||||
"111101" & X"000", -- 0x19C: POP R00
|
||||
"111110" & X"000", -- 0x19D: RET
|
||||
"111100" & X"000", -- 0x19E: PUSH R00
|
||||
"000011" & X"010", -- 0x19F: MOV R00, 0x01
|
||||
"100100" & X"0E0", -- 0x1A0: XOUT (0x0E), R00
|
||||
"111101" & X"000", -- 0x1A1: POP R00
|
||||
"111110" & X"000", -- 0x1A2: RET
|
||||
"111011" & X"1B9", -- 0x1A3: CALL 0x1B9
|
||||
"100100" & X"0C1", -- 0x1A4: XOUT (0x0C), R01
|
||||
"100100" & X"0B0", -- 0x1A5: XOUT (0x0B), R00
|
||||
"111110" & X"000", -- 0x1A6: RET
|
||||
"111011" & X"1B9", -- 0x1A7: CALL 0x1B9
|
||||
"100100" & X"0D0", -- 0x1A8: XOUT (0x0D), R00
|
||||
"111110" & X"000", -- 0x1A9: RET
|
||||
"111100" & X"000", -- 0x1AA: PUSH R00
|
||||
"000100" & X"010", -- 0x1AB: MOVX R00, (R01)
|
||||
"010001" & X"011", -- 0x1AC: INC R01
|
||||
"001111" & X"000", -- 0x1AD: TST R00
|
||||
"110001" & X"1B1", -- 0x1AE: JZ 0x1B1
|
||||
"111011" & X"1A7", -- 0x1AF: CALL 0x1A7
|
||||
"110000" & X"1AB", -- 0x1B0: JMP 0x1AB
|
||||
"111101" & X"000", -- 0x1B1: POP R00
|
||||
"111110" & X"000", -- 0x1B2: RET
|
||||
"111011" & X"199", -- 0x1B3: CALL 0x199
|
||||
"111011" & X"1AA", -- 0x1B4: CALL 0x1AA
|
||||
"111110" & X"000", -- 0x1B5: RET
|
||||
"111011" & X"1AA", -- 0x1B6: CALL 0x1AA
|
||||
"111011" & X"199", -- 0x1B7: CALL 0x199
|
||||
"111110" & X"000", -- 0x1B8: RET
|
||||
"111100" & X"000", -- 0x1B9: PUSH R00
|
||||
"101000" & X"0E0", -- 0x1BA: XIN R00, (0x0E)
|
||||
"011001" & X"020", -- 0x1BB: AND R00, 0x02
|
||||
"110001" & X"1BA", -- 0x1BC: JZ 0x1BA
|
||||
"111101" & X"000", -- 0x1BD: POP R00
|
||||
"111110" & X"000", -- 0x1BE: RET
|
||||
"111100" & X"00F", -- 0x1BF: PUSH R15
|
||||
"000011" & X"0AF", -- 0x1C0: MOV R15, 0x0A
|
||||
"111011" & X"1C6", -- 0x1C1: CALL 0x1C6
|
||||
"010101" & X"01F", -- 0x1C2: DEC R15
|
||||
"110010" & X"1C1", -- 0x1C3: JNZ 0x1C1
|
||||
"111101" & X"00F", -- 0x1C4: POP R15
|
||||
"111110" & X"000", -- 0x1C5: RET
|
||||
"111100" & X"00F", -- 0x1C6: PUSH R15
|
||||
"000011" & X"0AF", -- 0x1C7: MOV R15, 0x0A
|
||||
"111011" & X"1CD", -- 0x1C8: CALL 0x1CD
|
||||
"010101" & X"01F", -- 0x1C9: DEC R15
|
||||
"110010" & X"1C8", -- 0x1CA: JNZ 0x1C8
|
||||
"111101" & X"00F", -- 0x1CB: POP R15
|
||||
"111110" & X"000", -- 0x1CC: RET
|
||||
"111100" & X"00F", -- 0x1CD: PUSH R15
|
||||
"000011" & X"0AF", -- 0x1CE: MOV R15, 0x0A
|
||||
"111011" & X"1D4", -- 0x1CF: CALL 0x1D4
|
||||
"010101" & X"01F", -- 0x1D0: DEC R15
|
||||
"110010" & X"1CF", -- 0x1D1: JNZ 0x1CF
|
||||
"111101" & X"00F", -- 0x1D2: POP R15
|
||||
"111110" & X"000", -- 0x1D3: RET
|
||||
"111100" & X"00F", -- 0x1D4: PUSH R15
|
||||
"000011" & X"0AF", -- 0x1D5: MOV R15, 0x0A
|
||||
"111011" & X"1DB", -- 0x1D6: CALL 0x1DB
|
||||
"010101" & X"01F", -- 0x1D7: DEC R15
|
||||
"110010" & X"1D6", -- 0x1D8: JNZ 0x1D6
|
||||
"111101" & X"00F", -- 0x1D9: POP R15
|
||||
"111110" & X"000", -- 0x1DA: RET
|
||||
"111100" & X"00F", -- 0x1DB: PUSH R15
|
||||
"000011" & X"0AF", -- 0x1DC: MOV R15, 0x0A
|
||||
"111011" & X"1E2", -- 0x1DD: CALL 0x1E2
|
||||
"010101" & X"01F", -- 0x1DE: DEC R15
|
||||
"110010" & X"1DD", -- 0x1DF: JNZ 0x1DD
|
||||
"111101" & X"00F", -- 0x1E0: POP R15
|
||||
"111110" & X"000", -- 0x1E1: RET
|
||||
"111100" & X"00F", -- 0x1E2: PUSH R15
|
||||
"000011" & X"63F", -- 0x1E3: MOV R15, 0x63
|
||||
"000000" & X"000", -- 0x1E4: NOP
|
||||
"000000" & X"000", -- 0x1E5: NOP
|
||||
"000000" & X"000", -- 0x1E6: NOP
|
||||
"010101" & X"01F", -- 0x1E7: DEC R15
|
||||
"110010" & X"1E4", -- 0x1E8: JNZ 0x1E4
|
||||
"111101" & X"00F", -- 0x1E9: POP R15
|
||||
"111110" & X"000", -- 0x1EA: RET
|
||||
"111100" & X"00F", -- 0x1EB: PUSH R15
|
||||
"000011" & X"09F", -- 0x1EC: MOV R15, 0x09
|
||||
"000000" & X"000", -- 0x1ED: NOP
|
||||
"000000" & X"000", -- 0x1EE: NOP
|
||||
"000000" & X"000", -- 0x1EF: NOP
|
||||
"010101" & X"01F", -- 0x1F0: DEC R15
|
||||
"110010" & X"1ED", -- 0x1F1: JNZ 0x1ED
|
||||
"111101" & X"00F", -- 0x1F2: POP R15
|
||||
"111110" & X"000", -- 0x1F3: RET
|
||||
"111100" & X"001", -- 0x1F4: PUSH R01
|
||||
"101000" & X"061", -- 0x1F5: XIN R01, (0x06)
|
||||
"011001" & X"021", -- 0x1F6: AND R01, 0x02
|
||||
"110010" & X"1F5", -- 0x1F7: JNZ 0x1F5
|
||||
"100100" & X"020", -- 0x1F8: XOUT (0x02), R00
|
||||
"111101" & X"001", -- 0x1F9: POP R01
|
||||
"111110" & X"000", -- 0x1FA: RET
|
||||
"111100" & X"001", -- 0x1FB: PUSH R01
|
||||
"101000" & X"061", -- 0x1FC: XIN R01, (0x06)
|
||||
"011001" & X"101", -- 0x1FD: AND R01, 0x10
|
||||
"110001" & X"1FC", -- 0x1FE: JZ 0x1FC
|
||||
"101000" & X"020", -- 0x1FF: XIN R00, (0x02)
|
||||
"111101" & X"001", -- 0x200: POP R01
|
||||
"111110" & X"000" -- 0x201: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdram_test;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,226 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE sdram_test_short OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 164) of inst_t;
|
||||
|
||||
-- Assembled from sdram_test_short.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"002", -- 0x000: JMP 0x002
|
||||
"111111" & X"000", -- 0x001: RETI
|
||||
"000011" & X"000", -- 0x002: MOV R00, 0x00
|
||||
"100100" & X"010", -- 0x003: XOUT (0x01), R00
|
||||
"000011" & X"040", -- 0x004: MOV R00, 0x04
|
||||
"100100" & X"040", -- 0x005: XOUT (0x04), R00
|
||||
"000011" & X"000", -- 0x006: MOV R00, 0x00
|
||||
"000011" & X"801", -- 0x007: MOV R01, 0x80
|
||||
"100100" & X"100", -- 0x008: XOUT (0x10), R00
|
||||
"100100" & X"111", -- 0x009: XOUT (0x11), R01
|
||||
"100100" & X"120", -- 0x00A: XOUT (0x12), R00
|
||||
"110000" & X"026", -- 0x00B: JMP 0x026
|
||||
"111011" & X"07D", -- 0x00C: CALL 0x07D
|
||||
"000011" & X"800", -- 0x00D: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x00E: MOV R15, 0x08
|
||||
"000111" & X"000", -- 0x00F: MOVX (R00), 0x00
|
||||
"010001" & X"010", -- 0x010: INC R00
|
||||
"010101" & X"01F", -- 0x011: DEC R15
|
||||
"110010" & X"00F", -- 0x012: JNZ 0x00F
|
||||
"101000" & X"080", -- 0x013: XIN R00, (0x08)
|
||||
"001111" & X"400", -- 0x014: CMP R00, 0x40
|
||||
"111001" & X"025", -- 0x015: JEQ 0x025
|
||||
"000011" & X"082", -- 0x016: MOV R02, 0x08
|
||||
"101000" & X"070", -- 0x017: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x018: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x019: AND R00, 0x04
|
||||
"110010" & X"017", -- 0x01A: JNZ 0x017
|
||||
"000011" & X"100", -- 0x01B: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x01C: XOUT (0x07), R00
|
||||
"010101" & X"022", -- 0x01D: SUB R02, 0x02
|
||||
"110010" & X"017", -- 0x01E: JNZ 0x017
|
||||
"111011" & X"072", -- 0x01F: CALL 0x072
|
||||
"000011" & X"060", -- 0x020: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x021: XOUT (0x07), R00
|
||||
"000011" & X"080", -- 0x022: MOV R00, 0x08
|
||||
"111011" & X"084", -- 0x023: CALL 0x084
|
||||
"110000" & X"013", -- 0x024: JMP 0x013
|
||||
"111011" & X"094", -- 0x025: CALL 0x094
|
||||
"111011" & X"07D", -- 0x026: CALL 0x07D
|
||||
"000011" & X"000", -- 0x027: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x028: MOVC (0x00), R00
|
||||
"101000" & X"080", -- 0x029: XIN R00, (0x08)
|
||||
"001111" & X"400", -- 0x02A: CMP R00, 0x40
|
||||
"111001" & X"046", -- 0x02B: JEQ 0x046
|
||||
"000011" & X"082", -- 0x02C: MOV R02, 0x08
|
||||
"001010" & X"001", -- 0x02D: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x02E: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x02F: MOV R15, 0x08
|
||||
"000110" & X"001", -- 0x030: MOVX (R01), R00
|
||||
"010001" & X"010", -- 0x031: INC R00
|
||||
"010001" & X"011", -- 0x032: INC R01
|
||||
"010101" & X"01F", -- 0x033: DEC R15
|
||||
"110010" & X"030", -- 0x034: JNZ 0x030
|
||||
"101000" & X"070", -- 0x035: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x036: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x037: AND R00, 0x04
|
||||
"110010" & X"035", -- 0x038: JNZ 0x035
|
||||
"000011" & X"100", -- 0x039: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x03A: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x03B: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x03C: INC R00
|
||||
"001101" & X"000", -- 0x03D: MOVC (0x00), R00
|
||||
"010101" & X"022", -- 0x03E: SUB R02, 0x02
|
||||
"110010" & X"02D", -- 0x03F: JNZ 0x02D
|
||||
"111011" & X"072", -- 0x040: CALL 0x072
|
||||
"000011" & X"060", -- 0x041: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x042: XOUT (0x07), R00
|
||||
"000011" & X"080", -- 0x043: MOV R00, 0x08
|
||||
"111011" & X"084", -- 0x044: CALL 0x084
|
||||
"110000" & X"029", -- 0x045: JMP 0x029
|
||||
"111011" & X"094", -- 0x046: CALL 0x094
|
||||
"111011" & X"07D", -- 0x047: CALL 0x07D
|
||||
"000011" & X"000", -- 0x048: MOV R00, 0x00
|
||||
"001101" & X"000", -- 0x049: MOVC (0x00), R00
|
||||
"101000" & X"0A0", -- 0x04A: XIN R00, (0x0A)
|
||||
"001111" & X"400", -- 0x04B: CMP R00, 0x40
|
||||
"111001" & X"07A", -- 0x04C: JEQ 0x07A
|
||||
"111011" & X"072", -- 0x04D: CALL 0x072
|
||||
"000011" & X"050", -- 0x04E: MOV R00, 0x05
|
||||
"100100" & X"070", -- 0x04F: XOUT (0x07), R00
|
||||
"000011" & X"083", -- 0x050: MOV R03, 0x08
|
||||
"101000" & X"070", -- 0x051: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x052: XOUT (0x01), R00
|
||||
"011001" & X"200", -- 0x053: AND R00, 0x20
|
||||
"110010" & X"051", -- 0x054: JNZ 0x051
|
||||
"001010" & X"001", -- 0x055: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x056: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x057: MOV R15, 0x08
|
||||
"000100" & X"002", -- 0x058: MOVX R02, (R00)
|
||||
"001110" & X"012", -- 0x059: CMP R02, R01
|
||||
"111010" & X"07B", -- 0x05A: JNE 0x07B
|
||||
"010001" & X"010", -- 0x05B: INC R00
|
||||
"010001" & X"011", -- 0x05C: INC R01
|
||||
"010101" & X"01F", -- 0x05D: DEC R15
|
||||
"110010" & X"058", -- 0x05E: JNZ 0x058
|
||||
"000011" & X"200", -- 0x05F: MOV R00, 0x20
|
||||
"100100" & X"070", -- 0x060: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x061: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x062: INC R00
|
||||
"001101" & X"000", -- 0x063: MOVC (0x00), R00
|
||||
"010101" & X"023", -- 0x064: SUB R03, 0x02
|
||||
"110010" & X"051", -- 0x065: JNZ 0x051
|
||||
"000011" & X"080", -- 0x066: MOV R00, 0x08
|
||||
"111011" & X"084", -- 0x067: CALL 0x084
|
||||
"110000" & X"04A", -- 0x068: JMP 0x04A
|
||||
"111100" & X"000", -- 0x069: PUSH R00
|
||||
"000011" & X"800", -- 0x06A: MOV R00, 0x80
|
||||
"100100" & X"070", -- 0x06B: XOUT (0x07), R00
|
||||
"101000" & X"070", -- 0x06C: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x06D: XOUT (0x01), R00
|
||||
"011001" & X"800", -- 0x06E: AND R00, 0x80
|
||||
"110001" & X"06C", -- 0x06F: JZ 0x06C
|
||||
"111101" & X"000", -- 0x070: POP R00
|
||||
"111110" & X"000", -- 0x071: RET
|
||||
"111011" & X"069", -- 0x072: CALL 0x069
|
||||
"111100" & X"000", -- 0x073: PUSH R00
|
||||
"101000" & X"070", -- 0x074: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x075: XOUT (0x01), R00
|
||||
"011001" & X"010", -- 0x076: AND R00, 0x01
|
||||
"110010" & X"074", -- 0x077: JNZ 0x074
|
||||
"111101" & X"000", -- 0x078: POP R00
|
||||
"111110" & X"000", -- 0x079: RET
|
||||
"110000" & X"07C", -- 0x07A: JMP 0x07C
|
||||
"110000" & X"07C", -- 0x07B: JMP 0x07C
|
||||
"110000" & X"00C", -- 0x07C: JMP 0x00C
|
||||
"111100" & X"000", -- 0x07D: PUSH R00
|
||||
"000011" & X"000", -- 0x07E: MOV R00, 0x00
|
||||
"100100" & X"080", -- 0x07F: XOUT (0x08), R00
|
||||
"100100" & X"090", -- 0x080: XOUT (0x09), R00
|
||||
"100100" & X"0A0", -- 0x081: XOUT (0x0A), R00
|
||||
"111101" & X"000", -- 0x082: POP R00
|
||||
"111110" & X"000", -- 0x083: RET
|
||||
"111100" & X"001", -- 0x084: PUSH R01
|
||||
"111100" & X"002", -- 0x085: PUSH R02
|
||||
"111100" & X"003", -- 0x086: PUSH R03
|
||||
"101000" & X"081", -- 0x087: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x088: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x089: XIN R03, (0x0A)
|
||||
"010000" & X"001", -- 0x08A: ADD R01, R00
|
||||
"010011" & X"002", -- 0x08B: ADDC R02, 0x00
|
||||
"010011" & X"003", -- 0x08C: ADDC R03, 0x00
|
||||
"100100" & X"081", -- 0x08D: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x08E: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x08F: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x090: POP R03
|
||||
"111101" & X"002", -- 0x091: POP R02
|
||||
"111101" & X"001", -- 0x092: POP R01
|
||||
"111110" & X"000", -- 0x093: RET
|
||||
"111110" & X"000", -- 0x094: RET
|
||||
"111110" & X"000", -- 0x095: RET
|
||||
"111110" & X"000", -- 0x096: RET
|
||||
"111110" & X"000", -- 0x097: RET
|
||||
"011001" & X"0F0", -- 0x098: AND R00, 0x0F
|
||||
"001111" & X"0A0", -- 0x099: CMP R00, 0x0A
|
||||
"110101" & X"09C", -- 0x09A: JLT 0x09C
|
||||
"010001" & X"070", -- 0x09B: ADD R00, 0x07
|
||||
"010001" & X"300", -- 0x09C: ADD R00, 0x30
|
||||
"111110" & X"000", -- 0x09D: RET
|
||||
"111100" & X"000", -- 0x09E: PUSH R00
|
||||
"111011" & X"098", -- 0x09F: CALL 0x098
|
||||
"000010" & X"001", -- 0x0A0: MOV R01, R00
|
||||
"111101" & X"000", -- 0x0A1: POP R00
|
||||
"101010" & X"000", -- 0x0A2: SWAP R00
|
||||
"111011" & X"098", -- 0x0A3: CALL 0x098
|
||||
"111110" & X"000" -- 0x0A4: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdram_test_short;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,317 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE sdram_test_short OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from sdram_test_short.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"56", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"72", -- 0x3B
|
||||
X"69", -- 0x3C
|
||||
X"66", -- 0x3D
|
||||
X"79", -- 0x3E
|
||||
X"20", -- 0x3F
|
||||
X"4F", -- 0x40
|
||||
X"4B", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"46", -- 0x43
|
||||
X"61", -- 0x44
|
||||
X"69", -- 0x45
|
||||
X"6C", -- 0x46
|
||||
X"65", -- 0x47
|
||||
X"64", -- 0x48
|
||||
X"20", -- 0x49
|
||||
X"61", -- 0x4A
|
||||
X"74", -- 0x4B
|
||||
X"20", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdram_test_short;
|
||||
|
||||
@@ -0,0 +1,413 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from sdram_test_short.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"56", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"72", -- 0x3B
|
||||
X"69", -- 0x3C
|
||||
X"66", -- 0x3D
|
||||
X"79", -- 0x3E
|
||||
X"20", -- 0x3F
|
||||
X"4F", -- 0x40
|
||||
X"4B", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"46", -- 0x43
|
||||
X"61", -- 0x44
|
||||
X"69", -- 0x45
|
||||
X"6C", -- 0x46
|
||||
X"65", -- 0x47
|
||||
X"64", -- 0x48
|
||||
X"20", -- 0x49
|
||||
X"61", -- 0x4A
|
||||
X"74", -- 0x4B
|
||||
X"20", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
@@ -0,0 +1,317 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE sdram_test OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from sdram_test.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"56", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"72", -- 0x3B
|
||||
X"69", -- 0x3C
|
||||
X"66", -- 0x3D
|
||||
X"79", -- 0x3E
|
||||
X"20", -- 0x3F
|
||||
X"4F", -- 0x40
|
||||
X"4B", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"46", -- 0x43
|
||||
X"61", -- 0x44
|
||||
X"69", -- 0x45
|
||||
X"6C", -- 0x46
|
||||
X"65", -- 0x47
|
||||
X"64", -- 0x48
|
||||
X"20", -- 0x49
|
||||
X"61", -- 0x4A
|
||||
X"74", -- 0x4B
|
||||
X"20", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end sdram_test;
|
||||
|
||||
@@ -0,0 +1,413 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from sdram_test.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"56", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"72", -- 0x3B
|
||||
X"69", -- 0x3C
|
||||
X"66", -- 0x3D
|
||||
X"79", -- 0x3E
|
||||
X"20", -- 0x3F
|
||||
X"4F", -- 0x40
|
||||
X"4B", -- 0x41
|
||||
X"00", -- 0x42
|
||||
X"46", -- 0x43
|
||||
X"61", -- 0x44
|
||||
X"69", -- 0x45
|
||||
X"6C", -- 0x46
|
||||
X"65", -- 0x47
|
||||
X"64", -- 0x48
|
||||
X"20", -- 0x49
|
||||
X"61", -- 0x4A
|
||||
X"74", -- 0x4B
|
||||
X"20", -- 0x4C
|
||||
X"00", -- 0x4D
|
||||
X"2E", -- 0x4E
|
||||
X"00", -- 0x4F
|
||||
X"00", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"00", -- 0x52
|
||||
X"00", -- 0x53
|
||||
X"00", -- 0x54
|
||||
X"00", -- 0x55
|
||||
X"00", -- 0x56
|
||||
X"00", -- 0x57
|
||||
X"00", -- 0x58
|
||||
X"00", -- 0x59
|
||||
X"00", -- 0x5A
|
||||
X"00", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"00", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,408 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
Library UNISIM;
|
||||
use UNISIM.vcomponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY systest IS
|
||||
PORT
|
||||
(
|
||||
sys_rst_n_in : in std_logic;
|
||||
sys_clk_in : in std_logic;
|
||||
sys_btn : in std_logic_vector(4 downto 0);
|
||||
sys_dip : in std_logic_vector(7 downto 0);
|
||||
sys_led : out std_logic_vector(8 downto 0);
|
||||
sys_rx : in std_logic;
|
||||
sys_tx : out std_logic;
|
||||
sys_lcd_d : inout std_logic_vector(3 downto 0);
|
||||
sys_lcd_e : out std_logic;
|
||||
sys_lcd_rs : out std_logic;
|
||||
sys_lcd_rw : out std_logic
|
||||
);
|
||||
END systest;
|
||||
|
||||
|
||||
ARCHITECTURE behavior OF systest IS
|
||||
|
||||
COMPONENT embedded_cpu
|
||||
Port (
|
||||
rst : in STD_LOGIC;
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
int_in : in STD_LOGIC;
|
||||
int_ack : out STD_LOGIC;
|
||||
xmem_we : out STD_LOGIC;
|
||||
xmem_re : out STD_LOGIC;
|
||||
xmem_din : in unsigned (DMEM_WIDTH-1 downto 0);
|
||||
xmem_dout : out unsigned (DMEM_WIDTH-1 downto 0);
|
||||
xmem_addr : out unsigned (DMEM_WIDTH-1 downto 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--
|
||||
-- declaration of UART transmitter with integral 16 byte FIFO buffer
|
||||
--
|
||||
component uart_tx
|
||||
Port ( data_in : in std_logic_vector(7 downto 0);
|
||||
write_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
serial_out : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
--
|
||||
-- declaration of UART Receiver with integral 16 byte FIFO buffer
|
||||
--
|
||||
component uart_rx
|
||||
Port ( serial_in : in std_logic;
|
||||
data_out : out std_logic_vector(7 downto 0);
|
||||
read_buffer : in std_logic;
|
||||
reset_buffer : in std_logic;
|
||||
en_16_x_baud : in std_logic;
|
||||
buffer_data_present : out std_logic;
|
||||
buffer_full : out std_logic;
|
||||
buffer_half_full : out std_logic;
|
||||
clk : in std_logic);
|
||||
end component;
|
||||
|
||||
signal rst : std_logic;
|
||||
signal clk, clk0 : std_logic;
|
||||
signal ce : std_logic;
|
||||
signal int_req, int_in, int_ack, int_en : std_logic;
|
||||
|
||||
signal cpu_din : data_t;
|
||||
signal cpu_dout : data_t;
|
||||
signal cpu_addr : unsigned (DMEM_WIDTH-1 downto 0);
|
||||
signal cpu_we, reg_sel : std_logic;
|
||||
signal cpu_re : std_logic;
|
||||
signal led_reg_we, lcd_reg_we, ctrl_reg_we : std_logic;
|
||||
signal rom_dout, reg_dout, ctrl_reg : data_t;
|
||||
signal led_reg : data_t;
|
||||
signal lcd_reg_out, lcd_reg_in: data_t;
|
||||
--
|
||||
-- Signals for connection of peripherals
|
||||
--
|
||||
signal uart_status_port : data_t;
|
||||
--
|
||||
-- Signals to form an timer generating an interrupt every microsecond
|
||||
--
|
||||
constant timer_reload : integer := 99999;
|
||||
signal timer_count : integer range 0 to 99999 :=0;
|
||||
signal timer_pulse, timer_en : std_logic;
|
||||
--
|
||||
-- Signals for UART connections
|
||||
--
|
||||
signal baud_count : integer range 0 to 255 :=0;
|
||||
signal en_16_x_baud : std_logic;
|
||||
signal write_to_uart : std_logic;
|
||||
signal tx_full : std_logic;
|
||||
signal tx_half_full : std_logic;
|
||||
signal read_from_uart : std_logic;
|
||||
signal rx_data : std_logic_vector(7 downto 0);
|
||||
signal rx_data_present : std_logic;
|
||||
signal rx_full : std_logic;
|
||||
signal rx_half_full : std_logic;
|
||||
|
||||
signal rom_addr : unsigned(5 downto 0);
|
||||
signal reg_addr : unsigned(5 downto 0);
|
||||
|
||||
constant rom_data : string(1 to 64) :=
|
||||
(
|
||||
"J-CPU V1.0 " &
|
||||
' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' &
|
||||
' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' &
|
||||
' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' &
|
||||
' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' ' & ' '
|
||||
|
||||
);
|
||||
constant lcd_e : integer := 7;
|
||||
constant lcd_rs : integer := 6;
|
||||
constant lcd_rw : integer := 5;
|
||||
|
||||
BEGIN
|
||||
|
||||
int_in <= sys_btn(4) or sys_dip(7) or timer_pulse or ctrl_reg(7) or rx_data_present;
|
||||
clk0 <= sys_clk_in;
|
||||
ce <= not rst;
|
||||
int_en <= ctrl_reg(0);
|
||||
timer_en <= ctrl_reg(1);
|
||||
sys_led(8) <= int_in;
|
||||
sys_led (7 downto 0) <= std_logic_vector(led_reg(7 downto 0));
|
||||
uart_status_port <= "000" & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
|
||||
sys_lcd_d <= std_logic_vector(lcd_reg_out(3 downto 0)) when lcd_reg_out(lcd_rw) = '0' else (others => 'Z');
|
||||
sys_lcd_e <= lcd_reg_out(lcd_e);
|
||||
sys_lcd_rw <= lcd_reg_out(lcd_rw);
|
||||
sys_lcd_rs <= lcd_reg_out(lcd_rs);
|
||||
rom_addr <= cpu_addr(5 downto 0);
|
||||
reg_addr <= cpu_addr(5 downto 0);
|
||||
|
||||
BUFG_inst : BUFG
|
||||
port map (
|
||||
O => clk, -- Clock buffer output
|
||||
I => clk0 -- Clock buffer input
|
||||
);
|
||||
|
||||
clock_halbe:
|
||||
process(sys_rst_n_in, sys_clk_in)
|
||||
variable reset_latency : integer range 0 to 999 := 999;
|
||||
begin
|
||||
if sys_rst_n_in = '0' then
|
||||
-- clk0 <= '0';
|
||||
rst <= '1';
|
||||
reset_latency := 999;
|
||||
elsif rising_edge(sys_clk_in) then
|
||||
rst <= '1';
|
||||
-- clk0 <= not clk0;
|
||||
if reset_latency /= 0 then
|
||||
reset_latency := reset_latency - 1;
|
||||
else
|
||||
rst <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
timer:
|
||||
process(rst, clk, timer_count, timer_en)
|
||||
begin
|
||||
if rst = '1' then
|
||||
timer_count <= timer_reload;
|
||||
timer_pulse <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
timer_pulse <= '0';
|
||||
if timer_count /= 0 then
|
||||
if timer_en = '1' then
|
||||
timer_count <= timer_count - 1;
|
||||
end if;
|
||||
else
|
||||
timer_pulse <= '1';
|
||||
timer_count <= timer_reload;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
reg_mux:
|
||||
process(clk, reg_addr, reg_sel, cpu_we, cpu_re, sys_btn, sys_dip, lcd_reg_in, led_reg, uart_status_port)
|
||||
variable data : data_t;
|
||||
begin
|
||||
led_reg_we <= '0';
|
||||
lcd_reg_we <= '0';
|
||||
ctrl_reg_we <= '0';
|
||||
write_to_uart <= '0';
|
||||
read_from_uart <= '0';
|
||||
data := (others => '-');
|
||||
|
||||
if reg_sel = '1' then
|
||||
case reg_addr(2 downto 0) is
|
||||
|
||||
when "000" => -- C0
|
||||
data := "0000" & unsigned(sys_btn(3 downto 0));
|
||||
when "001" => -- C1
|
||||
data := led_reg;
|
||||
led_reg_we <= cpu_we;
|
||||
when "010" => -- C2
|
||||
data := unsigned(rx_data);
|
||||
write_to_uart <= cpu_we;
|
||||
read_from_uart <= cpu_re;
|
||||
when "011" => -- C3
|
||||
data := lcd_reg_in;
|
||||
lcd_reg_we <= cpu_we;
|
||||
when "100" => -- C4
|
||||
data := ctrl_reg;
|
||||
ctrl_reg_we <= cpu_we;
|
||||
when "101" => -- C5
|
||||
data := unsigned(sys_dip);
|
||||
when "110" => -- C6
|
||||
data := uart_status_port;
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
end if;
|
||||
|
||||
if rising_edge(clk) then
|
||||
reg_dout <= data;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
din_mux:
|
||||
process(clk, cpu_addr, cpu_we, rom_dout, reg_dout)
|
||||
variable data : data_t;
|
||||
begin
|
||||
reg_sel <= '0';
|
||||
|
||||
case cpu_addr(7 downto 6) is
|
||||
when "00" | "01" => -- 00 .. 7F
|
||||
data := X"AA";
|
||||
when "10" => -- 80 .. BF
|
||||
data := rom_dout;
|
||||
when "11" => -- C0 .. FF
|
||||
data := reg_dout;
|
||||
reg_sel <= '1';
|
||||
|
||||
when others =>
|
||||
data := (others => '-');
|
||||
end case;
|
||||
|
||||
cpu_din <= data;
|
||||
|
||||
end process;
|
||||
|
||||
ctrl_reg_write:
|
||||
process(rst, clk, ctrl_reg_we, cpu_dout)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
ctrl_reg <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if ctrl_reg_we = '1' then
|
||||
ctrl_reg <= cpu_dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
led_reg_write:
|
||||
process(rst, clk, led_reg_we, cpu_dout)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
led_reg <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if led_reg_we = '1' then
|
||||
led_reg <= cpu_dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_lcd_reg_write:
|
||||
process(rst, clk, lcd_reg_we, cpu_dout)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
lcd_reg_out <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if lcd_reg_we = '1' then
|
||||
lcd_reg_out <= cpu_dout;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
proc_lcd_reg_sample:
|
||||
process(rst, clk, sys_lcd_d, lcd_reg_out)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
lcd_reg_in <= (others => '0');
|
||||
elsif rising_edge(clk) then
|
||||
if lcd_reg_out(lcd_rw) = '1' then
|
||||
lcd_reg_in <= unsigned("0000" & sys_lcd_d);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
int_register:
|
||||
process(rst, clk, int_in, int_ack)
|
||||
begin
|
||||
if (rst = '1') then
|
||||
int_req <= '0';
|
||||
elsif rising_edge(clk) then
|
||||
if int_ack = '1' then
|
||||
int_req <= '0';
|
||||
elsif int_en = '1' and int_in = '1' then
|
||||
int_req <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
the_embedded_cpu: embedded_cpu
|
||||
PORT MAP(
|
||||
rst => rst,
|
||||
clk => clk,
|
||||
ce => ce,
|
||||
int_in => int_req,
|
||||
int_ack => int_ack,
|
||||
xmem_we => cpu_we,
|
||||
xmem_re => cpu_re,
|
||||
xmem_din => cpu_din,
|
||||
xmem_dout => cpu_dout,
|
||||
xmem_addr => cpu_addr
|
||||
);
|
||||
|
||||
transmit: uart_tx
|
||||
port map ( data_in => std_logic_vector(cpu_dout),
|
||||
write_buffer => write_to_uart,
|
||||
reset_buffer => rst,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
serial_out => sys_tx,
|
||||
buffer_full => tx_full,
|
||||
buffer_half_full => tx_half_full,
|
||||
clk => clk );
|
||||
|
||||
receive: uart_rx
|
||||
port map ( serial_in => sys_rx,
|
||||
data_out => rx_data,
|
||||
read_buffer => read_from_uart,
|
||||
reset_buffer => rst,
|
||||
en_16_x_baud => en_16_x_baud,
|
||||
buffer_data_present => rx_data_present,
|
||||
buffer_full => rx_full,
|
||||
buffer_half_full => rx_half_full,
|
||||
clk => clk );
|
||||
--
|
||||
-- Set baud rate to 38400 for the UART communications
|
||||
-- Requires en_16_x_baud to be 614400Hz which is a single cycle pulse every 163 cycles at 100MHz
|
||||
--
|
||||
-- NOTE : If the highest value for baud_count exceeds 127 you will need to adjust
|
||||
-- the range of integers in the signal declaration for baud_count.
|
||||
--
|
||||
|
||||
baud_timer: process(clk)
|
||||
begin
|
||||
if clk'event and clk='1' then
|
||||
if baud_count=162 then
|
||||
baud_count <= 0;
|
||||
en_16_x_baud <= '1';
|
||||
else
|
||||
baud_count <= baud_count + 1;
|
||||
en_16_x_baud <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process baud_timer;
|
||||
|
||||
ROM_RD:
|
||||
process(rst, clk, rom_addr)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
rom_dout <= to_unsigned(character'pos(rom_data(to_integer(rom_addr)+1)), data_t'length);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
END;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,19 @@
|
||||
library IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
configuration cpu_irom of cpu_embedded is
|
||||
for rtl
|
||||
for inst_irom : irom
|
||||
use entity work.irom(loadable);
|
||||
end for;
|
||||
end for;
|
||||
end configuration cpu_irom;
|
||||
|
||||
configuration system_xrom of systest is
|
||||
for behavior
|
||||
for inst_xrom : xrom
|
||||
use entity work.xrom(loadable);
|
||||
end for;
|
||||
end for;
|
||||
end configuration system_xrom;
|
||||
@@ -0,0 +1,166 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: testbench for system test using Xilinx ML-402
|
||||
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
|
||||
-- This library is free software; you can redistribute it and/or
|
||||
-- modify it under the terms of the GNU Lesser General Public
|
||||
-- License as published by the Free Software Foundation; either
|
||||
-- version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
-- This library is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
-- Lesser General Public License for more details.
|
||||
|
||||
-- You should have received a copy of the GNU Lesser General Public
|
||||
-- License along with this library; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
use work.ddr_sdr_conf_pkg.all;
|
||||
use work.systest_cfg.all;
|
||||
|
||||
ENTITY tb_systest IS
|
||||
END tb_systest;
|
||||
|
||||
ARCHITECTURE behavior OF tb_systest IS
|
||||
|
||||
constant CLK_PERIOD : time := 10 ns;
|
||||
signal sys_rst_n_in : std_logic := '0';
|
||||
signal sys_clk_in : std_logic := '1';
|
||||
signal dip : unsigned(7 downto 0) := (others => '0');
|
||||
signal btn : unsigned(4 downto 0) := (others => '0');
|
||||
signal led : unsigned(8 downto 0);
|
||||
signal sys_rx : std_logic := '0';
|
||||
signal sys_tx : std_logic;
|
||||
|
||||
signal sys_lcd_d : unsigned(3 downto 0);
|
||||
signal sys_lcd_e : std_logic;
|
||||
signal sys_lcd_rs : std_logic;
|
||||
signal sys_lcd_rw : std_logic;
|
||||
|
||||
signal refresh : boolean:= true;
|
||||
|
||||
signal sys_sdr_clk_p : std_logic; -- ddr_sdram_clock
|
||||
signal sys_sdr_clk_n : std_logic; -- /ddr_sdram_clock
|
||||
signal sys_sdr_cke_q : std_logic; -- clock enable
|
||||
signal sys_sdr_cs_qn : std_logic; -- /chip select
|
||||
signal sys_sdr_ras_qn : std_logic; -- /ras
|
||||
signal sys_sdr_cas_qn : std_logic; -- /cas
|
||||
signal sys_sdr_we_qn : std_logic; -- /write enable
|
||||
signal sys_sdr_dm_q : unsigned(DDR_DM_WIDTH-1 downto 0); -- data mask bits, set to "00"
|
||||
signal sys_sdr_dqs_q : unsigned(DDR_DQS_WIDTH-1 downto 0); -- data strobe, only for write
|
||||
signal sys_sdr_ba_q : unsigned(DDR_BANK_WIDTH-1 downto 0); -- bank select
|
||||
signal sys_sdr_a_q : unsigned(DDR_ADDR_WIDTH-1 downto 0); -- address bus
|
||||
signal sys_sdr_data : unsigned(DDR_DATA_WIDTH-1 downto 0); -- bidir data bus
|
||||
|
||||
signal sys_error : unsigned(1 downto 0); -- indicates DCM Errors
|
||||
signal sys_sdr_clk_fb : std_logic;
|
||||
|
||||
BEGIN
|
||||
|
||||
uut: entity work.systest
|
||||
-- GENERIC MAP
|
||||
-- (
|
||||
-- ddr_phaseshift => 90,
|
||||
-- ddr_frequency_hz => 100E6
|
||||
-- )
|
||||
PORT MAP
|
||||
(
|
||||
sys_rst_n_in => sys_rst_n_in,
|
||||
sys_clk_in => sys_clk_in,
|
||||
sys_btn => btn,
|
||||
sys_dip => dip,
|
||||
sys_led => led,
|
||||
sys_rx => sys_rx,
|
||||
sys_tx => sys_tx,
|
||||
sys_lcd_d => sys_lcd_d,
|
||||
sys_lcd_e => sys_lcd_e,
|
||||
sys_lcd_rs => sys_lcd_rs,
|
||||
sys_lcd_rw => sys_lcd_rw,
|
||||
|
||||
sys_sdr_clk_p => sys_sdr_clk_p,
|
||||
sys_sdr_clk_n => sys_sdr_clk_n,
|
||||
sys_sdr_cke_q => sys_sdr_cke_q,
|
||||
sys_sdr_clk_fb => sys_sdr_clk_fb,
|
||||
sys_sdr_cs_qn => sys_sdr_cs_qn,
|
||||
sys_sdr_ras_qn => sys_sdr_ras_qn,
|
||||
sys_sdr_cas_qn => sys_sdr_cas_qn,
|
||||
sys_sdr_we_qn => sys_sdr_we_qn,
|
||||
sys_sdr_dm_q => sys_sdr_dm_q,
|
||||
sys_sdr_dqs_q => sys_sdr_dqs_q,
|
||||
sys_sdr_ba_q => sys_sdr_ba_q,
|
||||
sys_sdr_a_q => sys_sdr_a_q,
|
||||
sys_sdr_data => sys_sdr_data,
|
||||
sys_error => sys_error
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_0 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(sys_sdr_data(15 downto 0)),
|
||||
dqs => std_logic_vector(sys_sdr_dqs_q(1 downto 0)),
|
||||
addr => std_logic_vector(sys_sdr_a_q),
|
||||
ba => std_logic_vector(sys_sdr_ba_q),
|
||||
clk => sys_sdr_clk_p,
|
||||
clk_n => sys_sdr_clk_n,
|
||||
cke => sys_sdr_cke_q,
|
||||
cs_n => sys_sdr_cs_qn,
|
||||
ras_n => sys_sdr_ras_qn,
|
||||
cas_n => sys_sdr_cas_qn,
|
||||
we_n => sys_sdr_we_qn,
|
||||
dm => std_logic_vector(sys_sdr_dm_q(1 downto 0))
|
||||
);
|
||||
|
||||
-- MICRON DDR SDRAM Simulation Model
|
||||
i_mt46v16m16_1 : entity work.mt46v16m16
|
||||
port map (
|
||||
dq => std_logic_vector(sys_sdr_data(31 downto 16)),
|
||||
dqs => std_logic_vector(sys_sdr_dqs_q(3 downto 2)),
|
||||
addr => std_logic_vector(sys_sdr_a_q),
|
||||
ba => std_logic_vector(sys_sdr_ba_q),
|
||||
clk => sys_sdr_clk_p,
|
||||
clk_n => sys_sdr_clk_n,
|
||||
cke => sys_sdr_cke_q,
|
||||
cs_n => sys_sdr_cs_qn,
|
||||
ras_n => sys_sdr_ras_qn,
|
||||
cas_n => sys_sdr_cas_qn,
|
||||
we_n => sys_sdr_we_qn,
|
||||
dm => std_logic_vector(sys_sdr_dm_q(3 downto 2))
|
||||
);
|
||||
|
||||
sys_sdr_clk_fb <= sys_sdr_clk_p after 2300 ps;
|
||||
refresh <= true when falling_edge(sys_sdr_ras_qn) and falling_edge(sys_sdr_cas_qn) and sys_sdr_we_qn='1' else false;
|
||||
|
||||
CLK_GEN: process
|
||||
begin
|
||||
wait for CLK_PERIOD/2;
|
||||
sys_clk_in <= not sys_clk_in;
|
||||
end process;
|
||||
|
||||
STIMULUS: process
|
||||
|
||||
begin
|
||||
|
||||
wait for 3*CLK_PERIOD;
|
||||
sys_rst_n_in <= '1';
|
||||
wait for 2*CLK_PERIOD;
|
||||
|
||||
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,786 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY irom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in inst_addr_t;
|
||||
dout : out inst_t
|
||||
);
|
||||
END irom;
|
||||
|
||||
ARCHITECTURE vga_test OF irom IS
|
||||
|
||||
type imem_rom_t is array (0 to 724) of inst_t;
|
||||
|
||||
-- Assembled from vga_test.jsm
|
||||
constant imem_rom : imem_rom_t :=
|
||||
(
|
||||
"110000" & X"02D", -- 0x000: JMP 0x02D
|
||||
"111100" & X"000", -- 0x001: PUSH R00
|
||||
"111100" & X"001", -- 0x002: PUSH R01
|
||||
"101000" & X"061", -- 0x003: XIN R01, (0x06)
|
||||
"011001" & X"101", -- 0x004: AND R01, 0x10
|
||||
"110001" & X"015", -- 0x005: JZ 0x015
|
||||
"101000" & X"020", -- 0x006: XIN R00, (0x02)
|
||||
"001010" & X"5F1", -- 0x007: MOVC R01, (0x5F)
|
||||
"001011" & X"010", -- 0x008: MOVC (R00), R01
|
||||
"010001" & X"011", -- 0x009: INC R01
|
||||
"001111" & X"5E1", -- 0x00A: CMP R01, 0x5E
|
||||
"111010" & X"00D", -- 0x00B: JNE 0x00D
|
||||
"000011" & X"1E1", -- 0x00C: MOV R01, 0x1E
|
||||
"001101" & X"5F1", -- 0x00D: MOVC (0x5F), R01
|
||||
"001010" & X"5E0", -- 0x00E: MOVC R00, (0x5E)
|
||||
"001110" & X"010", -- 0x00F: CMP R00, R01
|
||||
"111010" & X"003", -- 0x010: JNE 0x003
|
||||
"101000" & X"040", -- 0x011: XIN R00, (0x04)
|
||||
"011011" & X"200", -- 0x012: OR R00, 0x20
|
||||
"100100" & X"040", -- 0x013: XOUT (0x04), R00
|
||||
"110000" & X"003", -- 0x014: JMP 0x003
|
||||
"111011" & X"019", -- 0x015: CALL 0x019
|
||||
"111101" & X"001", -- 0x016: POP R01
|
||||
"111101" & X"000", -- 0x017: POP R00
|
||||
"111111" & X"000", -- 0x018: RETI
|
||||
"101000" & X"000", -- 0x019: XIN R00, (0x00)
|
||||
"011001" & X"010", -- 0x01A: AND R00, 0x01
|
||||
"110001" & X"023", -- 0x01B: JZ 0x023
|
||||
"000011" & X"140", -- 0x01C: MOV R00, 0x14
|
||||
"100101" & X"000", -- 0x01D: XOUT (R00), 0x00
|
||||
"010001" & X"010", -- 0x01E: INC R00
|
||||
"100101" & X"000", -- 0x01F: XOUT (R00), 0x00
|
||||
"010001" & X"010", -- 0x020: INC R00
|
||||
"100101" & X"000", -- 0x021: XOUT (R00), 0x00
|
||||
"110000" & X"02C", -- 0x022: JMP 0x02C
|
||||
"101000" & X"000", -- 0x023: XIN R00, (0x00)
|
||||
"011001" & X"020", -- 0x024: AND R00, 0x02
|
||||
"110001" & X"02C", -- 0x025: JZ 0x02C
|
||||
"000011" & X"140", -- 0x026: MOV R00, 0x14
|
||||
"100101" & X"000", -- 0x027: XOUT (R00), 0x00
|
||||
"010001" & X"010", -- 0x028: INC R00
|
||||
"100101" & X"000", -- 0x029: XOUT (R00), 0x00
|
||||
"010001" & X"010", -- 0x02A: INC R00
|
||||
"100101" & X"200", -- 0x02B: XOUT (R00), 0x20
|
||||
"111110" & X"000", -- 0x02C: RET
|
||||
"111011" & X"1C6", -- 0x02D: CALL 0x1C6
|
||||
"111011" & X"1FB", -- 0x02E: CALL 0x1FB
|
||||
"000011" & X"000", -- 0x02F: MOV R00, 0x00
|
||||
"100100" & X"010", -- 0x030: XOUT (0x01), R00
|
||||
"000011" & X"040", -- 0x031: MOV R00, 0x04
|
||||
"100100" & X"040", -- 0x032: XOUT (0x04), R00
|
||||
"101000" & X"040", -- 0x033: XIN R00, (0x04)
|
||||
"011011" & X"020", -- 0x034: OR R00, 0x02
|
||||
"100100" & X"040", -- 0x035: XOUT (0x04), R00
|
||||
"000011" & X"030", -- 0x036: MOV R00, 0x03
|
||||
"100110" & X"030", -- 0x037: COUT (0x03), R00
|
||||
"000011" & X"010", -- 0x038: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x039: CALL 0x218
|
||||
"000011" & X"000", -- 0x03A: MOV R00, 0x00
|
||||
"000011" & X"C01", -- 0x03B: MOV R01, 0xC0
|
||||
"100100" & X"101", -- 0x03C: XOUT (0x10), R01
|
||||
"100100" & X"111", -- 0x03D: XOUT (0x11), R01
|
||||
"100100" & X"121", -- 0x03E: XOUT (0x12), R01
|
||||
"111011" & X"28C", -- 0x03F: CALL 0x28C
|
||||
"111011" & X"271", -- 0x040: CALL 0x271
|
||||
"000011" & X"031", -- 0x041: MOV R01, 0x03
|
||||
"111011" & X"21D", -- 0x042: CALL 0x21D
|
||||
"000011" & X"031", -- 0x043: MOV R01, 0x03
|
||||
"111011" & X"27D", -- 0x044: CALL 0x27D
|
||||
"000011" & X"001", -- 0x045: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x046: CALL 0x289
|
||||
"101000" & X"040", -- 0x047: XIN R00, (0x04)
|
||||
"011001" & X"CF0", -- 0x048: AND R00, 0xCF
|
||||
"100100" & X"040", -- 0x049: XOUT (0x04), R00
|
||||
"000011" & X"000", -- 0x04A: MOV R00, 0x00
|
||||
"001101" & X"010", -- 0x04B: MOVC (0x01), R00
|
||||
"111011" & X"080", -- 0x04C: CALL 0x080
|
||||
"111011" & X"0D9", -- 0x04D: CALL 0x0D9
|
||||
"111011" & X"10D", -- 0x04E: CALL 0x10D
|
||||
"001010" & X"010", -- 0x04F: MOVC R00, (0x01)
|
||||
"010001" & X"010", -- 0x050: INC R00
|
||||
"001101" & X"010", -- 0x051: MOVC (0x01), R00
|
||||
"110000" & X"04D", -- 0x052: JMP 0x04D
|
||||
"000011" & X"010", -- 0x053: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x054: CALL 0x218
|
||||
"000011" & X"0E1", -- 0x055: MOV R01, 0x0E
|
||||
"111011" & X"21D", -- 0x056: CALL 0x21D
|
||||
"000011" & X"0E1", -- 0x057: MOV R01, 0x0E
|
||||
"111011" & X"286", -- 0x058: CALL 0x286
|
||||
"000011" & X"001", -- 0x059: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x05A: CALL 0x289
|
||||
"000011" & X"000", -- 0x05B: MOV R00, 0x00
|
||||
"000011" & X"001", -- 0x05C: MOV R01, 0x00
|
||||
"000011" & X"002", -- 0x05D: MOV R02, 0x00
|
||||
"111011" & X"16A", -- 0x05E: CALL 0x16A
|
||||
"000011" & X"800", -- 0x05F: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x060: MOV R15, 0x08
|
||||
"000111" & X"000", -- 0x061: MOVX (R00), 0x00
|
||||
"010001" & X"010", -- 0x062: INC R00
|
||||
"010101" & X"01F", -- 0x063: DEC R15
|
||||
"110010" & X"061", -- 0x064: JNZ 0x061
|
||||
"000011" & X"082", -- 0x065: MOV R02, 0x08
|
||||
"101000" & X"070", -- 0x066: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x067: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x068: AND R00, 0x04
|
||||
"110010" & X"066", -- 0x069: JNZ 0x066
|
||||
"000011" & X"100", -- 0x06A: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x06B: XOUT (0x07), R00
|
||||
"010101" & X"022", -- 0x06C: SUB R02, 0x02
|
||||
"110010" & X"066", -- 0x06D: JNZ 0x066
|
||||
"111011" & X"147", -- 0x06E: CALL 0x147
|
||||
"000011" & X"060", -- 0x06F: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x070: XOUT (0x07), R00
|
||||
"101000" & X"080", -- 0x071: XIN R00, (0x08)
|
||||
"001111" & X"F80", -- 0x072: CMP R00, 0xF8
|
||||
"111010" & X"07A", -- 0x073: JNE 0x07A
|
||||
"101000" & X"090", -- 0x074: XIN R00, (0x09)
|
||||
"001111" & X"FF0", -- 0x075: CMP R00, 0xFF
|
||||
"111010" & X"07A", -- 0x076: JNE 0x07A
|
||||
"101000" & X"0A0", -- 0x077: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x078: CMP R00, 0xFF
|
||||
"111001" & X"07D", -- 0x079: JEQ 0x07D
|
||||
"000011" & X"080", -- 0x07A: MOV R00, 0x08
|
||||
"111011" & X"16E", -- 0x07B: CALL 0x16E
|
||||
"110000" & X"065", -- 0x07C: JMP 0x065
|
||||
"111011" & X"18E", -- 0x07D: CALL 0x18E
|
||||
"111011" & X"292", -- 0x07E: CALL 0x292
|
||||
"111110" & X"000", -- 0x07F: RET
|
||||
"000011" & X"010", -- 0x080: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x081: CALL 0x218
|
||||
"000011" & X"391", -- 0x082: MOV R01, 0x39
|
||||
"111011" & X"21D", -- 0x083: CALL 0x21D
|
||||
"000011" & X"391", -- 0x084: MOV R01, 0x39
|
||||
"111011" & X"286", -- 0x085: CALL 0x286
|
||||
"000011" & X"001", -- 0x086: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x087: CALL 0x289
|
||||
"000011" & X"F80", -- 0x088: MOV R00, 0xF8
|
||||
"000011" & X"FF1", -- 0x089: MOV R01, 0xFF
|
||||
"000011" & X"132", -- 0x08A: MOV R02, 0x13
|
||||
"111011" & X"16A", -- 0x08B: CALL 0x16A
|
||||
"000011" & X"00F", -- 0x08C: MOV R15, 0x00
|
||||
"111011" & X"1D2", -- 0x08D: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x08E: JC 0x080
|
||||
"010001" & X"01F", -- 0x08F: INC R15
|
||||
"001111" & X"0AF", -- 0x090: CMP R15, 0x0A
|
||||
"111010" & X"08D", -- 0x091: JNE 0x08D
|
||||
"111011" & X"1D2", -- 0x092: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x093: JC 0x080
|
||||
"010001" & X"01F", -- 0x094: INC R15
|
||||
"001101" & X"020", -- 0x095: MOVC (0x02), R00
|
||||
"111011" & X"1D2", -- 0x096: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x097: JC 0x080
|
||||
"010001" & X"01F", -- 0x098: INC R15
|
||||
"001101" & X"030", -- 0x099: MOVC (0x03), R00
|
||||
"111011" & X"1D2", -- 0x09A: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x09B: JC 0x080
|
||||
"010001" & X"01F", -- 0x09C: INC R15
|
||||
"001101" & X"040", -- 0x09D: MOVC (0x04), R00
|
||||
"111011" & X"1D2", -- 0x09E: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x09F: JC 0x080
|
||||
"010001" & X"01F", -- 0x0A0: INC R15
|
||||
"001101" & X"050", -- 0x0A1: MOVC (0x05), R00
|
||||
"001010" & X"021", -- 0x0A2: MOVC R01, (0x02)
|
||||
"111011" & X"1D2", -- 0x0A3: CALL 0x1D2
|
||||
"110011" & X"080", -- 0x0A4: JC 0x080
|
||||
"010001" & X"01F", -- 0x0A5: INC R15
|
||||
"001110" & X"01F", -- 0x0A6: CMP R15, R01
|
||||
"111010" & X"0A3", -- 0x0A7: JNE 0x0A3
|
||||
"000011" & X"08F", -- 0x0A8: MOV R15, 0x08
|
||||
"000011" & X"1D1", -- 0x0A9: MOV R01, 0x1D
|
||||
"000011" & X"032", -- 0x0AA: MOV R02, 0x03
|
||||
"010101" & X"012", -- 0x0AB: DEC R02
|
||||
"000010" & X"013", -- 0x0AC: MOV R03, R01
|
||||
"111011" & X"1D2", -- 0x0AD: CALL 0x1D2
|
||||
"110011" & X"0D7", -- 0x0AE: JC 0x0D7
|
||||
"010100" & X"023", -- 0x0AF: SUB R03, R02
|
||||
"001011" & X"030", -- 0x0B0: MOVC (R00), R03
|
||||
"001111" & X"002", -- 0x0B1: TST R02
|
||||
"110010" & X"0AB", -- 0x0B2: JNZ 0x0AB
|
||||
"010101" & X"031", -- 0x0B3: SUB R01, 0x03
|
||||
"010101" & X"01F", -- 0x0B4: DEC R15
|
||||
"110010" & X"0AA", -- 0x0B5: JNZ 0x0AA
|
||||
"000011" & X"082", -- 0x0B6: MOV R02, 0x08
|
||||
"000011" & X"061", -- 0x0B7: MOV R01, 0x06
|
||||
"000011" & X"803", -- 0x0B8: MOV R03, 0x80
|
||||
"001001" & X"010", -- 0x0B9: MOVC R00, (R01)
|
||||
"000110" & X"030", -- 0x0BA: MOVX (R00), R03
|
||||
"010001" & X"011", -- 0x0BB: INC R01
|
||||
"010001" & X"013", -- 0x0BC: INC R03
|
||||
"001111" & X"863", -- 0x0BD: CMP R03, 0x86
|
||||
"111010" & X"0B9", -- 0x0BE: JNE 0x0B9
|
||||
"101000" & X"070", -- 0x0BF: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x0C0: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x0C1: AND R00, 0x04
|
||||
"110010" & X"0BF", -- 0x0C2: JNZ 0x0BF
|
||||
"000011" & X"100", -- 0x0C3: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x0C4: XOUT (0x07), R00
|
||||
"010101" & X"022", -- 0x0C5: SUB R02, 0x02
|
||||
"110010" & X"0B8", -- 0x0C6: JNZ 0x0B8
|
||||
"111011" & X"147", -- 0x0C7: CALL 0x147
|
||||
"000011" & X"060", -- 0x0C8: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x0C9: XOUT (0x07), R00
|
||||
"111011" & X"18E", -- 0x0CA: CALL 0x18E
|
||||
"101000" & X"080", -- 0x0CB: XIN R00, (0x08)
|
||||
"001111" & X"000", -- 0x0CC: TST R00
|
||||
"110010" & X"0D4", -- 0x0CD: JNZ 0x0D4
|
||||
"101000" & X"090", -- 0x0CE: XIN R00, (0x09)
|
||||
"001111" & X"000", -- 0x0CF: TST R00
|
||||
"110010" & X"0D4", -- 0x0D0: JNZ 0x0D4
|
||||
"101000" & X"0A0", -- 0x0D1: XIN R00, (0x0A)
|
||||
"001111" & X"000", -- 0x0D2: TST R00
|
||||
"110001" & X"0D7", -- 0x0D3: JZ 0x0D7
|
||||
"000011" & X"080", -- 0x0D4: MOV R00, 0x08
|
||||
"111011" & X"17E", -- 0x0D5: CALL 0x17E
|
||||
"110000" & X"0A8", -- 0x0D6: JMP 0x0A8
|
||||
"111011" & X"292", -- 0x0D7: CALL 0x292
|
||||
"111110" & X"000", -- 0x0D8: RET
|
||||
"000011" & X"010", -- 0x0D9: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x0DA: CALL 0x218
|
||||
"000011" & X"1D1", -- 0x0DB: MOV R01, 0x1D
|
||||
"111011" & X"21D", -- 0x0DC: CALL 0x21D
|
||||
"000011" & X"1D1", -- 0x0DD: MOV R01, 0x1D
|
||||
"111011" & X"286", -- 0x0DE: CALL 0x286
|
||||
"000011" & X"001", -- 0x0DF: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x0E0: CALL 0x289
|
||||
"000011" & X"000", -- 0x0E1: MOV R00, 0x00
|
||||
"000011" & X"001", -- 0x0E2: MOV R01, 0x00
|
||||
"000011" & X"202", -- 0x0E3: MOV R02, 0x20
|
||||
"111011" & X"16A", -- 0x0E4: CALL 0x16A
|
||||
"001010" & X"010", -- 0x0E5: MOVC R00, (0x01)
|
||||
"001101" & X"000", -- 0x0E6: MOVC (0x00), R00
|
||||
"000011" & X"082", -- 0x0E7: MOV R02, 0x08
|
||||
"001010" & X"001", -- 0x0E8: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x0E9: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x0EA: MOV R15, 0x08
|
||||
"000110" & X"001", -- 0x0EB: MOVX (R01), R00
|
||||
"010001" & X"010", -- 0x0EC: INC R00
|
||||
"010001" & X"011", -- 0x0ED: INC R01
|
||||
"010101" & X"01F", -- 0x0EE: DEC R15
|
||||
"110010" & X"0EB", -- 0x0EF: JNZ 0x0EB
|
||||
"101000" & X"070", -- 0x0F0: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x0F1: XOUT (0x01), R00
|
||||
"011001" & X"040", -- 0x0F2: AND R00, 0x04
|
||||
"110010" & X"0F0", -- 0x0F3: JNZ 0x0F0
|
||||
"000011" & X"100", -- 0x0F4: MOV R00, 0x10
|
||||
"100100" & X"070", -- 0x0F5: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x0F6: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x0F7: INC R00
|
||||
"001101" & X"000", -- 0x0F8: MOVC (0x00), R00
|
||||
"010101" & X"022", -- 0x0F9: SUB R02, 0x02
|
||||
"110010" & X"0E8", -- 0x0FA: JNZ 0x0E8
|
||||
"111011" & X"147", -- 0x0FB: CALL 0x147
|
||||
"000011" & X"060", -- 0x0FC: MOV R00, 0x06
|
||||
"100100" & X"070", -- 0x0FD: XOUT (0x07), R00
|
||||
"101000" & X"080", -- 0x0FE: XIN R00, (0x08)
|
||||
"001111" & X"F80", -- 0x0FF: CMP R00, 0xF8
|
||||
"111010" & X"107", -- 0x100: JNE 0x107
|
||||
"101000" & X"090", -- 0x101: XIN R00, (0x09)
|
||||
"001111" & X"FF0", -- 0x102: CMP R00, 0xFF
|
||||
"111010" & X"107", -- 0x103: JNE 0x107
|
||||
"101000" & X"0A0", -- 0x104: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x105: CMP R00, 0xFF
|
||||
"111001" & X"10A", -- 0x106: JEQ 0x10A
|
||||
"000011" & X"080", -- 0x107: MOV R00, 0x08
|
||||
"111011" & X"16E", -- 0x108: CALL 0x16E
|
||||
"110000" & X"0E7", -- 0x109: JMP 0x0E7
|
||||
"111011" & X"18E", -- 0x10A: CALL 0x18E
|
||||
"111011" & X"292", -- 0x10B: CALL 0x292
|
||||
"111110" & X"000", -- 0x10C: RET
|
||||
"000011" & X"010", -- 0x10D: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x10E: CALL 0x218
|
||||
"000011" & X"2B1", -- 0x10F: MOV R01, 0x2B
|
||||
"111011" & X"21D", -- 0x110: CALL 0x21D
|
||||
"000011" & X"2B1", -- 0x111: MOV R01, 0x2B
|
||||
"111011" & X"286", -- 0x112: CALL 0x286
|
||||
"000011" & X"001", -- 0x113: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x114: CALL 0x289
|
||||
"000011" & X"000", -- 0x115: MOV R00, 0x00
|
||||
"000011" & X"001", -- 0x116: MOV R01, 0x00
|
||||
"000011" & X"202", -- 0x117: MOV R02, 0x20
|
||||
"111011" & X"16A", -- 0x118: CALL 0x16A
|
||||
"001010" & X"010", -- 0x119: MOVC R00, (0x01)
|
||||
"001101" & X"000", -- 0x11A: MOVC (0x00), R00
|
||||
"101000" & X"070", -- 0x11B: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x11C: XOUT (0x01), R00
|
||||
"011001" & X"200", -- 0x11D: AND R00, 0x20
|
||||
"110010" & X"122", -- 0x11E: JNZ 0x122
|
||||
"000011" & X"200", -- 0x11F: MOV R00, 0x20
|
||||
"100100" & X"070", -- 0x120: XOUT (0x07), R00
|
||||
"110000" & X"11B", -- 0x121: JMP 0x11B
|
||||
"111011" & X"147", -- 0x122: CALL 0x147
|
||||
"000011" & X"050", -- 0x123: MOV R00, 0x05
|
||||
"100100" & X"070", -- 0x124: XOUT (0x07), R00
|
||||
"000011" & X"083", -- 0x125: MOV R03, 0x08
|
||||
"101000" & X"070", -- 0x126: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x127: XOUT (0x01), R00
|
||||
"011001" & X"200", -- 0x128: AND R00, 0x20
|
||||
"110010" & X"126", -- 0x129: JNZ 0x126
|
||||
"001010" & X"001", -- 0x12A: MOVC R01, (0x00)
|
||||
"000011" & X"800", -- 0x12B: MOV R00, 0x80
|
||||
"000011" & X"08F", -- 0x12C: MOV R15, 0x08
|
||||
"000100" & X"002", -- 0x12D: MOVX R02, (R00)
|
||||
"001110" & X"012", -- 0x12E: CMP R02, R01
|
||||
"111010" & X"15A", -- 0x12F: JNE 0x15A
|
||||
"010001" & X"010", -- 0x130: INC R00
|
||||
"010001" & X"011", -- 0x131: INC R01
|
||||
"010101" & X"01F", -- 0x132: DEC R15
|
||||
"110010" & X"12D", -- 0x133: JNZ 0x12D
|
||||
"000011" & X"200", -- 0x134: MOV R00, 0x20
|
||||
"100100" & X"070", -- 0x135: XOUT (0x07), R00
|
||||
"001010" & X"000", -- 0x136: MOVC R00, (0x00)
|
||||
"010001" & X"010", -- 0x137: INC R00
|
||||
"001101" & X"000", -- 0x138: MOVC (0x00), R00
|
||||
"010101" & X"023", -- 0x139: SUB R03, 0x02
|
||||
"110010" & X"126", -- 0x13A: JNZ 0x126
|
||||
"101000" & X"080", -- 0x13B: XIN R00, (0x08)
|
||||
"001111" & X"F80", -- 0x13C: CMP R00, 0xF8
|
||||
"111010" & X"144", -- 0x13D: JNE 0x144
|
||||
"101000" & X"090", -- 0x13E: XIN R00, (0x09)
|
||||
"001111" & X"FF0", -- 0x13F: CMP R00, 0xFF
|
||||
"111010" & X"144", -- 0x140: JNE 0x144
|
||||
"101000" & X"0A0", -- 0x141: XIN R00, (0x0A)
|
||||
"001111" & X"FF0", -- 0x142: CMP R00, 0xFF
|
||||
"111001" & X"14E", -- 0x143: JEQ 0x14E
|
||||
"000011" & X"080", -- 0x144: MOV R00, 0x08
|
||||
"111011" & X"16E", -- 0x145: CALL 0x16E
|
||||
"110000" & X"122", -- 0x146: JMP 0x122
|
||||
"111100" & X"000", -- 0x147: PUSH R00
|
||||
"101000" & X"070", -- 0x148: XIN R00, (0x07)
|
||||
"100100" & X"010", -- 0x149: XOUT (0x01), R00
|
||||
"011001" & X"010", -- 0x14A: AND R00, 0x01
|
||||
"110010" & X"148", -- 0x14B: JNZ 0x148
|
||||
"111101" & X"000", -- 0x14C: POP R00
|
||||
"111110" & X"000", -- 0x14D: RET
|
||||
"000011" & X"010", -- 0x14E: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x14F: CALL 0x218
|
||||
"000011" & X"481", -- 0x150: MOV R01, 0x48
|
||||
"111011" & X"21D", -- 0x151: CALL 0x21D
|
||||
"000011" & X"C00", -- 0x152: MOV R00, 0xC0
|
||||
"111011" & X"218", -- 0x153: CALL 0x218
|
||||
"111011" & X"199", -- 0x154: CALL 0x199
|
||||
"000011" & X"481", -- 0x155: MOV R01, 0x48
|
||||
"111011" & X"286", -- 0x156: CALL 0x286
|
||||
"000011" & X"001", -- 0x157: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x158: CALL 0x289
|
||||
"110000" & X"168", -- 0x159: JMP 0x168
|
||||
"000011" & X"010", -- 0x15A: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x15B: CALL 0x218
|
||||
"000011" & X"521", -- 0x15C: MOV R01, 0x52
|
||||
"111011" & X"21D", -- 0x15D: CALL 0x21D
|
||||
"111011" & X"199", -- 0x15E: CALL 0x199
|
||||
"111011" & X"1B1", -- 0x15F: CALL 0x1B1
|
||||
"000011" & X"521", -- 0x160: MOV R01, 0x52
|
||||
"111011" & X"286", -- 0x161: CALL 0x286
|
||||
"000011" & X"001", -- 0x162: MOV R01, 0x00
|
||||
"111011" & X"289", -- 0x163: CALL 0x289
|
||||
"101000" & X"040", -- 0x164: XIN R00, (0x04)
|
||||
"011011" & X"100", -- 0x165: OR R00, 0x10
|
||||
"100100" & X"040", -- 0x166: XOUT (0x04), R00
|
||||
"110000" & X"168", -- 0x167: JMP 0x168
|
||||
"111011" & X"292", -- 0x168: CALL 0x292
|
||||
"111110" & X"000", -- 0x169: RET
|
||||
"100100" & X"080", -- 0x16A: XOUT (0x08), R00
|
||||
"100100" & X"091", -- 0x16B: XOUT (0x09), R01
|
||||
"100100" & X"0A2", -- 0x16C: XOUT (0x0A), R02
|
||||
"111110" & X"000", -- 0x16D: RET
|
||||
"111100" & X"001", -- 0x16E: PUSH R01
|
||||
"111100" & X"002", -- 0x16F: PUSH R02
|
||||
"111100" & X"003", -- 0x170: PUSH R03
|
||||
"101000" & X"081", -- 0x171: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x172: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x173: XIN R03, (0x0A)
|
||||
"010000" & X"001", -- 0x174: ADD R01, R00
|
||||
"010011" & X"002", -- 0x175: ADDC R02, 0x00
|
||||
"010011" & X"003", -- 0x176: ADDC R03, 0x00
|
||||
"100100" & X"081", -- 0x177: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x178: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x179: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x17A: POP R03
|
||||
"111101" & X"002", -- 0x17B: POP R02
|
||||
"111101" & X"001", -- 0x17C: POP R01
|
||||
"111110" & X"000", -- 0x17D: RET
|
||||
"111100" & X"001", -- 0x17E: PUSH R01
|
||||
"111100" & X"002", -- 0x17F: PUSH R02
|
||||
"111100" & X"003", -- 0x180: PUSH R03
|
||||
"101000" & X"081", -- 0x181: XIN R01, (0x08)
|
||||
"101000" & X"092", -- 0x182: XIN R02, (0x09)
|
||||
"101000" & X"0A3", -- 0x183: XIN R03, (0x0A)
|
||||
"010100" & X"001", -- 0x184: SUB R01, R00
|
||||
"010111" & X"002", -- 0x185: SUBC R02, 0x00
|
||||
"010111" & X"003", -- 0x186: SUBC R03, 0x00
|
||||
"100100" & X"081", -- 0x187: XOUT (0x08), R01
|
||||
"100100" & X"092", -- 0x188: XOUT (0x09), R02
|
||||
"100100" & X"0A3", -- 0x189: XOUT (0x0A), R03
|
||||
"111101" & X"003", -- 0x18A: POP R03
|
||||
"111101" & X"002", -- 0x18B: POP R02
|
||||
"111101" & X"001", -- 0x18C: POP R01
|
||||
"111110" & X"000", -- 0x18D: RET
|
||||
"000011" & X"C00", -- 0x18E: MOV R00, 0xC0
|
||||
"111011" & X"218", -- 0x18F: CALL 0x218
|
||||
"111011" & X"199", -- 0x190: CALL 0x199
|
||||
"111110" & X"000", -- 0x191: RET
|
||||
"111100" & X"001", -- 0x192: PUSH R01
|
||||
"111011" & X"1F4", -- 0x193: CALL 0x1F4
|
||||
"111011" & X"22F", -- 0x194: CALL 0x22F
|
||||
"000010" & X"010", -- 0x195: MOV R00, R01
|
||||
"111011" & X"22F", -- 0x196: CALL 0x22F
|
||||
"111101" & X"001", -- 0x197: POP R01
|
||||
"111110" & X"000", -- 0x198: RET
|
||||
"111100" & X"000", -- 0x199: PUSH R00
|
||||
"101000" & X"0A0", -- 0x19A: XIN R00, (0x0A)
|
||||
"111011" & X"192", -- 0x19B: CALL 0x192
|
||||
"101000" & X"090", -- 0x19C: XIN R00, (0x09)
|
||||
"111011" & X"192", -- 0x19D: CALL 0x192
|
||||
"101000" & X"080", -- 0x19E: XIN R00, (0x08)
|
||||
"111011" & X"192", -- 0x19F: CALL 0x192
|
||||
"111101" & X"000", -- 0x1A0: POP R00
|
||||
"111110" & X"000", -- 0x1A1: RET
|
||||
"111100" & X"000", -- 0x1A2: PUSH R00
|
||||
"010001" & X"031", -- 0x1A3: ADD R01, 0x03
|
||||
"001001" & X"010", -- 0x1A4: MOVC R00, (R01)
|
||||
"111011" & X"192", -- 0x1A5: CALL 0x192
|
||||
"010101" & X"011", -- 0x1A6: DEC R01
|
||||
"001001" & X"010", -- 0x1A7: MOVC R00, (R01)
|
||||
"111011" & X"192", -- 0x1A8: CALL 0x192
|
||||
"010101" & X"011", -- 0x1A9: DEC R01
|
||||
"001001" & X"010", -- 0x1AA: MOVC R00, (R01)
|
||||
"111011" & X"192", -- 0x1AB: CALL 0x192
|
||||
"010101" & X"011", -- 0x1AC: DEC R01
|
||||
"001001" & X"010", -- 0x1AD: MOVC R00, (R01)
|
||||
"111011" & X"192", -- 0x1AE: CALL 0x192
|
||||
"111101" & X"000", -- 0x1AF: POP R00
|
||||
"111110" & X"000", -- 0x1B0: RET
|
||||
"111100" & X"000", -- 0x1B1: PUSH R00
|
||||
"000011" & X"C00", -- 0x1B2: MOV R00, 0xC0
|
||||
"111011" & X"218", -- 0x1B3: CALL 0x218
|
||||
"000101" & X"870", -- 0x1B4: MOVX R00, (0x87)
|
||||
"111011" & X"192", -- 0x1B5: CALL 0x192
|
||||
"000101" & X"860", -- 0x1B6: MOVX R00, (0x86)
|
||||
"111011" & X"192", -- 0x1B7: CALL 0x192
|
||||
"000101" & X"850", -- 0x1B8: MOVX R00, (0x85)
|
||||
"111011" & X"192", -- 0x1B9: CALL 0x192
|
||||
"000101" & X"840", -- 0x1BA: MOVX R00, (0x84)
|
||||
"111011" & X"192", -- 0x1BB: CALL 0x192
|
||||
"000101" & X"830", -- 0x1BC: MOVX R00, (0x83)
|
||||
"111011" & X"192", -- 0x1BD: CALL 0x192
|
||||
"000101" & X"820", -- 0x1BE: MOVX R00, (0x82)
|
||||
"111011" & X"192", -- 0x1BF: CALL 0x192
|
||||
"000101" & X"810", -- 0x1C0: MOVX R00, (0x81)
|
||||
"111011" & X"192", -- 0x1C1: CALL 0x192
|
||||
"000101" & X"800", -- 0x1C2: MOVX R00, (0x80)
|
||||
"111011" & X"192", -- 0x1C3: CALL 0x192
|
||||
"111101" & X"000", -- 0x1C4: POP R00
|
||||
"111110" & X"000", -- 0x1C5: RET
|
||||
"111100" & X"000", -- 0x1C6: PUSH R00
|
||||
"000011" & X"0D0", -- 0x1C7: MOV R00, 0x0D
|
||||
"100100" & X"130", -- 0x1C8: XOUT (0x13), R00
|
||||
"000011" & X"1E0", -- 0x1C9: MOV R00, 0x1E
|
||||
"001101" & X"5E0", -- 0x1CA: MOVC (0x5E), R00
|
||||
"001101" & X"5F0", -- 0x1CB: MOVC (0x5F), R00
|
||||
"000011" & X"E80", -- 0x1CC: MOV R00, 0xE8
|
||||
"001101" & X"600", -- 0x1CD: MOVC (0x60), R00
|
||||
"000011" & X"030", -- 0x1CE: MOV R00, 0x03
|
||||
"001101" & X"610", -- 0x1CF: MOVC (0x61), R00
|
||||
"111101" & X"000", -- 0x1D0: POP R00
|
||||
"111110" & X"000", -- 0x1D1: RET
|
||||
"111100" & X"001", -- 0x1D2: PUSH R01
|
||||
"111100" & X"002", -- 0x1D3: PUSH R02
|
||||
"111100" & X"003", -- 0x1D4: PUSH R03
|
||||
"001010" & X"602", -- 0x1D5: MOVC R02, (0x60)
|
||||
"001010" & X"613", -- 0x1D6: MOVC R03, (0x61)
|
||||
"001010" & X"5E1", -- 0x1D7: MOVC R01, (0x5E)
|
||||
"001010" & X"5F0", -- 0x1D8: MOVC R00, (0x5F)
|
||||
"001110" & X"010", -- 0x1D9: CMP R00, R01
|
||||
"111001" & X"1E6", -- 0x1DA: JEQ 0x1E6
|
||||
"001001" & X"010", -- 0x1DB: MOVC R00, (R01)
|
||||
"010001" & X"011", -- 0x1DC: INC R01
|
||||
"001111" & X"5E1", -- 0x1DD: CMP R01, 0x5E
|
||||
"111010" & X"1E0", -- 0x1DE: JNE 0x1E0
|
||||
"000011" & X"1E1", -- 0x1DF: MOV R01, 0x1E
|
||||
"001101" & X"5E1", -- 0x1E0: MOVC (0x5E), R01
|
||||
"010101" & X"000", -- 0x1E1: CLRC
|
||||
"111101" & X"003", -- 0x1E2: POP R03
|
||||
"111101" & X"002", -- 0x1E3: POP R02
|
||||
"111101" & X"001", -- 0x1E4: POP R01
|
||||
"111110" & X"000", -- 0x1E5: RET
|
||||
"111011" & X"2A7", -- 0x1E6: CALL 0x2A7
|
||||
"010101" & X"012", -- 0x1E7: DEC R02
|
||||
"010111" & X"003", -- 0x1E8: SUBC R03, 0x00
|
||||
"110010" & X"1D8", -- 0x1E9: JNZ 0x1D8
|
||||
"001111" & X"002", -- 0x1EA: TST R02
|
||||
"110010" & X"1D8", -- 0x1EB: JNZ 0x1D8
|
||||
"101011" & X"000", -- 0x1EC: SETC
|
||||
"110000" & X"1E2", -- 0x1ED: JMP 0x1E2
|
||||
"011001" & X"0F0", -- 0x1EE: AND R00, 0x0F
|
||||
"001111" & X"0A0", -- 0x1EF: CMP R00, 0x0A
|
||||
"110101" & X"1F2", -- 0x1F0: JLT 0x1F2
|
||||
"010001" & X"070", -- 0x1F1: ADD R00, 0x07
|
||||
"010001" & X"300", -- 0x1F2: ADD R00, 0x30
|
||||
"111110" & X"000", -- 0x1F3: RET
|
||||
"111100" & X"000", -- 0x1F4: PUSH R00
|
||||
"111011" & X"1EE", -- 0x1F5: CALL 0x1EE
|
||||
"000010" & X"001", -- 0x1F6: MOV R01, R00
|
||||
"111101" & X"000", -- 0x1F7: POP R00
|
||||
"101010" & X"000", -- 0x1F8: SWAP R00
|
||||
"111011" & X"1EE", -- 0x1F9: CALL 0x1EE
|
||||
"111110" & X"000", -- 0x1FA: RET
|
||||
"000011" & X"002", -- 0x1FB: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x1FC: MOV R00, 0x03
|
||||
"111011" & X"247", -- 0x1FD: CALL 0x247
|
||||
"111011" & X"2A0", -- 0x1FE: CALL 0x2A0
|
||||
"000011" & X"002", -- 0x1FF: MOV R02, 0x00
|
||||
"000011" & X"030", -- 0x200: MOV R00, 0x03
|
||||
"111011" & X"247", -- 0x201: CALL 0x247
|
||||
"111011" & X"2A0", -- 0x202: CALL 0x2A0
|
||||
"000011" & X"002", -- 0x203: MOV R02, 0x00
|
||||
"000011" & X"020", -- 0x204: MOV R00, 0x02
|
||||
"111011" & X"247", -- 0x205: CALL 0x247
|
||||
"111011" & X"2A7", -- 0x206: CALL 0x2A7
|
||||
"000011" & X"280", -- 0x207: MOV R00, 0x28
|
||||
"111011" & X"218", -- 0x208: CALL 0x218
|
||||
"000011" & X"0C0", -- 0x209: MOV R00, 0x0C
|
||||
"111011" & X"218", -- 0x20A: CALL 0x218
|
||||
"000011" & X"060", -- 0x20B: MOV R00, 0x06
|
||||
"111011" & X"218", -- 0x20C: CALL 0x218
|
||||
"000011" & X"010", -- 0x20D: MOV R00, 0x01
|
||||
"111011" & X"218", -- 0x20E: CALL 0x218
|
||||
"111110" & X"000", -- 0x20F: RET
|
||||
"111100" & X"000", -- 0x210: PUSH R00
|
||||
"111011" & X"23B", -- 0x211: CALL 0x23B
|
||||
"011001" & X"800", -- 0x212: AND R00, 0x80
|
||||
"110001" & X"216", -- 0x213: JZ 0x216
|
||||
"111011" & X"2BE", -- 0x214: CALL 0x2BE
|
||||
"110000" & X"211", -- 0x215: JMP 0x211
|
||||
"111101" & X"000", -- 0x216: POP R00
|
||||
"111110" & X"000", -- 0x217: RET
|
||||
"111100" & X"002", -- 0x218: PUSH R02
|
||||
"000011" & X"002", -- 0x219: MOV R02, 0x00
|
||||
"111011" & X"234", -- 0x21A: CALL 0x234
|
||||
"111101" & X"002", -- 0x21B: POP R02
|
||||
"111110" & X"000", -- 0x21C: RET
|
||||
"111100" & X"000", -- 0x21D: PUSH R00
|
||||
"000100" & X"010", -- 0x21E: MOVX R00, (R01)
|
||||
"010001" & X"011", -- 0x21F: INC R01
|
||||
"001111" & X"000", -- 0x220: TST R00
|
||||
"110001" & X"224", -- 0x221: JZ 0x224
|
||||
"111011" & X"22F", -- 0x222: CALL 0x22F
|
||||
"110000" & X"21E", -- 0x223: JMP 0x21E
|
||||
"111101" & X"000", -- 0x224: POP R00
|
||||
"111110" & X"000", -- 0x225: RET
|
||||
"111100" & X"000", -- 0x226: PUSH R00
|
||||
"001001" & X"010", -- 0x227: MOVC R00, (R01)
|
||||
"010001" & X"011", -- 0x228: INC R01
|
||||
"001111" & X"000", -- 0x229: TST R00
|
||||
"110001" & X"22D", -- 0x22A: JZ 0x22D
|
||||
"111011" & X"22F", -- 0x22B: CALL 0x22F
|
||||
"110000" & X"227", -- 0x22C: JMP 0x227
|
||||
"111101" & X"000", -- 0x22D: POP R00
|
||||
"111110" & X"000", -- 0x22E: RET
|
||||
"111100" & X"002", -- 0x22F: PUSH R02
|
||||
"000011" & X"402", -- 0x230: MOV R02, 0x40
|
||||
"111011" & X"234", -- 0x231: CALL 0x234
|
||||
"111101" & X"002", -- 0x232: POP R02
|
||||
"111110" & X"000", -- 0x233: RET
|
||||
"111011" & X"210", -- 0x234: CALL 0x210
|
||||
"111100" & X"000", -- 0x235: PUSH R00
|
||||
"101010" & X"000", -- 0x236: SWAP R00
|
||||
"111011" & X"247", -- 0x237: CALL 0x247
|
||||
"111101" & X"000", -- 0x238: POP R00
|
||||
"111011" & X"247", -- 0x239: CALL 0x247
|
||||
"111110" & X"000", -- 0x23A: RET
|
||||
"111100" & X"002", -- 0x23B: PUSH R02
|
||||
"000011" & X"002", -- 0x23C: MOV R02, 0x00
|
||||
"111011" & X"240", -- 0x23D: CALL 0x240
|
||||
"111101" & X"002", -- 0x23E: POP R02
|
||||
"111110" & X"000", -- 0x23F: RET
|
||||
"111011" & X"25A", -- 0x240: CALL 0x25A
|
||||
"101010" & X"000", -- 0x241: SWAP R00
|
||||
"111100" & X"000", -- 0x242: PUSH R00
|
||||
"111011" & X"25A", -- 0x243: CALL 0x25A
|
||||
"111101" & X"002", -- 0x244: POP R02
|
||||
"011010" & X"020", -- 0x245: OR R00, R02
|
||||
"111110" & X"000", -- 0x246: RET
|
||||
"111100" & X"001", -- 0x247: PUSH R01
|
||||
"011001" & X"0F0", -- 0x248: AND R00, 0x0F
|
||||
"000010" & X"001", -- 0x249: MOV R01, R00
|
||||
"011010" & X"021", -- 0x24A: OR R01, R02
|
||||
"100100" & X"031", -- 0x24B: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x24C: CALL 0x2BE
|
||||
"000010" & X"001", -- 0x24D: MOV R01, R00
|
||||
"011010" & X"021", -- 0x24E: OR R01, R02
|
||||
"011011" & X"801", -- 0x24F: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x250: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x251: CALL 0x2BE
|
||||
"000010" & X"001", -- 0x252: MOV R01, R00
|
||||
"011010" & X"021", -- 0x253: OR R01, R02
|
||||
"100100" & X"031", -- 0x254: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x255: CALL 0x2BE
|
||||
"011011" & X"201", -- 0x256: OR R01, 0x20
|
||||
"100100" & X"031", -- 0x257: XOUT (0x03), R01
|
||||
"111101" & X"001", -- 0x258: POP R01
|
||||
"111110" & X"000", -- 0x259: RET
|
||||
"111100" & X"001", -- 0x25A: PUSH R01
|
||||
"000011" & X"201", -- 0x25B: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x25C: OR R01, R02
|
||||
"100100" & X"031", -- 0x25D: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x25E: CALL 0x2BE
|
||||
"000011" & X"201", -- 0x25F: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x260: OR R01, R02
|
||||
"011011" & X"801", -- 0x261: OR R01, 0x80
|
||||
"100100" & X"031", -- 0x262: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x263: CALL 0x2BE
|
||||
"101000" & X"030", -- 0x264: XIN R00, (0x03)
|
||||
"011001" & X"0F0", -- 0x265: AND R00, 0x0F
|
||||
"000011" & X"201", -- 0x266: MOV R01, 0x20
|
||||
"011010" & X"021", -- 0x267: OR R01, R02
|
||||
"100100" & X"031", -- 0x268: XOUT (0x03), R01
|
||||
"111011" & X"2BE", -- 0x269: CALL 0x2BE
|
||||
"111101" & X"001", -- 0x26A: POP R01
|
||||
"111110" & X"000", -- 0x26B: RET
|
||||
"111100" & X"000", -- 0x26C: PUSH R00
|
||||
"000011" & X"020", -- 0x26D: MOV R00, 0x02
|
||||
"100100" & X"0E0", -- 0x26E: XOUT (0x0E), R00
|
||||
"111101" & X"000", -- 0x26F: POP R00
|
||||
"111110" & X"000", -- 0x270: RET
|
||||
"111100" & X"000", -- 0x271: PUSH R00
|
||||
"000011" & X"010", -- 0x272: MOV R00, 0x01
|
||||
"100100" & X"0E0", -- 0x273: XOUT (0x0E), R00
|
||||
"111101" & X"000", -- 0x274: POP R00
|
||||
"111110" & X"000", -- 0x275: RET
|
||||
"111011" & X"28C", -- 0x276: CALL 0x28C
|
||||
"100100" & X"0C1", -- 0x277: XOUT (0x0C), R01
|
||||
"100100" & X"0B0", -- 0x278: XOUT (0x0B), R00
|
||||
"111110" & X"000", -- 0x279: RET
|
||||
"111011" & X"28C", -- 0x27A: CALL 0x28C
|
||||
"100100" & X"0D0", -- 0x27B: XOUT (0x0D), R00
|
||||
"111110" & X"000", -- 0x27C: RET
|
||||
"111100" & X"000", -- 0x27D: PUSH R00
|
||||
"000100" & X"010", -- 0x27E: MOVX R00, (R01)
|
||||
"010001" & X"011", -- 0x27F: INC R01
|
||||
"001111" & X"000", -- 0x280: TST R00
|
||||
"110001" & X"284", -- 0x281: JZ 0x284
|
||||
"111011" & X"27A", -- 0x282: CALL 0x27A
|
||||
"110000" & X"27E", -- 0x283: JMP 0x27E
|
||||
"111101" & X"000", -- 0x284: POP R00
|
||||
"111110" & X"000", -- 0x285: RET
|
||||
"111011" & X"26C", -- 0x286: CALL 0x26C
|
||||
"111011" & X"27D", -- 0x287: CALL 0x27D
|
||||
"111110" & X"000", -- 0x288: RET
|
||||
"111011" & X"27D", -- 0x289: CALL 0x27D
|
||||
"111011" & X"26C", -- 0x28A: CALL 0x26C
|
||||
"111110" & X"000", -- 0x28B: RET
|
||||
"111100" & X"000", -- 0x28C: PUSH R00
|
||||
"101000" & X"0E0", -- 0x28D: XIN R00, (0x0E)
|
||||
"011001" & X"020", -- 0x28E: AND R00, 0x02
|
||||
"110001" & X"28D", -- 0x28F: JZ 0x28D
|
||||
"111101" & X"000", -- 0x290: POP R00
|
||||
"111110" & X"000", -- 0x291: RET
|
||||
"111100" & X"00F", -- 0x292: PUSH R15
|
||||
"000011" & X"0AF", -- 0x293: MOV R15, 0x0A
|
||||
"111011" & X"299", -- 0x294: CALL 0x299
|
||||
"010101" & X"01F", -- 0x295: DEC R15
|
||||
"110010" & X"294", -- 0x296: JNZ 0x294
|
||||
"111101" & X"00F", -- 0x297: POP R15
|
||||
"111110" & X"000", -- 0x298: RET
|
||||
"111100" & X"00F", -- 0x299: PUSH R15
|
||||
"000011" & X"0AF", -- 0x29A: MOV R15, 0x0A
|
||||
"111011" & X"2A0", -- 0x29B: CALL 0x2A0
|
||||
"010101" & X"01F", -- 0x29C: DEC R15
|
||||
"110010" & X"29B", -- 0x29D: JNZ 0x29B
|
||||
"111101" & X"00F", -- 0x29E: POP R15
|
||||
"111110" & X"000", -- 0x29F: RET
|
||||
"111100" & X"00F", -- 0x2A0: PUSH R15
|
||||
"000011" & X"0AF", -- 0x2A1: MOV R15, 0x0A
|
||||
"111011" & X"2A7", -- 0x2A2: CALL 0x2A7
|
||||
"010101" & X"01F", -- 0x2A3: DEC R15
|
||||
"110010" & X"2A2", -- 0x2A4: JNZ 0x2A2
|
||||
"111101" & X"00F", -- 0x2A5: POP R15
|
||||
"111110" & X"000", -- 0x2A6: RET
|
||||
"111100" & X"00F", -- 0x2A7: PUSH R15
|
||||
"000011" & X"0AF", -- 0x2A8: MOV R15, 0x0A
|
||||
"111011" & X"2AE", -- 0x2A9: CALL 0x2AE
|
||||
"010101" & X"01F", -- 0x2AA: DEC R15
|
||||
"110010" & X"2A9", -- 0x2AB: JNZ 0x2A9
|
||||
"111101" & X"00F", -- 0x2AC: POP R15
|
||||
"111110" & X"000", -- 0x2AD: RET
|
||||
"111100" & X"00F", -- 0x2AE: PUSH R15
|
||||
"000011" & X"0AF", -- 0x2AF: MOV R15, 0x0A
|
||||
"111011" & X"2B5", -- 0x2B0: CALL 0x2B5
|
||||
"010101" & X"01F", -- 0x2B1: DEC R15
|
||||
"110010" & X"2B0", -- 0x2B2: JNZ 0x2B0
|
||||
"111101" & X"00F", -- 0x2B3: POP R15
|
||||
"111110" & X"000", -- 0x2B4: RET
|
||||
"111100" & X"00F", -- 0x2B5: PUSH R15
|
||||
"000011" & X"63F", -- 0x2B6: MOV R15, 0x63
|
||||
"000000" & X"000", -- 0x2B7: NOP
|
||||
"000000" & X"000", -- 0x2B8: NOP
|
||||
"000000" & X"000", -- 0x2B9: NOP
|
||||
"010101" & X"01F", -- 0x2BA: DEC R15
|
||||
"110010" & X"2B7", -- 0x2BB: JNZ 0x2B7
|
||||
"111101" & X"00F", -- 0x2BC: POP R15
|
||||
"111110" & X"000", -- 0x2BD: RET
|
||||
"111100" & X"00F", -- 0x2BE: PUSH R15
|
||||
"000011" & X"09F", -- 0x2BF: MOV R15, 0x09
|
||||
"000000" & X"000", -- 0x2C0: NOP
|
||||
"000000" & X"000", -- 0x2C1: NOP
|
||||
"000000" & X"000", -- 0x2C2: NOP
|
||||
"010101" & X"01F", -- 0x2C3: DEC R15
|
||||
"110010" & X"2C0", -- 0x2C4: JNZ 0x2C0
|
||||
"111101" & X"00F", -- 0x2C5: POP R15
|
||||
"111110" & X"000", -- 0x2C6: RET
|
||||
"111100" & X"001", -- 0x2C7: PUSH R01
|
||||
"101000" & X"061", -- 0x2C8: XIN R01, (0x06)
|
||||
"011001" & X"021", -- 0x2C9: AND R01, 0x02
|
||||
"110010" & X"2C8", -- 0x2CA: JNZ 0x2C8
|
||||
"100100" & X"020", -- 0x2CB: XOUT (0x02), R00
|
||||
"111101" & X"001", -- 0x2CC: POP R01
|
||||
"111110" & X"000", -- 0x2CD: RET
|
||||
"111100" & X"001", -- 0x2CE: PUSH R01
|
||||
"101000" & X"061", -- 0x2CF: XIN R01, (0x06)
|
||||
"011001" & X"101", -- 0x2D0: AND R01, 0x10
|
||||
"110001" & X"2CF", -- 0x2D1: JZ 0x2CF
|
||||
"101000" & X"020", -- 0x2D2: XIN R00, (0x02)
|
||||
"111101" & X"001", -- 0x2D3: POP R01
|
||||
"111110" & X"000" -- 0x2D4: RET
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= imem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end vga_test;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,317 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: The ROM file for use in your VHDL design
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE vga_test OF xrom IS
|
||||
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
|
||||
-- Assembled from vga_test.jsm
|
||||
constant xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"52", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"61", -- 0x3B
|
||||
X"64", -- 0x3C
|
||||
X"69", -- 0x3D
|
||||
X"6E", -- 0x3E
|
||||
X"67", -- 0x3F
|
||||
X"20", -- 0x40
|
||||
X"42", -- 0x41
|
||||
X"69", -- 0x42
|
||||
X"74", -- 0x43
|
||||
X"6D", -- 0x44
|
||||
X"61", -- 0x45
|
||||
X"70", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"56", -- 0x48
|
||||
X"65", -- 0x49
|
||||
X"72", -- 0x4A
|
||||
X"69", -- 0x4B
|
||||
X"66", -- 0x4C
|
||||
X"79", -- 0x4D
|
||||
X"20", -- 0x4E
|
||||
X"4F", -- 0x4F
|
||||
X"4B", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"46", -- 0x52
|
||||
X"61", -- 0x53
|
||||
X"69", -- 0x54
|
||||
X"6C", -- 0x55
|
||||
X"65", -- 0x56
|
||||
X"64", -- 0x57
|
||||
X"20", -- 0x58
|
||||
X"61", -- 0x59
|
||||
X"74", -- 0x5A
|
||||
X"20", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"2E", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
begin
|
||||
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end vga_test;
|
||||
|
||||
@@ -0,0 +1,413 @@
|
||||
-------------------------------------------------------------------------
|
||||
-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
|
||||
-- This file: loadable ROM
|
||||
--
|
||||
-- Copyright (C) 2007 J. Ahrensfeld
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
-- For questions and ideas, please contact the author at jens@jayfield.org
|
||||
--
|
||||
--------------------------------------------------------------------------
|
||||
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library UNISIM;
|
||||
use UNISIM.VComponents.all;
|
||||
|
||||
library work;
|
||||
use work.cpu_pkg.all;
|
||||
|
||||
ENTITY xrom IS
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
ce : in STD_LOGIC;
|
||||
addr : in dmem_addr_t;
|
||||
dout : out dmem_data_t
|
||||
);
|
||||
|
||||
END xrom;
|
||||
|
||||
ARCHITECTURE loadable OF xrom IS
|
||||
|
||||
-- JASM_ROM_INSERT_HERE
|
||||
|
||||
-- Assembled from vga_test.jsm
|
||||
type xmem_rom_t is array (0 to 255) of dmem_data_t;
|
||||
signal xmem_rom : xmem_rom_t :=
|
||||
(
|
||||
X"0D", -- 0x00
|
||||
X"0A", -- 0x01
|
||||
X"00", -- 0x02
|
||||
X"53", -- 0x03
|
||||
X"44", -- 0x04
|
||||
X"52", -- 0x05
|
||||
X"41", -- 0x06
|
||||
X"4D", -- 0x07
|
||||
X"20", -- 0x08
|
||||
X"54", -- 0x09
|
||||
X"65", -- 0x0A
|
||||
X"73", -- 0x0B
|
||||
X"74", -- 0x0C
|
||||
X"00", -- 0x0D
|
||||
X"43", -- 0x0E
|
||||
X"6C", -- 0x0F
|
||||
X"65", -- 0x10
|
||||
X"61", -- 0x11
|
||||
X"72", -- 0x12
|
||||
X"69", -- 0x13
|
||||
X"6E", -- 0x14
|
||||
X"67", -- 0x15
|
||||
X"20", -- 0x16
|
||||
X"53", -- 0x17
|
||||
X"44", -- 0x18
|
||||
X"52", -- 0x19
|
||||
X"41", -- 0x1A
|
||||
X"4D", -- 0x1B
|
||||
X"00", -- 0x1C
|
||||
X"57", -- 0x1D
|
||||
X"72", -- 0x1E
|
||||
X"69", -- 0x1F
|
||||
X"74", -- 0x20
|
||||
X"69", -- 0x21
|
||||
X"6E", -- 0x22
|
||||
X"67", -- 0x23
|
||||
X"20", -- 0x24
|
||||
X"53", -- 0x25
|
||||
X"44", -- 0x26
|
||||
X"52", -- 0x27
|
||||
X"41", -- 0x28
|
||||
X"4D", -- 0x29
|
||||
X"00", -- 0x2A
|
||||
X"52", -- 0x2B
|
||||
X"65", -- 0x2C
|
||||
X"61", -- 0x2D
|
||||
X"64", -- 0x2E
|
||||
X"69", -- 0x2F
|
||||
X"6E", -- 0x30
|
||||
X"67", -- 0x31
|
||||
X"20", -- 0x32
|
||||
X"53", -- 0x33
|
||||
X"44", -- 0x34
|
||||
X"52", -- 0x35
|
||||
X"41", -- 0x36
|
||||
X"4D", -- 0x37
|
||||
X"00", -- 0x38
|
||||
X"52", -- 0x39
|
||||
X"65", -- 0x3A
|
||||
X"61", -- 0x3B
|
||||
X"64", -- 0x3C
|
||||
X"69", -- 0x3D
|
||||
X"6E", -- 0x3E
|
||||
X"67", -- 0x3F
|
||||
X"20", -- 0x40
|
||||
X"42", -- 0x41
|
||||
X"69", -- 0x42
|
||||
X"74", -- 0x43
|
||||
X"6D", -- 0x44
|
||||
X"61", -- 0x45
|
||||
X"70", -- 0x46
|
||||
X"00", -- 0x47
|
||||
X"56", -- 0x48
|
||||
X"65", -- 0x49
|
||||
X"72", -- 0x4A
|
||||
X"69", -- 0x4B
|
||||
X"66", -- 0x4C
|
||||
X"79", -- 0x4D
|
||||
X"20", -- 0x4E
|
||||
X"4F", -- 0x4F
|
||||
X"4B", -- 0x50
|
||||
X"00", -- 0x51
|
||||
X"46", -- 0x52
|
||||
X"61", -- 0x53
|
||||
X"69", -- 0x54
|
||||
X"6C", -- 0x55
|
||||
X"65", -- 0x56
|
||||
X"64", -- 0x57
|
||||
X"20", -- 0x58
|
||||
X"61", -- 0x59
|
||||
X"74", -- 0x5A
|
||||
X"20", -- 0x5B
|
||||
X"00", -- 0x5C
|
||||
X"2E", -- 0x5D
|
||||
X"00", -- 0x5E
|
||||
X"00", -- 0x5F
|
||||
X"00", -- 0x60
|
||||
X"00", -- 0x61
|
||||
X"00", -- 0x62
|
||||
X"00", -- 0x63
|
||||
X"00", -- 0x64
|
||||
X"00", -- 0x65
|
||||
X"00", -- 0x66
|
||||
X"00", -- 0x67
|
||||
X"00", -- 0x68
|
||||
X"00", -- 0x69
|
||||
X"00", -- 0x6A
|
||||
X"00", -- 0x6B
|
||||
X"00", -- 0x6C
|
||||
X"00", -- 0x6D
|
||||
X"00", -- 0x6E
|
||||
X"00", -- 0x6F
|
||||
X"00", -- 0x70
|
||||
X"00", -- 0x71
|
||||
X"00", -- 0x72
|
||||
X"00", -- 0x73
|
||||
X"00", -- 0x74
|
||||
X"00", -- 0x75
|
||||
X"00", -- 0x76
|
||||
X"00", -- 0x77
|
||||
X"00", -- 0x78
|
||||
X"00", -- 0x79
|
||||
X"00", -- 0x7A
|
||||
X"00", -- 0x7B
|
||||
X"00", -- 0x7C
|
||||
X"00", -- 0x7D
|
||||
X"00", -- 0x7E
|
||||
X"00", -- 0x7F
|
||||
X"00", -- 0x80
|
||||
X"00", -- 0x81
|
||||
X"00", -- 0x82
|
||||
X"00", -- 0x83
|
||||
X"00", -- 0x84
|
||||
X"00", -- 0x85
|
||||
X"00", -- 0x86
|
||||
X"00", -- 0x87
|
||||
X"00", -- 0x88
|
||||
X"00", -- 0x89
|
||||
X"00", -- 0x8A
|
||||
X"00", -- 0x8B
|
||||
X"00", -- 0x8C
|
||||
X"00", -- 0x8D
|
||||
X"00", -- 0x8E
|
||||
X"00", -- 0x8F
|
||||
X"00", -- 0x90
|
||||
X"00", -- 0x91
|
||||
X"00", -- 0x92
|
||||
X"00", -- 0x93
|
||||
X"00", -- 0x94
|
||||
X"00", -- 0x95
|
||||
X"00", -- 0x96
|
||||
X"00", -- 0x97
|
||||
X"00", -- 0x98
|
||||
X"00", -- 0x99
|
||||
X"00", -- 0x9A
|
||||
X"00", -- 0x9B
|
||||
X"00", -- 0x9C
|
||||
X"00", -- 0x9D
|
||||
X"00", -- 0x9E
|
||||
X"00", -- 0x9F
|
||||
X"00", -- 0xA0
|
||||
X"00", -- 0xA1
|
||||
X"00", -- 0xA2
|
||||
X"00", -- 0xA3
|
||||
X"00", -- 0xA4
|
||||
X"00", -- 0xA5
|
||||
X"00", -- 0xA6
|
||||
X"00", -- 0xA7
|
||||
X"00", -- 0xA8
|
||||
X"00", -- 0xA9
|
||||
X"00", -- 0xAA
|
||||
X"00", -- 0xAB
|
||||
X"00", -- 0xAC
|
||||
X"00", -- 0xAD
|
||||
X"00", -- 0xAE
|
||||
X"00", -- 0xAF
|
||||
X"00", -- 0xB0
|
||||
X"00", -- 0xB1
|
||||
X"00", -- 0xB2
|
||||
X"00", -- 0xB3
|
||||
X"00", -- 0xB4
|
||||
X"00", -- 0xB5
|
||||
X"00", -- 0xB6
|
||||
X"00", -- 0xB7
|
||||
X"00", -- 0xB8
|
||||
X"00", -- 0xB9
|
||||
X"00", -- 0xBA
|
||||
X"00", -- 0xBB
|
||||
X"00", -- 0xBC
|
||||
X"00", -- 0xBD
|
||||
X"00", -- 0xBE
|
||||
X"00", -- 0xBF
|
||||
X"00", -- 0xC0
|
||||
X"00", -- 0xC1
|
||||
X"00", -- 0xC2
|
||||
X"00", -- 0xC3
|
||||
X"00", -- 0xC4
|
||||
X"00", -- 0xC5
|
||||
X"00", -- 0xC6
|
||||
X"00", -- 0xC7
|
||||
X"00", -- 0xC8
|
||||
X"00", -- 0xC9
|
||||
X"00", -- 0xCA
|
||||
X"00", -- 0xCB
|
||||
X"00", -- 0xCC
|
||||
X"00", -- 0xCD
|
||||
X"00", -- 0xCE
|
||||
X"00", -- 0xCF
|
||||
X"00", -- 0xD0
|
||||
X"00", -- 0xD1
|
||||
X"00", -- 0xD2
|
||||
X"00", -- 0xD3
|
||||
X"00", -- 0xD4
|
||||
X"00", -- 0xD5
|
||||
X"00", -- 0xD6
|
||||
X"00", -- 0xD7
|
||||
X"00", -- 0xD8
|
||||
X"00", -- 0xD9
|
||||
X"00", -- 0xDA
|
||||
X"00", -- 0xDB
|
||||
X"00", -- 0xDC
|
||||
X"00", -- 0xDD
|
||||
X"00", -- 0xDE
|
||||
X"00", -- 0xDF
|
||||
X"00", -- 0xE0
|
||||
X"00", -- 0xE1
|
||||
X"00", -- 0xE2
|
||||
X"00", -- 0xE3
|
||||
X"00", -- 0xE4
|
||||
X"00", -- 0xE5
|
||||
X"00", -- 0xE6
|
||||
X"00", -- 0xE7
|
||||
X"00", -- 0xE8
|
||||
X"00", -- 0xE9
|
||||
X"00", -- 0xEA
|
||||
X"00", -- 0xEB
|
||||
X"00", -- 0xEC
|
||||
X"00", -- 0xED
|
||||
X"00", -- 0xEE
|
||||
X"00", -- 0xEF
|
||||
X"00", -- 0xF0
|
||||
X"00", -- 0xF1
|
||||
X"00", -- 0xF2
|
||||
X"00", -- 0xF3
|
||||
X"00", -- 0xF4
|
||||
X"00", -- 0xF5
|
||||
X"00", -- 0xF6
|
||||
X"00", -- 0xF7
|
||||
X"00", -- 0xF8
|
||||
X"00", -- 0xF9
|
||||
X"00", -- 0xFA
|
||||
X"00", -- 0xFB
|
||||
X"00", -- 0xFC
|
||||
X"00", -- 0xFD
|
||||
X"00", -- 0xFE
|
||||
X"00" -- 0xFF
|
||||
);
|
||||
|
||||
signal jtag_ld_clk : STD_LOGIC;
|
||||
signal jtag_ld_we : STD_LOGIC;
|
||||
signal jtag_ld_addr : dmem_addr_t;
|
||||
signal jtag_ld_dout : dmem_data_t;
|
||||
signal jtag_ld_din : dmem_data_t;
|
||||
signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;
|
||||
signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;
|
||||
signal user_regi, user_rego : unsigned (15 downto 0);
|
||||
constant id : unsigned (15 downto 0) := X"BEEF";
|
||||
|
||||
begin
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- Virtex-4: JTAG Loader
|
||||
--------------------------------------------------------------------------
|
||||
i00_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_clk1,
|
||||
I => bs_clk0
|
||||
);
|
||||
|
||||
i01_BUFG : BUFG
|
||||
port map
|
||||
(
|
||||
O => bs_update1,
|
||||
I => bs_update0
|
||||
);
|
||||
|
||||
BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4
|
||||
generic map
|
||||
(
|
||||
JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)
|
||||
)
|
||||
port map
|
||||
(
|
||||
CAPTURE => bs_capture, -- CAPTURE output from TAP controller
|
||||
DRCK => bs_clk0, -- Data register output for USER functions
|
||||
RESET => bs_rst, -- Reset output from TAP controller
|
||||
SEL => bs_sel, -- USER active output
|
||||
SHIFT => bs_shift, -- SHIFT output from TAP controller
|
||||
TDI => bs_tdi, -- TDI output from TAP controller
|
||||
UPDATE => bs_update0, -- UPDATE output from TAP controller
|
||||
TDO => bs_tdo -- Data input for USER function
|
||||
);
|
||||
|
||||
jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1);
|
||||
jtag_ld_din <= user_regi(dmem_data_t'left downto 0);
|
||||
jtag_ld_clk <= bs_update1;
|
||||
jtag_ld_we <= bs_sel;
|
||||
|
||||
sipo:
|
||||
process (bs_rst, bs_clk1, bs_tdi, bs_shift)
|
||||
begin
|
||||
if bs_rst = '1' then
|
||||
user_regi <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_regi <= bs_tdi & user_regi(user_regi'left downto 1);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
piso:
|
||||
process (bs_rst, bs_clk1, bs_shift, user_rego)
|
||||
begin
|
||||
bs_tdo <= user_rego(0);
|
||||
if bs_rst = '1' then
|
||||
user_rego <= (others => '0');
|
||||
elsif rising_edge(bs_clk1) then
|
||||
if bs_shift = '1' then
|
||||
user_rego <= user_rego(0) & user_rego(user_rego'left downto 1);
|
||||
else
|
||||
user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout;
|
||||
-- user_rego <= id;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
-- ROM Read/Write
|
||||
--------------------------------------------------------------------------
|
||||
PROM_READ:
|
||||
process(clk, ce)
|
||||
begin
|
||||
if rising_edge(clk) and ce = '1' then
|
||||
dout <= xmem_rom(to_integer(addr));
|
||||
end if;
|
||||
end process;
|
||||
|
||||
PROM_WRITE:
|
||||
process(jtag_ld_clk, jtag_ld_we)
|
||||
begin
|
||||
if rising_edge(jtag_ld_clk) then
|
||||
if jtag_ld_we = '1' then
|
||||
xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din;
|
||||
else
|
||||
jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------------------------------------------------------
|
||||
end loadable;
|
||||
Reference in New Issue
Block a user