diff --git a/lib/uart/uart_wb.vhd b/lib/uart/uart_wb.vhd
index 0c767c6..f13bb4f 100644
--- a/lib/uart/uart_wb.vhd
+++ b/lib/uart/uart_wb.vhd
@@ -78,6 +78,7 @@ ARCHITECTURE behavior OF uart_wb IS
 	signal tx_complete		: std_logic;
 	signal tx_empty			: std_logic;
 	signal tx_busy			: std_logic;
+	signal force_irq_tx		: std_logic;
 	
 begin
 
@@ -90,6 +91,7 @@ registers_write:
 		if rising_edge(CLK_I) then
 			reg_we_uart_tx	<= '0';
 			irq_tx_ack		<= '0';
+			force_irq_tx	<= '0';
 			if RST_I = '1' then
 				reg_uart_baud	<= to_unsigned(53, 16);
 				rx_int_en		<= '0';
@@ -105,6 +107,7 @@ registers_write:
 					rx_int_en		<= DAT_I(6);
 					tx_int_en		<= DAT_I(5);
 					irq_tx_ack		<= DAT_I(8);
+					force_irq_tx	<= DAT_I(9);
 					
 				when "0010" =>
 					reg_uart_baud	<= DAT_I(15 downto 0);
@@ -168,7 +171,9 @@ tx_interrupt:
 			elsif irq_tx_ack = '1' then
 				irq_tx <= '0';
 			else
-				if tx_empty = '0' then
+				if force_irq_tx = '1' then
+					irq_tx <= tx_int_en;
+				elsif tx_empty = '0' then
 					tx_busy <= '1';
 				elsif tx_busy = '1' then
 					irq_tx <= tx_int_en;