- Intital revision

git-svn-id: http://moon:8086/svn/vhdl/trunk@166 cc03376c-175c-47c8-b038-4cd826a8556b

lib/radio/decimator/CIC/src/cic_c_pipe.vhd

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+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    12:16:14 10/02/05
+-- Design Name:    
+-- Module Name:    cordic_stage_pre - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity cic_c_pipe is
+Generic
+(
+	max_diff_delay	: integer := 1;
+	max_width		: integer := 32;
+	max_width_frac	: integer := 20;
+	in_width		: integer := 32;
+	in_width_frac	: integer := 20;
+	out_width		: integer := 32;
+	out_width_frac	: integer := 20
+);
+Port
+(
+	clk			: in std_logic;
+	rst			: in std_logic;
+	vld_in		: in std_logic;
+	diff_delay	: in natural range 1 to max_diff_delay;
+	din			: in sfixed;
+	dout		: out sfixed;
+	vld_out 	: out std_logic
+);
+end cic_c_pipe;
+
+architecture Behavioral of cic_c_pipe is
+
+subtype word_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+type word_pipe_t is array (1 to max_diff_delay) of word_t;
+
+signal word_pipe	: word_pipe_t;
+
+------------------------------------------------------------
+begin
+
+------------------------------------------------------------
+delay_pipe_proc: 
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+--				for i in 1 to max_diff_delay loop
+--					word_pipe(i) <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
+--				end loop;
+			elsif vld_in = '1' then
+				word_pipe(1)	<= resize(din, word_pipe(1));
+				for i in 2 to max_diff_delay loop
+					word_pipe(i)	<= word_pipe(i-1);
+				end loop;
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------
+comb_proc: 
+	process(clk)
+	variable x0, x1 : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+	
+	begin
+		if rising_edge(clk) then
+			vld_out <= '0';
+			x0	:= resize(din, x0);
+			x1	:= word_pipe(diff_delay);
+			if rst = '1' then
+				dout <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
+			elsif vld_in = '1' then
+				vld_out <= '1';
+				dout	<= resize(x0 - x1, shi(out_width, out_width_frac), slo(out_width, out_width_frac));
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------
+end Behavioral;
+