jens
d9ba866ed0
git-svn-id: http://moon:8086/svn/vhdl/trunk@166 cc03376c-175c-47c8-b038-4cd826a8556b
106 lines
2.6 KiB
VHDL
106 lines
2.6 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12:16:14 10/02/05
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-- Design Name:
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-- Module Name: cordic_stage_pre - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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library work;
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use work.fixed_pkg.all;
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use work.fixed_util_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity cic_c_pipe is
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Generic
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(
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max_diff_delay : integer := 1;
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max_width : integer := 32;
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max_width_frac : integer := 20;
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in_width : integer := 32;
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in_width_frac : integer := 20;
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out_width : integer := 32;
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out_width_frac : integer := 20
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);
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Port
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(
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clk : in std_logic;
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rst : in std_logic;
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vld_in : in std_logic;
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diff_delay : in natural range 1 to max_diff_delay;
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din : in sfixed;
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dout : out sfixed;
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vld_out : out std_logic
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);
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end cic_c_pipe;
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architecture Behavioral of cic_c_pipe is
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subtype word_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
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type word_pipe_t is array (1 to max_diff_delay) of word_t;
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signal word_pipe : word_pipe_t;
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------------------------------------------------------------
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begin
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------------------------------------------------------------
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delay_pipe_proc:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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-- for i in 1 to max_diff_delay loop
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-- word_pipe(i) <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
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-- end loop;
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elsif vld_in = '1' then
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word_pipe(1) <= resize(din, word_pipe(1));
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for i in 2 to max_diff_delay loop
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word_pipe(i) <= word_pipe(i-1);
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end loop;
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end if;
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end if;
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end process;
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------------------------------------------------------------
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comb_proc:
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process(clk)
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variable x0, x1 : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
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begin
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if rising_edge(clk) then
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vld_out <= '0';
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x0 := resize(din, x0);
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x1 := word_pipe(diff_delay);
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if rst = '1' then
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dout <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
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elsif vld_in = '1' then
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vld_out <= '1';
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dout <= resize(x0 - x1, shi(out_width, out_width_frac), slo(out_width, out_width_frac));
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end if;
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end if;
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end process;
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------------------------------------------------------------
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end Behavioral;
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