diff --git a/lib/radio/ddc/sim/tb_ddc.fdo b/lib/radio/ddc/sim/tb_ddc.fdo
new file mode 100644
index 0000000..b7911bd
--- /dev/null
+++ b/lib/radio/ddc/sim/tb_ddc.fdo
@@ -0,0 +1,22 @@
+vlib work
+vcom -explicit  -93 "../../../fixed/fixed_pkg_c.vhd"
+vcom -explicit  -93 "../../../fixed/fixed_util_pkg.vhd"
+vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit  -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit  -93 "../../cordic/src/cordic_pkg.vhd"
+vcom -explicit  -93 "../../cordic/src/cordic_pipe_stage.vhd"
+vcom -explicit  -93 "../../cordic/src/cordic_pipe_pre.vhd"
+vcom -explicit  -93 "../../cordic/src/cordic_pipe_post.vhd"
+vcom -explicit  -93 "../../cordic/src/cordic_pipe_top.vhd"
+vcom -explicit  -93 "../../nco/src/mix_cordic.vhd"
+vcom -explicit  -93 "../../decimator/CIC/src/cic_i_pipe.vhd"
+vcom -explicit  -93 "../../decimator/CIC/src/cic_c_pipe.vhd"
+vcom -explicit  -93 "../../decimator/CIC/src/cic_decim_pipe.vhd"
+vcom -explicit  -93 "../src/ddc.vhd"
+vcom -explicit  -93 "../src/tb_ddc.vhd"
+vsim -t 1ps   -lib work tb_ddc
+do {tb_ddc.wdo}
+view wave
+view structure
+view signals
+run 400us
diff --git a/lib/radio/ddc/sim/tb_ddc.wdo b/lib/radio/ddc/sim/tb_ddc.wdo
new file mode 100644
index 0000000..93e3549
--- /dev/null
+++ b/lib/radio/ddc/sim/tb_ddc.wdo
@@ -0,0 +1,64 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_ddc/clk
+add wave -noupdate -format Logic /tb_ddc/rst
+add wave -noupdate -format Logic /tb_ddc/ddc_shift_we
+add wave -noupdate -format Literal /tb_ddc/ddc_shift_addr
+add wave -noupdate -format Literal /tb_ddc/ddc_shift_in
+add wave -noupdate -format Logic /tb_ddc/ddc_nco_rst
+add wave -noupdate -format Logic /tb_ddc/ddc_nco_en
+add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_freq_in
+add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_phase_in
+add wave -noupdate -format Literal /tb_ddc/ddc_ratio
+add wave -noupdate -format Literal /tb_ddc/ddc_diff_delay
+add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_i
+add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_din_q
+add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_i
+add wave -noupdate -format Literal -radix decimal /tb_ddc/ddc_dout_q
+add wave -noupdate -format Logic /tb_ddc/ddc_dout_vld
+add wave -noupdate -format Logic /tb_ddc/ddc_din_vld
+add wave -noupdate -format Logic /tb_ddc/rfgen_nco_rst
+add wave -noupdate -format Logic /tb_ddc/rfgen_nco_en
+add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_freq_in
+add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_phase_in
+add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_i
+add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_din_q
+add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_i
+add wave -noupdate -format Literal -radix decimal /tb_ddc/rfgen_dout_q
+add wave -noupdate -format Logic /tb_ddc/rfgen_dout_vld
+add wave -noupdate -format Logic /tb_ddc/fileout_enable
+add wave -noupdate -divider DDC
+add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_i
+add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/din_q
+add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_i
+add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dout_q
+add wave -noupdate -format Logic /tb_ddc/uut/din_vld
+add wave -noupdate -format Logic /tb_ddc/uut/dout_vld
+add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_i
+add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/mix_dout_q
+add wave -noupdate -format Logic /tb_ddc/uut/mix_dout_vld
+add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_i
+add wave -noupdate -format Literal -radix decimal /tb_ddc/uut/dec_dout_q
+add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_i
+add wave -noupdate -format Logic /tb_ddc/uut/dec_dout_vld_q
+add wave -noupdate -format Logic /tb_ddc/ddc_din_vld
+add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_i_out_f
+add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/ddc_q_out_f
+add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_i_out_f
+add wave -noupdate -format Analog-Step -height 50 -scale 10.0 /tb_ddc/rfgen_q_out_f
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {399851293 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {399827014 ps} {400009105 ps}
diff --git a/lib/radio/ddc/sim/tb_results.m b/lib/radio/ddc/sim/tb_results.m
new file mode 100644
index 0000000..3274d28
--- /dev/null
+++ b/lib/radio/ddc/sim/tb_results.m
@@ -0,0 +1,36 @@
+% Read data
+function tb_results()
+fa = 100.0;
+f = TEXTREAD('freq.txt')*1E-6
+R = 64;
+fa_dec = fa/R
+N_pfir = 63;
+
+I_out_dec = TEXTREAD('i_dec.txt')';
+Q_out_dec = TEXTREAD('q_dec.txt')';
+
+N_dec = length(I_out_dec)-2*N_pfir;
+N_fft_dec = N_dec
+N_fft2_dec = N_fft_dec/2;
+fft_y2_dec = 2/N_fft_dec*abs(fft(I_out_dec(2*N_pfir+1:N_fft_dec+2*N_pfir).*hann(N_fft_dec)'));
+
+pfir_b = sinc(0.2*(-(N_pfir-1)/2:1:(N_pfir)/2));
+pfir_b = pfir_b/sum(pfir_b).*blackman(N_pfir)';
+I_out_dec_pfir = filter(pfir_b, 1, I_out_dec);
+Q_out_dec_pfir = filter(pfir_b, 1, Q_out_dec);
+fft_y2_dec_pfir = 2/N_fft_dec*abs(fft(I_out_dec_pfir(2*N_pfir+1:N_fft_dec+2*N_pfir).*hann(N_fft_dec)'));
+
+% Output
+close all;
+
+plot(fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(fft_y2_dec(1:N_fft2_dec+1)), '-', fa/(R*N_fft_dec)*(0:N_fft2_dec),20*log10(fft_y2_dec_pfir(1:N_fft2_dec+1)), '-'); grid;
+xlabel('MHz');
+figure;
+plot(1:length(I_out_dec_pfir), I_out_dec_pfir, 1:length(Q_out_dec_pfir), Q_out_dec_pfir); grid;
+
+figure;
+freqz(pfir_b, 1, 1000);
+
+figure;
+plot(pfir_b); grid;
+
diff --git a/lib/radio/ddc/src/ddc.vhd b/lib/radio/ddc/src/ddc.vhd
new file mode 100644
index 0000000..563baa1
--- /dev/null
+++ b/lib/radio/ddc/src/ddc.vhd
@@ -0,0 +1,219 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_nco
+-- Module Name:   tb_nco.vhd
+-- Project Name:  nco
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+
+ENTITY ddc IS
+	Generic 
+	(
+		nbits_in			: integer := 18;
+		nbits_in_frac		: integer := 16;
+		nbits_out			: integer := 18;
+		nbits_out_frac		: integer := 16;
+		lo_nbits_phase		: integer := 20;
+		lo_nbits_freq		: integer := 20;
+		cic_nstages			: integer := 3;
+		cic_max_ratio		: integer := 4096;
+		cic_max_diff_delay	: integer := 2;
+		cic_max_width		: integer := 32;
+		cic_max_width_frac	: integer := 20
+	);
+	PORT
+	(
+		rst					: in std_logic;
+		clk					: in std_logic;
+		lo_nco_rst			: in std_logic;
+		lo_nco_en			: in std_logic;
+		lo_freq_in			: in unsigned(lo_nbits_freq-1 downto 0);
+		lo_phase_in			: in unsigned(lo_nbits_phase-1 downto 0);
+		cic_ratio			: in natural range 1 to cic_max_ratio;
+		cic_diff_delay		: in natural range 1 to cic_max_diff_delay;
+		cic_shift_in		: in natural range 0 to cic_max_width-1;
+		din_i				: in  sfixed;
+		din_q				: in  sfixed;
+		dout_i				: out sfixed;
+		dout_q				: out sfixed;
+		din_vld				: in  std_logic;
+		dout_vld			: out std_logic
+	);
+END ddc;
+
+ARCHITECTURE behavior OF ddc IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT mix
+	GENERIC
+	(
+		nbits_din		: integer;
+		nbits_din_frac	: integer;
+		nbits_dout		: integer;
+		nbits_dout_frac	: integer;
+		nbits_phase		: integer;
+		nbits_freq		: integer
+	);
+	PORT
+	(
+		rst				: in std_logic;
+		clk				: in std_logic;
+		nco_rst			: in std_logic;
+		nco_en			: in std_logic;
+		freq_in			: in unsigned(nbits_freq-1 downto 0);
+		phase_in		: in unsigned(nbits_phase-1 downto 0);
+		din_i			: in  sfixed;
+		din_q			: in  sfixed;
+		dout_i			: out sfixed;
+		dout_q			: out sfixed;
+		din_vld			: in std_logic;
+		dout_vld		: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT cic_decim_pipe
+	GENERIC
+	(
+		nstages			: integer;
+		max_ratio		: integer;
+		max_diff_delay	: integer;
+		max_width		: integer;
+		max_width_frac	: integer;
+		in_width		: integer;
+		in_width_frac	: integer;
+		out_width		: integer;
+		out_width_frac	: integer
+	);
+	PORT
+	(
+		clk				: in std_logic;
+		rst				: in std_logic;
+		vld_in			: in std_logic;
+		ratio			: in natural range 1 to max_ratio;
+		diff_delay		: in natural range 1 to max_diff_delay;
+		shift_in		: in natural range 0 to max_width-1;
+		din				: in sfixed;
+		dout			: out sfixed;
+		vld_out 		: out std_logic
+	);
+	END COMPONENT;
+
+	constant lo_nbits_in		: integer := nbits_in;
+	constant lo_nbits_in_frac	: integer := nbits_in_frac;
+	constant lo_nbits_out		: integer := nbits_in;
+	constant lo_nbits_out_frac	: integer := nbits_in_frac;
+	
+	constant cic_nbits_in		: integer := lo_nbits_out;
+	constant cic_nbits_in_frac	: integer := lo_nbits_out_frac;
+	constant cic_nbits_out		: integer := nbits_out;
+	constant cic_nbits_out_frac	: integer := nbits_out_frac;
+
+	SIGNAL mix_dout_i			: sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
+	SIGNAL mix_dout_q			: sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
+	SIGNAL mix_dout_vld			: std_logic;
+
+	SIGNAL dec_dout_i			: sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
+	SIGNAL dec_dout_q			: sfixed(shi(cic_nbits_out, cic_nbits_out_frac) downto slo(cic_nbits_out, cic_nbits_out_frac));
+	SIGNAL dec_dout_vld_i		: std_logic;
+	SIGNAL dec_dout_vld_q		: std_logic;
+
+BEGIN
+
+	dout_vld	<= dec_dout_vld_i and dec_dout_vld_q;
+	dout_i		<= dec_dout_i;
+	dout_q		<= dec_dout_q;
+	
+	-- Instantiate the Unit Under Test (UUT)
+	inst_mixer: mix 
+	GENERIC MAP
+	(
+		nbits_din			=> lo_nbits_in,
+		nbits_din_frac		=> lo_nbits_in_frac,
+		nbits_dout			=> lo_nbits_out,
+		nbits_dout_frac		=> lo_nbits_out_frac,
+		nbits_phase			=> lo_nbits_phase,
+		nbits_freq			=> lo_nbits_freq
+	)
+	PORT MAP
+	(
+		rst					=> rst,
+		clk					=> clk,
+		nco_rst				=> lo_nco_rst,
+		nco_en				=> lo_nco_en,
+		freq_in				=> lo_freq_in,
+		phase_in			=> lo_phase_in,
+		din_i				=> din_i,
+		din_q				=> din_q,
+		dout_i				=> mix_dout_i,
+		dout_q				=> mix_dout_q,
+		din_vld				=> din_vld,
+		dout_vld			=> mix_dout_vld
+	);
+
+	inst_cic_decim_pipe_I : cic_decim_pipe
+	GENERIC MAP
+	(
+		nstages				=> cic_nstages,
+		max_ratio			=> cic_max_ratio,
+		max_diff_delay		=> cic_max_diff_delay,
+		max_width			=> cic_max_width,
+		max_width_frac		=> cic_max_width_frac,
+		in_width			=> cic_nbits_in,
+		in_width_frac		=> cic_nbits_in_frac,
+		out_width			=> cic_nbits_out,
+		out_width_frac		=> cic_nbits_out_frac
+	)
+	PORT MAP
+	(
+		clk					=> clk,
+		rst					=> rst,
+		vld_in				=> mix_dout_vld,
+		ratio				=> cic_ratio,
+		diff_delay			=> cic_diff_delay,
+		shift_in			=> cic_shift_in,
+		din					=> mix_dout_i,
+		dout				=> dec_dout_i,
+		vld_out				=> dec_dout_vld_i
+	);
+
+	inst_cic_decim_pipe_Q : cic_decim_pipe
+	GENERIC MAP
+	(
+		nstages				=> cic_nstages,
+		max_ratio			=> cic_max_ratio,
+		max_diff_delay		=> cic_max_diff_delay,
+		max_width			=> cic_max_width,
+		max_width_frac		=> cic_max_width_frac,
+		in_width			=> cic_nbits_in,
+		in_width_frac		=> cic_nbits_in_frac,
+		out_width			=> cic_nbits_out,
+		out_width_frac		=> cic_nbits_out_frac
+	)
+	PORT MAP
+	(
+		clk					=> clk,
+		rst					=> rst,
+		vld_in				=> mix_dout_vld,
+		ratio				=> cic_ratio,
+		diff_delay			=> cic_diff_delay,
+		shift_in			=> cic_shift_in,
+		din					=> mix_dout_q,
+		dout				=> dec_dout_q,
+		vld_out				=> dec_dout_vld_q
+	);
+
+END;
diff --git a/lib/radio/ddc/src/syn_ddc.vhd b/lib/radio/ddc/src/syn_ddc.vhd
new file mode 100644
index 0000000..c220b9a
--- /dev/null
+++ b/lib/radio/ddc/src/syn_ddc.vhd
@@ -0,0 +1,146 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_nco
+-- Module Name:   tb_nco.vhd
+-- Project Name:  nco
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+use work.cordic_pkg.all;
+
+	ENTITY syn_ddc IS
+	Generic 
+	(
+		nbits_in			: integer := 18;
+		nbits_in_frac		: integer := 16;
+		nbits_out			: integer := 18;
+		nbits_out_frac		: integer := 16;
+		lo_nbits_phase		: integer := 20;
+		lo_nbits_freq		: integer := 20;
+		cic_nstages			: integer := 3;
+		cic_max_ratio		: integer := 1024;
+		cic_max_diff_delay	: integer := 2;
+		cic_max_width		: integer := 48;
+		cic_max_width_frac	: integer := 16
+	);
+	PORT
+	(
+		rst					: in std_logic;
+		clk					: in std_logic;
+		lo_nco_rst			: in std_logic;
+		lo_nco_en			: in std_logic;
+		lo_freq_in			: in unsigned(lo_nbits_freq-1 downto 0);
+		lo_phase_in			: in unsigned(lo_nbits_phase-1 downto 0);
+		cic_ratio			: in natural range 1 to cic_max_ratio;
+		cic_diff_delay		: in natural range 1 to cic_max_diff_delay;
+		cic_shift_in		: in natural range 0 to cic_max_width-1;
+		din_i				: in  signed(nbits_in-1 downto 0);
+		din_q				: in  signed(nbits_in-1 downto 0);
+		dout_i				: out signed(nbits_out-1 downto 0);
+		dout_q				: out signed(nbits_out-1 downto 0);
+		din_vld				: in  std_logic;
+		dout_vld			: out std_logic
+	);
+	END syn_ddc;
+
+ARCHITECTURE behavior OF syn_ddc IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT ddc
+	GENERIC 
+	(
+		nbits_in			: integer;
+		nbits_in_frac		: integer;
+		nbits_out			: integer;
+		nbits_out_frac		: integer;
+		lo_nbits_phase		: integer;
+		lo_nbits_freq		: integer;
+		cic_nstages			: integer;
+		cic_max_ratio		: integer;
+		cic_max_diff_delay	: integer;
+		cic_max_width		: integer;
+		cic_max_width_frac	: integer
+	);
+	PORT
+	(
+		rst					: in std_logic;
+		clk					: in std_logic;
+		lo_nco_rst			: in std_logic;
+		lo_nco_en			: in std_logic;
+		lo_freq_in			: in unsigned(lo_nbits_freq-1 downto 0);
+		lo_phase_in			: in unsigned(lo_nbits_phase-1 downto 0);
+		cic_ratio			: in natural range 1 to cic_max_ratio;
+		cic_diff_delay		: in natural range 1 to cic_max_diff_delay;
+		cic_shift_in		: in natural range 0 to cic_max_width-1;
+		din_i				: in  sfixed;
+		din_q				: in  sfixed;
+		dout_i				: out sfixed;
+		dout_q				: out sfixed;
+		din_vld				: in  std_logic;
+		dout_vld			: out std_logic
+	);
+	END COMPONENT;
+
+	--Outputs
+	SIGNAL ddc_din_i		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL ddc_din_q		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL ddc_dout_i		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
+	SIGNAL ddc_dout_q		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	inst_ddc : ddc
+	GENERIC MAP 
+	(
+		nbits_in			=> nbits_in,
+		nbits_in_frac		=> nbits_in_frac,
+		nbits_out			=> nbits_out,
+		nbits_out_frac		=> nbits_out_frac,
+		lo_nbits_phase		=> lo_nbits_phase,
+		lo_nbits_freq		=> lo_nbits_freq,
+		cic_nstages			=> cic_nstages,
+		cic_max_ratio		=> cic_max_ratio,
+		cic_max_diff_delay	=> cic_max_diff_delay,
+		cic_max_width		=> cic_max_width,
+		cic_max_width_frac	=> cic_max_width_frac
+	)
+	PORT MAP
+	(
+		rst					=> rst,
+		clk					=> clk,
+		lo_nco_rst			=> lo_nco_rst,
+		lo_nco_en			=> lo_nco_en,
+		lo_freq_in			=> lo_freq_in,
+		lo_phase_in			=> lo_phase_in,
+		cic_ratio			=> cic_ratio,
+		cic_diff_delay		=> cic_diff_delay,
+		cic_shift_in		=> cic_shift_in,
+		din_i				=> ddc_din_i,
+		din_q				=> ddc_din_q,
+		dout_i				=> ddc_dout_i,
+		dout_q				=> ddc_dout_q,
+		din_vld				=> din_vld,
+		dout_vld			=> dout_vld
+	);
+	
+	ddc_din_i	<= to_sfixed(din_i, ddc_din_i);
+	ddc_din_q	<= to_sfixed(din_q, ddc_din_q);
+	
+	dout_i	<= signed(ddc_dout_i);
+	dout_q	<= signed(ddc_dout_q);
+	
+END;
diff --git a/lib/radio/ddc/src/tb_ddc.vhd b/lib/radio/ddc/src/tb_ddc.vhd
new file mode 100644
index 0000000..b557fdb
--- /dev/null
+++ b/lib/radio/ddc/src/tb_ddc.vhd
@@ -0,0 +1,378 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_nco
+-- Module Name:   tb_nco.vhd
+-- Project Name:  nco
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+use work.cordic_pkg.all;
+use work.PCK_FIO.all;
+
+ENTITY tb_ddc IS
+	Generic 
+	(
+		nbits_in			: integer := 16;
+		nbits_in_frac		: integer := 14;
+		nbits_out			: integer := 18;
+		nbits_out_frac		: integer := 16;
+		lo_nbits_phase		: integer := 20;
+		lo_nbits_freq		: integer := 20;
+		cic_nstages			: integer := 3;
+		cic_max_ratio		: integer := 4096;
+		cic_max_diff_delay	: integer := 1;
+		cic_max_width		: integer := 36;
+		cic_max_width_frac	: integer := 16;
+		rfgen_nbits_phase	: integer := 20;
+		rfgen_nbits_freq	: integer := 20
+	);
+END tb_ddc;
+
+ARCHITECTURE behavior OF tb_ddc IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT ddc
+	GENERIC 
+	(
+		nbits_in			: integer;
+		nbits_in_frac		: integer;
+		nbits_out			: integer;
+		nbits_out_frac		: integer;
+		lo_nbits_phase		: integer;
+		lo_nbits_freq		: integer;
+		cic_nstages			: integer;
+		cic_max_ratio		: integer;
+		cic_max_diff_delay	: integer;
+		cic_max_width		: integer;
+		cic_max_width_frac	: integer
+	);
+	PORT
+	(
+		rst					: in std_logic;
+		clk					: in std_logic;
+		lo_nco_rst			: in std_logic;
+		lo_nco_en			: in std_logic;
+		lo_freq_in			: in unsigned(lo_nbits_freq-1 downto 0);
+		lo_phase_in			: in unsigned(lo_nbits_phase-1 downto 0);
+		cic_ratio			: in natural range 1 to cic_max_ratio;
+		cic_diff_delay		: in natural range 1 to cic_max_diff_delay;
+		cic_shift_in		: in natural range 0 to cic_max_width-1;
+		din_i				: in  sfixed;
+		din_q				: in  sfixed;
+		dout_i				: out sfixed;
+		dout_q				: out sfixed;
+		din_vld				: in  std_logic;
+		dout_vld			: out std_logic
+	);
+	END COMPONENT;
+
+	-- Rf-Generator
+	COMPONENT mix
+	GENERIC
+	(
+		nbits_din		: integer;
+		nbits_din_frac	: integer;
+		nbits_dout		: integer;
+		nbits_dout_frac	: integer;
+		nbits_phase		: integer;
+		nbits_freq		: integer
+	);
+	PORT
+	(
+		rst				: in std_logic;
+		clk				: in std_logic;
+		nco_rst			: in std_logic;
+		nco_en			: in std_logic;
+		freq_in			: in unsigned(nbits_freq-1 downto 0);
+		phase_in		: in unsigned(nbits_phase-1 downto 0);
+		din_i			: in  sfixed;
+		din_q			: in  sfixed;
+		dout_i			: out sfixed;
+		dout_q			: out sfixed;
+		din_vld			: in std_logic;
+		dout_vld		: out std_logic
+	);
+	END COMPONENT;
+
+	--Constants
+	constant fa : REAL := 100.0E6;
+	constant frf1 : REAL := 29.9E6;
+	constant frf2 : REAL := 30.0E6;
+	constant frf3 : REAL := 30.1E6;
+	constant flo : REAL := 30.0E6;
+	constant PERIOD : time := 10 ns;
+
+	SIGNAL rfgen1_freq_word	: integer := integer(frf1/fa*2.0**rfgen_nbits_freq);
+	SIGNAL rfgen2_freq_word	: integer := integer(frf2/fa*2.0**rfgen_nbits_freq);
+	SIGNAL rfgen3_freq_word	: integer := integer(frf3/fa*2.0**rfgen_nbits_freq);
+	SIGNAL lo_freq_word		: integer := integer(flo/fa*2.0**lo_nbits_freq);
+
+	--Inputs
+	SIGNAL clk				: std_logic := '0';
+	SIGNAL rst				: std_logic := '1';
+	SIGNAL ddc_nco_rst		: std_logic := '0';
+	SIGNAL ddc_nco_en		: std_logic := '0';
+	SIGNAL ddc_freq_in		: unsigned(lo_nbits_freq-1 downto 0) := (others => '0');
+	SIGNAL ddc_phase_in		: unsigned(lo_nbits_phase-1 downto 0) := (others => '0');
+	SIGNAL ddc_diff_delay	: natural := 1;
+	SIGNAL ddc_ratio		: natural := 64;
+	SIGNAL ddc_shift_in		: natural := 18;
+
+	--Outputs
+	SIGNAL ddc_din_i		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL ddc_din_q		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL ddc_dout_i		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
+	SIGNAL ddc_dout_q		: sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac));
+	SIGNAL ddc_dout_vld		: std_logic;
+	SIGNAL ddc_din_vld		: std_logic := '0';
+		
+	SIGNAL rfgen_nco_rst	: std_logic := '0';
+	SIGNAL rfgen_nco_en		: std_logic := '0';
+	SIGNAL rfgen1_freq_in	: unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
+	SIGNAL rfgen1_phase_in	: unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
+	SIGNAL rfgen2_freq_in	: unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
+	SIGNAL rfgen2_phase_in	: unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
+	SIGNAL rfgen3_freq_in	: unsigned(rfgen_nbits_freq-1 downto 0) := (others => '0');
+	SIGNAL rfgen3_phase_in	: unsigned(rfgen_nbits_phase-1 downto 0) := (others => '0');
+
+	--Outputs
+	signal rfgen_din_i		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(0.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
+	signal rfgen_din_q		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)) := to_sfixed(1.0, shi(nbits_in, nbits_in_frac), slo(nbits_in, nbits_in_frac));
+	SIGNAL rfgen_dout_i		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL rfgen_dout_q		: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL rfgen1_dout_i	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL rfgen1_dout_q	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL rfgen1_dout_vld	: std_logic;
+	SIGNAL rfgen2_dout_i	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL rfgen2_dout_q	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL rfgen2_dout_vld	: std_logic;
+	SIGNAL rfgen3_dout_i	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL rfgen3_dout_q	: sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
+	SIGNAL rfgen3_dout_vld	: std_logic;
+
+	SIGNAL fileout_enable   : std_logic := '0';
+
+	-- Debug
+	signal ddc_i_out_f		: real;
+	signal ddc_q_out_f		: real;
+	signal rfgen_i_out_f	: real;
+	signal rfgen_q_out_f	: real;
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut : ddc
+	GENERIC MAP 
+	(
+		nbits_in			=> nbits_in,
+		nbits_in_frac		=> nbits_in_frac,
+		nbits_out			=> nbits_out,
+		nbits_out_frac		=> nbits_out_frac,
+		lo_nbits_phase		=> lo_nbits_phase,
+		lo_nbits_freq		=> lo_nbits_freq,
+		cic_nstages			=> cic_nstages,
+		cic_max_ratio		=> cic_max_ratio,
+		cic_max_diff_delay	=> cic_max_diff_delay,
+		cic_max_width		=> cic_max_width,
+		cic_max_width_frac	=> cic_max_width_frac
+	)
+	PORT MAP
+	(
+		rst					=> rst,
+		clk					=> clk,
+		lo_nco_rst			=> ddc_nco_rst,
+		lo_nco_en			=> ddc_nco_en,
+		lo_freq_in			=> ddc_freq_in,
+		lo_phase_in			=> ddc_phase_in,
+		cic_ratio			=> ddc_ratio,
+		cic_diff_delay		=> ddc_diff_delay,
+		cic_shift_in		=> ddc_shift_in,
+		din_i				=> ddc_din_i,
+		din_q				=> ddc_din_q,
+		dout_i				=> ddc_dout_i,
+		dout_q				=> ddc_dout_q,
+		din_vld				=> ddc_din_vld,
+		dout_vld			=> ddc_dout_vld
+	);
+	
+	rfgen1: mix 
+	GENERIC MAP
+	(
+		nbits_din			=> nbits_in,
+		nbits_din_frac		=> nbits_in_frac,
+		nbits_dout			=> nbits_in,
+		nbits_dout_frac		=> nbits_in_frac,
+		nbits_phase			=> rfgen_nbits_phase,
+		nbits_freq			=> rfgen_nbits_freq
+	)
+	PORT MAP
+	(
+		rst					=> rst,
+		clk					=> clk,
+		nco_rst				=> rfgen_nco_rst,
+		nco_en				=> rfgen_nco_en,
+		freq_in				=> rfgen1_freq_in,
+		phase_in			=> rfgen1_phase_in,
+		din_i				=> rfgen_din_i,
+		din_q				=> rfgen_din_q,
+		dout_i				=> rfgen1_dout_i,
+		dout_q				=> rfgen1_dout_q,
+		din_vld				=> '1',
+		dout_vld			=> rfgen1_dout_vld
+	);
+
+	rfgen2: mix 
+	GENERIC MAP
+	(
+		nbits_din			=> nbits_in,
+		nbits_din_frac		=> nbits_in_frac,
+		nbits_dout			=> nbits_in,
+		nbits_dout_frac		=> nbits_in_frac,
+		nbits_phase			=> rfgen_nbits_phase,
+		nbits_freq			=> rfgen_nbits_freq
+	)
+	PORT MAP
+	(
+		rst					=> rst,
+		clk					=> clk,
+		nco_rst				=> rfgen_nco_rst,
+		nco_en				=> rfgen_nco_en,
+		freq_in				=> rfgen2_freq_in,
+		phase_in			=> rfgen2_phase_in,
+		din_i				=> rfgen_din_i,
+		din_q				=> rfgen_din_q,
+		dout_i				=> rfgen2_dout_i,
+		dout_q				=> rfgen2_dout_q,
+		din_vld				=> '1',
+		dout_vld			=> rfgen2_dout_vld
+	);
+
+	rfgen3: mix 
+	GENERIC MAP
+	(
+		nbits_din			=> nbits_in,
+		nbits_din_frac		=> nbits_in_frac,
+		nbits_dout			=> nbits_in,
+		nbits_dout_frac		=> nbits_in_frac,
+		nbits_phase			=> rfgen_nbits_phase,
+		nbits_freq			=> rfgen_nbits_freq
+	)
+	PORT MAP
+	(
+		rst					=> rst,
+		clk					=> clk,
+		nco_rst				=> rfgen_nco_rst,
+		nco_en				=> rfgen_nco_en,
+		freq_in				=> rfgen3_freq_in,
+		phase_in			=> rfgen3_phase_in,
+		din_i				=> rfgen_din_i,
+		din_q				=> rfgen_din_q,
+		dout_i				=> rfgen3_dout_i,
+		dout_q				=> rfgen3_dout_q,
+		din_vld				=> '1',
+		dout_vld			=> rfgen3_dout_vld
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+	rfgen_dout_i	<= resize(0.333*rfgen1_dout_i + 0.333*rfgen2_dout_i + 0.333*rfgen3_dout_i, rfgen_dout_i);
+	rfgen_dout_q	<= resize(0.333*rfgen1_dout_q + 0.333*rfgen2_dout_q + 0.333*rfgen3_dout_q, rfgen_dout_q);
+
+	ddc_din_i	<= rfgen_dout_i;
+	ddc_din_q	<= to_sfixed(0.0, ddc_din_q);
+	ddc_din_vld	<= rfgen1_dout_vld and rfgen2_dout_vld and rfgen3_dout_vld;
+	
+	ddc_i_out_f	<= to_real(ddc_dout_i);
+	ddc_q_out_f	<= to_real(ddc_dout_q);
+	
+	rfgen_i_out_f	<= to_real(rfgen_dout_i);
+	rfgen_q_out_f	<= to_real(rfgen_dout_q);
+	
+	tb : PROCESS
+	file RESULT_FREQ:   text open write_mode is "freq.txt"; 
+	variable L:         line;
+
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 4*PERIOD;
+		rst <= '0';
+
+		fprint(RESULT_FREQ, L,"%s\n", REAL'image(flo));
+
+		wait for 2*PERIOD;
+		-------------------------------------------
+		-- Program gains
+		wait for 2*PERIOD;
+		wait until rising_edge(clk);
+
+		-- start DDC
+		ddc_phase_in <= to_unsigned(0,lo_nbits_phase);
+		ddc_freq_in <= to_unsigned(lo_freq_word,lo_nbits_freq);
+		wait until rising_edge(clk);
+		ddc_nco_en	<= '1';
+		
+		wait for 20*PERIOD;
+		fileout_enable <= '1';
+
+		wait; 
+	END PROCESS;
+	
+	
+	rfgen_ctrl : PROCESS
+
+	BEGIN
+			wait until rising_edge(clk) and rst = '0';
+			rfgen1_freq_in <= to_unsigned(rfgen1_freq_word,rfgen_nbits_freq);
+			rfgen1_phase_in <= to_unsigned(0,rfgen_nbits_phase);
+			rfgen2_freq_in <= to_unsigned(rfgen2_freq_word,rfgen_nbits_freq);
+			rfgen2_phase_in <= to_unsigned(0,rfgen_nbits_phase);
+			rfgen3_freq_in <= to_unsigned(rfgen3_freq_word,rfgen_nbits_freq);
+			rfgen3_phase_in <= to_unsigned(0,rfgen_nbits_phase);
+			wait until rising_edge(clk);
+			rfgen_nco_en <= '1';
+	
+
+		wait; 
+	END PROCESS;
+
+	tb_fo : PROCESS(clk)
+	file RESULT_Ii:      text open write_mode is "i_in.txt"; 
+	file RESULT_Qi:      text open write_mode is "q_in.txt"; 
+	file RESULT_Io:      text open write_mode is "i_dec.txt"; 
+	file RESULT_Qo:      text open write_mode is "q_dec.txt"; 
+	variable L:         line;
+
+	BEGIN
+		if rising_edge(clk) and fileout_enable = '1' then
+			if ddc_din_vld = '1' then
+				fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_dout_i)));
+				fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_dout_q)));
+			end if;
+			if ddc_dout_vld = '1' then
+				fprint(RESULT_Io, L,"%s\n", REAL'image(to_real(ddc_dout_i)));
+				fprint(RESULT_Qo, L,"%s\n", REAL'image(to_real(ddc_dout_q)));
+			end if;
+		end if;
+
+	END PROCESS;
+
+END;
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo
new file mode 100644
index 0000000..db60e85
--- /dev/null
+++ b/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.fdo
@@ -0,0 +1,13 @@
+vlib work
+vcom -explicit  -93 "../../../../fixed/fixed_pkg_c.vhd"
+vcom -explicit  -93 "../../../../fixed/fixed_util_pkg.vhd"
+vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit  -93 "../src/cic_c_pipe.vhd"
+vcom -explicit  -93 "../src/tb_cic_c_pipe.vhd"
+vsim -t 1ps   -lib work tb_cic_c_pipe
+do {tb_cic_c_pipe.wdo}
+view wave
+view structure
+view signals
+run 500ns
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo
new file mode 100644
index 0000000..901e089
--- /dev/null
+++ b/lib/radio/decimator/CIC/sim/tb_cic_c_pipe.wdo
@@ -0,0 +1,26 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cic_c_pipe/clk
+add wave -noupdate -format Logic /tb_cic_c_pipe/srst
+add wave -noupdate -format Logic /tb_cic_c_pipe/vld_in
+add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/din
+add wave -noupdate -format Literal /tb_cic_c_pipe/diff_delay
+add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/dout
+add wave -noupdate -format Logic /tb_cic_c_pipe/vld_out
+add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/uut/word_pipe
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {250000 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {500608 ps}
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo
new file mode 100644
index 0000000..8fb70d9
--- /dev/null
+++ b/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.fdo
@@ -0,0 +1,15 @@
+vlib work
+vcom -explicit  -93 "../../../../fixed/fixed_pkg_c.vhd"
+vcom -explicit  -93 "../../../../fixed/fixed_util_pkg.vhd"
+vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit  -93 "../src/cic_i_pipe.vhd"
+vcom -explicit  -93 "../src/cic_c_pipe.vhd"
+vcom -explicit  -93 "../src/cic_decim_pipe.vhd"
+vcom -explicit  -93 "../src/tb_cic_decim_pipe.vhd"
+vsim -t 1ps   -lib work tb_cic_decim_pipe
+do {tb_cic_decim_pipe.wdo}
+view wave
+view structure
+view signals
+run 140us
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo
new file mode 100644
index 0000000..637f981
--- /dev/null
+++ b/lib/radio/decimator/CIC/sim/tb_cic_decim_pipe.wdo
@@ -0,0 +1,42 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cic_decim_pipe/clk
+add wave -noupdate -format Logic /tb_cic_decim_pipe/srst
+add wave -noupdate -format Literal /tb_cic_decim_pipe/shift_in
+add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_in
+add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/din
+add wave -noupdate -format Literal /tb_cic_decim_pipe/diff_delay
+add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/ratio
+add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/dout
+add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_out
+add wave -noupdate -divider Debug
+add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_cic_decim_pipe/xr
+add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_cic_decim_pipe/yr
+add wave -noupdate -divider -height 50 Trenn
+add wave -noupdate -format Literal -radix decimal -expand /tb_cic_decim_pipe/uut/word_i_pipe
+add wave -noupdate -format Literal /tb_cic_decim_pipe/uut/vld_i_pipe
+add wave -noupdate -format Logic /tb_cic_decim_pipe/clk
+add wave -noupdate -format Logic /tb_cic_decim_pipe/srst
+add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_in
+add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/din
+add wave -noupdate -format Literal /tb_cic_decim_pipe/diff_delay
+add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/ratio
+add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/dout
+add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_out
+add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/uut/word_c_pipe
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {52266667 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {147 us}
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo b/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo
new file mode 100644
index 0000000..425eb86
--- /dev/null
+++ b/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.fdo
@@ -0,0 +1,13 @@
+vlib work
+vcom -explicit  -93 "../../../../fixed/fixed_pkg_c.vhd"
+vcom -explicit  -93 "../../../../fixed/fixed_util_pkg.vhd"
+vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
+vcom -explicit  -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
+vcom -explicit  -93 "../src/cic_i_pipe.vhd"
+vcom -explicit  -93 "../src/tb_cic_i_pipe.vhd"
+vsim -t 1ps   -lib work tb_cic_i_pipe
+do {tb_cic_i_pipe.wdo}
+view wave
+view structure
+view signals
+run 500ns
diff --git a/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo b/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo
new file mode 100644
index 0000000..140032c
--- /dev/null
+++ b/lib/radio/decimator/CIC/sim/tb_cic_i_pipe.wdo
@@ -0,0 +1,30 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cic_i_pipe/srst
+add wave -noupdate -format Logic /tb_cic_i_pipe/clk
+add wave -noupdate -format Logic /tb_cic_i_pipe/vld_in
+add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/din
+add wave -noupdate -format Logic /tb_cic_i_pipe/vld_out
+add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/dout
+add wave -noupdate -format Logic /tb_cic_i_pipe/srst
+add wave -noupdate -format Logic /tb_cic_i_pipe/clk
+add wave -noupdate -format Logic /tb_cic_i_pipe/vld_in
+add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/din
+add wave -noupdate -format Logic /tb_cic_i_pipe/vld_out
+add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/dout
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {373333 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {0 ps} {1050 ns}
diff --git a/lib/radio/decimator/CIC/src/cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/cic_c_pipe.vhd
new file mode 100644
index 0000000..ac06dd4
--- /dev/null
+++ b/lib/radio/decimator/CIC/src/cic_c_pipe.vhd
@@ -0,0 +1,105 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    12:16:14 10/02/05
+-- Design Name:    
+-- Module Name:    cordic_stage_pre - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity cic_c_pipe is
+Generic
+(
+	max_diff_delay	: integer := 1;
+	max_width		: integer := 32;
+	max_width_frac	: integer := 20;
+	in_width		: integer := 32;
+	in_width_frac	: integer := 20;
+	out_width		: integer := 32;
+	out_width_frac	: integer := 20
+);
+Port
+(
+	clk			: in std_logic;
+	rst			: in std_logic;
+	vld_in		: in std_logic;
+	diff_delay	: in natural range 1 to max_diff_delay;
+	din			: in sfixed;
+	dout		: out sfixed;
+	vld_out 	: out std_logic
+);
+end cic_c_pipe;
+
+architecture Behavioral of cic_c_pipe is
+
+subtype word_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+type word_pipe_t is array (1 to max_diff_delay) of word_t;
+
+signal word_pipe	: word_pipe_t;
+
+------------------------------------------------------------
+begin
+
+------------------------------------------------------------
+delay_pipe_proc: 
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+--				for i in 1 to max_diff_delay loop
+--					word_pipe(i) <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
+--				end loop;
+			elsif vld_in = '1' then
+				word_pipe(1)	<= resize(din, word_pipe(1));
+				for i in 2 to max_diff_delay loop
+					word_pipe(i)	<= word_pipe(i-1);
+				end loop;
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------
+comb_proc: 
+	process(clk)
+	variable x0, x1 : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+	
+	begin
+		if rising_edge(clk) then
+			vld_out <= '0';
+			x0	:= resize(din, x0);
+			x1	:= word_pipe(diff_delay);
+			if rst = '1' then
+				dout <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
+			elsif vld_in = '1' then
+				vld_out <= '1';
+				dout	<= resize(x0 - x1, shi(out_width, out_width_frac), slo(out_width, out_width_frac));
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------
+end Behavioral;
+
diff --git a/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd b/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd
new file mode 100644
index 0000000..ac2b27b
--- /dev/null
+++ b/lib/radio/decimator/CIC/src/cic_decim_pipe.vhd
@@ -0,0 +1,203 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_mix_cpx
+-- Module Name:   tb_mix_cpx.vhd
+-- Project Name:  mix_cpx
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+
+ENTITY cic_decim_pipe IS
+	Generic
+	(
+		nstages			: integer := 3;
+		max_ratio		: integer := 64;
+		max_diff_delay	: integer := 2;
+		max_width		: integer := 32;
+		max_width_frac	: integer := 20;
+		in_width		: integer := 32;
+		in_width_frac	: integer := 20;
+		out_width		: integer := 32;
+		out_width_frac	: integer := 20
+	);
+	Port
+	(
+		clk				: in std_logic;
+		rst				: in std_logic;
+		vld_in			: in std_logic;
+		ratio			: in natural range 1 to max_ratio;
+		diff_delay		: in natural range 1 to max_diff_delay;
+		shift_in		: in natural range 0 to max_width-1;
+		din				: in sfixed;
+		dout			: out sfixed;
+		vld_out 		: out std_logic
+	);
+END cic_decim_pipe;
+
+ARCHITECTURE behavior OF cic_decim_pipe IS 
+
+	COMPONENT cic_i_pipe
+	GENERIC
+	(
+		max_width		: integer;
+		max_width_frac	: integer;
+		in_width		: integer;
+		in_width_frac	: integer;
+		out_width		: integer;
+		out_width_frac	: integer
+	);
+	PORT
+	(
+		clk			: in std_logic;
+		rst			: in std_logic;
+		vld_in		: in std_logic;
+		din			: in sfixed;
+		dout		: out sfixed;
+		vld_out 	: out std_logic
+	);
+	END COMPONENT;
+
+	COMPONENT cic_c_pipe
+	GENERIC
+	(
+		max_diff_delay	: integer;
+		max_width		: integer;
+		max_width_frac	: integer;
+		in_width		: integer;
+		in_width_frac	: integer;
+		out_width		: integer;
+		out_width_frac	: integer
+	);
+	PORT
+	(
+		clk			: in std_logic;
+		rst			: in std_logic;
+		vld_in		: in std_logic;
+		diff_delay	: in natural range 1 to max_diff_delay;
+		din			: in sfixed;
+		dout		: out sfixed;
+		vld_out 	: out std_logic
+	);
+	END COMPONENT;
+
+	subtype word_i_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+	type word_i_pipe_t is array (0 to nstages) of word_i_t;
+
+	signal word_i_pipe	: word_i_pipe_t;
+	signal vld_i_pipe	: unsigned (0 to nstages);
+	signal vld_i		: std_logic;
+	
+	subtype word_c_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+	type word_c_pipe_t is array (0 to nstages) of word_c_t;
+
+	signal word_c_pipe	: word_c_pipe_t;
+	signal vld_c_pipe	: unsigned (0 to nstages);
+	signal vld_c		: std_logic;
+
+	signal resample_cnt	: natural range 1 to max_ratio;
+	signal resample_vld	: std_logic;
+	
+BEGIN
+
+	word_i_pipe(0)	<= resize(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
+	vld_i_pipe(0)	<= vld_in;
+	vld_i			<= vld_i_pipe(nstages);
+	
+	gen_i_stages:
+	for i in 1 to nstages generate
+	begin
+		inst_cic_i_pipe: cic_i_pipe 
+		GENERIC MAP
+		(
+			max_width		=> max_width,
+			max_width_frac	=> max_width_frac,
+			in_width		=> max_width,
+			in_width_frac	=> max_width_frac,
+			out_width		=> max_width,
+			out_width_frac	=> max_width_frac
+		)
+		PORT MAP
+		(
+			clk				=> clk,
+			rst				=> rst,
+			vld_in			=> vld_i_pipe(i-1),
+			din				=> word_i_pipe(i-1),
+			dout			=> word_i_pipe(i),
+			vld_out			=> vld_i_pipe(i)
+		);
+	end generate;
+	
+	word_c_pipe(0)	<= word_i_pipe(nstages);
+	vld_c_pipe(0)	<= resample_vld;
+	vld_c			<= vld_c_pipe(nstages);
+
+	vld_out			<= vld_c;
+	
+	gen_c_stages:
+	for i in 1 to nstages generate
+	begin
+		inst_cic_c_pipe: cic_c_pipe 
+		GENERIC MAP
+		(
+			max_diff_delay	=> max_diff_delay,
+			max_width		=> max_width,
+			max_width_frac	=> max_width_frac,
+			in_width		=> max_width,
+			in_width_frac	=> max_width_frac,
+			out_width		=> max_width,
+			out_width_frac	=> max_width_frac
+		)
+		PORT MAP
+		(
+			clk				=> clk,
+			rst				=> rst,
+			vld_in			=> vld_c_pipe(i-1),
+			diff_delay		=> diff_delay,
+			din				=> word_c_pipe(i-1),
+			dout			=> word_c_pipe(i),
+			vld_out			=> vld_c_pipe(i)
+		);
+	end generate;
+	
+resampler_proc:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			resample_vld	<= '0';
+			if rst = '1' then
+				resample_cnt	<= 1;
+			elsif vld_i = '1' then
+				if resample_cnt = ratio then
+					resample_vld	<= '1';
+					resample_cnt	<= 1;
+				else
+					resample_cnt	<= resample_cnt + 1;
+				end if ;
+			end if;
+		end if;
+	end process;		
+
+dout_registers:
+	process(clk)
+	variable y : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
+	begin
+		if rising_edge(clk) then
+			y		:= resize(word_c_pipe(nstages) sra shift_in, y);
+			dout	<= y;
+		end if;
+	end process;		
+	
+END;
diff --git a/lib/radio/decimator/CIC/src/cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/cic_i_pipe.vhd
new file mode 100644
index 0000000..91db1bb
--- /dev/null
+++ b/lib/radio/decimator/CIC/src/cic_i_pipe.vhd
@@ -0,0 +1,82 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:    12:16:14 10/02/05
+-- Design Name:    
+-- Module Name:    cordic_stage_pre - Behavioral
+-- Project Name:   
+-- Target Device:  
+-- Tool versions:  
+-- Description:
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+--------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+library work;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity cic_i_pipe is
+Generic
+(
+	max_width		: integer := 32;
+	max_width_frac	: integer := 20;
+	in_width		: integer := 32;
+	in_width_frac	: integer := 20;
+	out_width		: integer := 32;
+	out_width_frac	: integer := 20
+);
+Port
+(
+	clk			: in std_logic;
+	rst			: in std_logic;
+	vld_in		: in std_logic;
+	din			: in sfixed;
+	dout		: out sfixed;
+	vld_out 	: out std_logic
+);
+end cic_i_pipe;
+
+architecture Behavioral of cic_i_pipe is
+
+signal accu			: sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+
+------------------------------------------------------------
+begin
+
+	dout	<= resize(accu, shi(out_width, out_width_frac), slo(out_width, out_width_frac));
+	
+------------------------------------------------------------
+integ_proc: 
+	process(clk)
+	variable x : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
+	begin
+		if rising_edge(clk) then
+			vld_out <= '0';
+			if rst = '1' then
+				accu <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
+			elsif vld_in = '1' then
+				vld_out <= '1';
+				x		:= resize(din, x);
+				accu	<= resize(x + accu, accu);
+			end if;	
+		end if;
+	end process;
+
+------------------------------------------------------------
+end Behavioral;
+
diff --git a/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd
new file mode 100644
index 0000000..7fb46c5
--- /dev/null
+++ b/lib/radio/decimator/CIC/src/syn_cic_c_pipe.vhd
@@ -0,0 +1,107 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_mix_cpx
+-- Module Name:   tb_mix_cpx.vhd
+-- Project Name:  mix_cpx
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+
+entity syn_cic_c_pipe is
+Generic
+(
+	max_diff_delay	: integer := 2;
+	max_width		: integer := 32;
+	max_width_frac	: integer := 20;
+	in_width		: integer := 32;
+	in_width_frac	: integer := 20;
+	out_width		: integer := 32;
+	out_width_frac	: integer := 20
+);
+Port
+(
+	clk			: in std_logic;
+	rst			: in std_logic;
+	vld_in		: in std_logic;
+	diff_delay	: in natural range 1 to max_diff_delay;
+	din			: in signed(in_width-1 downto 0);
+	dout		: out signed(out_width-1 downto 0);
+	vld_out 	: out std_logic
+);
+end syn_cic_c_pipe;
+
+ARCHITECTURE behavior OF syn_cic_c_pipe IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT cic_c_pipe
+	GENERIC
+	(
+		max_diff_delay	: integer;
+		max_width		: integer;
+		max_width_frac	: integer;
+		in_width		: integer;
+		in_width_frac	: integer;
+		out_width		: integer;
+		out_width_frac	: integer
+	);
+	PORT
+	(
+		clk			: in std_logic;
+		rst			: in std_logic;
+		vld_in		: in std_logic;
+		diff_delay	: in natural range 1 to max_diff_delay;
+		din			: in sfixed;
+		dout		: out sfixed;
+		vld_out 	: out std_logic
+	);
+	END COMPONENT;
+
+	--Inputs
+	SIGNAL sdin			: sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
+	
+	--Outputs
+	SIGNAL sdout		: sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
+	
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: cic_c_pipe 
+	GENERIC MAP
+	(
+		max_diff_delay	=> max_diff_delay,
+		max_width		=> max_width,
+		max_width_frac	=> max_width_frac,
+		in_width		=> in_width,
+		in_width_frac	=> in_width_frac,
+		out_width		=> out_width,
+		out_width_frac	=> out_width_frac
+	)
+	PORT MAP
+	(
+		clk				=> clk,
+		rst				=> rst,
+		vld_in			=> vld_in,
+		diff_delay		=> diff_delay,
+		din				=> sdin,
+		dout			=> sdout,
+		vld_out			=> vld_out
+	);
+
+	sdin	<= to_sfixed(din, shi(in_width, in_width_frac), slo(in_width, in_width_frac));
+	dout	<= signed(sdout);
+
+END;
diff --git a/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd
new file mode 100644
index 0000000..349134c
--- /dev/null
+++ b/lib/radio/decimator/CIC/src/syn_cic_i_pipe.vhd
@@ -0,0 +1,104 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_mix_cpx
+-- Module Name:   tb_mix_cpx.vhd
+-- Project Name:  mix_cpx
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+
+entity syn_cic_i_pipe is
+Generic
+(
+	max_width		: integer := 32;
+	max_width_frac	: integer := 20;
+	in_width		: integer := 32;
+	in_width_frac	: integer := 20;
+	out_width		: integer := 32;
+	out_width_frac	: integer := 20
+);
+Port
+(
+	clk			: in std_logic;
+	rst			: in std_logic;
+	vld_in		: in std_logic;
+	shamt		: in natural range 0 to max_width-1;
+	din			: in signed(in_width-1 downto 0);
+	dout		: out signed(out_width-1 downto 0);
+	vld_out 	: out std_logic
+);
+end syn_cic_i_pipe;
+
+ARCHITECTURE behavior OF syn_cic_i_pipe IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT cic_i_pipe
+	GENERIC
+	(
+		max_width		: integer;
+		max_width_frac	: integer;
+		in_width		: integer;
+		in_width_frac	: integer;
+		out_width		: integer;
+		out_width_frac	: integer
+	);
+	PORT
+	(
+		clk			: in std_logic;
+		rst			: in std_logic;
+		vld_in		: in std_logic;
+		shamt		: in natural range 0 to max_width-1;
+		din			: in sfixed;
+		dout		: out sfixed;
+		vld_out 	: out std_logic
+	);
+	END COMPONENT;
+
+	--Inputs
+	SIGNAL sdin			: sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
+	
+	--Outputs
+	SIGNAL sdout		: sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
+	
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: cic_i_pipe 
+	GENERIC MAP
+	(
+		max_width		=> max_width,
+		max_width_frac	=> max_width_frac,
+		in_width		=> in_width,
+		in_width_frac	=> in_width_frac,
+		out_width		=> out_width,
+		out_width_frac	=> out_width_frac
+	)
+	PORT MAP
+	(
+		clk				=> clk,
+		rst				=> rst,
+		vld_in			=> vld_in,
+		shamt			=> shamt,
+		din				=> sdin,
+		dout			=> sdout,
+		vld_out			=> vld_out
+	);
+
+	sdin	<= to_sfixed(din, shi(in_width, in_width_frac), slo(in_width, in_width_frac));
+	dout	<= signed(sdout);
+
+END;
diff --git a/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd
new file mode 100644
index 0000000..778bdb9
--- /dev/null
+++ b/lib/radio/decimator/CIC/src/tb_cic_c_pipe.vhd
@@ -0,0 +1,145 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_mix_cpx
+-- Module Name:   tb_mix_cpx.vhd
+-- Project Name:  mix_cpx
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.PCK_FIO.all;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+
+ENTITY tb_cic_c_pipe IS
+	Generic
+	(
+		max_width		: integer := 32;
+		max_width_frac	: integer := 20;
+		in_width		: integer := 32;
+		in_width_frac	: integer := 20;
+		out_width		: integer := 32;
+		out_width_frac	: integer := 20
+	);
+END tb_cic_c_pipe;
+
+ARCHITECTURE behavior OF tb_cic_c_pipe IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT cic_c_pipe
+	GENERIC
+	(
+		max_diff_delay	: integer;
+		max_width		: integer;
+		max_width_frac	: integer;
+		in_width		: integer;
+		in_width_frac	: integer;
+		out_width		: integer;
+		out_width_frac	: integer
+	);
+	PORT
+	(
+		clk			: in std_logic;
+		rst			: in std_logic;
+		vld_in		: in std_logic;
+		diff_delay	: in natural range 1 to max_diff_delay;
+		din			: in sfixed;
+		dout		: out sfixed;
+		vld_out 	: out std_logic
+	);
+	END COMPONENT;
+
+	--Constants
+	constant PERIOD : time := 10 ns;
+	
+
+	--Inputs
+	SIGNAL clk			: std_logic := '0';
+	SIGNAL srst			: std_logic := '1';
+	SIGNAL vld_in		: std_logic := '0';
+	SIGNAL din			: sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
+	SIGNAL diff_delay	: natural := 1;
+	
+	--Outputs
+	SIGNAL dout			: sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
+	SIGNAL vld_out		: std_logic;
+	
+	SIGNAL fileout_enable   : std_logic := '0';
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: cic_c_pipe 
+	GENERIC MAP
+	(
+		max_diff_delay	=> 2,
+		max_width		=> max_width,
+		max_width_frac	=> max_width_frac,
+		in_width		=> in_width,
+		in_width_frac	=> in_width_frac,
+		out_width		=> out_width,
+		out_width_frac	=> out_width_frac
+	)
+	PORT MAP
+	(
+		clk				=> clk,
+		rst				=> srst,
+		vld_in			=> vld_in,
+		diff_delay		=> diff_delay,
+		din				=> din,
+		dout			=> dout,
+		vld_out			=> vld_out
+	);
+
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+	tb : PROCESS
+
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 4*PERIOD;
+		srst <= '0';
+		------------------------------------------
+		wait for 2*PERIOD;
+		wait until rising_edge(clk);
+		din		<= to_sfixed(0.0, din, false, true);
+		vld_in	<= '1';
+
+		wait for 9*PERIOD;
+		wait until rising_edge(clk);
+
+		din		<= to_sfixed(0.5, din, false, true);
+
+		wait for 9*PERIOD;
+		wait until rising_edge(clk);
+
+		din		<= to_sfixed(0.0, din, false, true);
+
+		wait for 9*PERIOD;
+		wait until rising_edge(clk);
+		vld_in	<= '0';
+
+		wait for 20*PERIOD;
+
+		assert false report "Test finished" severity error;
+		wait; 
+	END PROCESS;
+	
+END;
diff --git a/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd
new file mode 100644
index 0000000..b636a1e
--- /dev/null
+++ b/lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd
@@ -0,0 +1,165 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_mix_cpx
+-- Module Name:   tb_mix_cpx.vhd
+-- Project Name:  mix_cpx
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.PCK_FIO.all;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+
+ENTITY tb_cic_decim_pipe IS
+	Generic
+	(
+		nstages			: integer := 3;
+		max_ratio		: integer := 4096;
+		max_diff_delay	: integer := 2;
+		max_width		: integer := 36;
+		max_width_frac	: integer := 16;
+		in_width		: integer := 18;
+		in_width_frac	: integer := 16;
+		out_width		: integer := 18;
+		out_width_frac	: integer := 16
+	);
+END tb_cic_decim_pipe;
+
+ARCHITECTURE behavior OF tb_cic_decim_pipe IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT cic_decim_pipe
+	GENERIC
+	(
+		nstages			: integer;
+		max_ratio		: integer;
+		max_diff_delay	: integer;
+		max_width		: integer;
+		max_width_frac	: integer;
+		in_width		: integer;
+		in_width_frac	: integer;
+		out_width		: integer;
+		out_width_frac	: integer
+	);
+	PORT
+	(
+		clk				: in std_logic;
+		rst				: in std_logic;
+		vld_in			: in std_logic;
+		ratio			: in natural range 1 to max_ratio;
+		diff_delay		: in natural range 1 to max_diff_delay;
+		shift_in		: in natural range 0 to max_width-1;
+		din				: in sfixed;
+		dout			: out sfixed;
+		vld_out 		: out std_logic
+	);
+	END COMPONENT;
+
+	--Constants
+	constant PERIOD : time := 10 ns;
+	
+
+	--Inputs
+	SIGNAL clk				: std_logic := '0';
+	SIGNAL srst				: std_logic := '1';
+	SIGNAL vld_in			: std_logic := '0';
+	SIGNAL din				: sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
+	SIGNAL diff_delay		: natural := 1;
+	SIGNAL ratio			: natural := 64;
+	SIGNAL shift_in			: natural := 18;
+	
+	--Outputs
+	SIGNAL dout				: sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
+	SIGNAL vld_out			: std_logic;
+	
+	SIGNAL fileout_enable   : std_logic := '0';
+
+	signal XR, YR		: real;
+	
+BEGIN
+
+	XR	<= to_real(din);
+	YR	<= to_real(dout);
+	
+	-- Instantiate the Unit Under Test (UUT)
+	uut : cic_decim_pipe
+	GENERIC MAP
+	(
+		nstages			=> nstages,
+		max_ratio		=> max_ratio,
+		max_diff_delay	=> max_diff_delay,
+		max_width		=> max_width,
+		max_width_frac	=> max_width_frac,
+		in_width		=> in_width,
+		in_width_frac	=> in_width_frac,
+		out_width		=> out_width,
+		out_width_frac	=> out_width_frac
+	)
+	PORT MAP
+	(
+		clk				=> clk,
+		rst				=> srst,
+		vld_in			=> vld_in,
+		ratio			=> ratio,
+		diff_delay		=> diff_delay,
+		shift_in		=> shift_in,
+		din				=> din,
+		dout			=> dout,
+		vld_out			=> vld_out
+	);
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+	tb : PROCESS
+
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 4*PERIOD;
+		srst <= '0';
+		
+		------------------------------------------
+		wait for 2*PERIOD;
+		wait until rising_edge(clk);
+		din		<= to_sfixed(0.0, din, false, true);
+		vld_in	<= '1';
+
+		wait for 49*PERIOD;
+		wait until rising_edge(clk);
+
+		din		<= to_sfixed(0.5, din, false, true);
+
+		wait for 4999*PERIOD;
+		wait until rising_edge(clk);
+
+		din		<= to_sfixed(-0.5, din, false, true);
+
+		wait for 99*PERIOD;
+		wait until rising_edge(clk);
+
+		din		<= to_sfixed(0.0, din, false, true);
+
+		wait for 499*PERIOD;
+		wait until rising_edge(clk);
+		vld_in	<= '0';
+
+		wait; 
+	END PROCESS;
+	
+END;
diff --git a/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd b/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd
new file mode 100644
index 0000000..4efba2a
--- /dev/null
+++ b/lib/radio/decimator/CIC/src/tb_cic_i_pipe.vhd
@@ -0,0 +1,135 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:16:42 13.05.2007
+-- Design Name:   tb_mix_cpx
+-- Module Name:   tb_mix_cpx.vhd
+-- Project Name:  mix_cpx
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.MATH_REAL.ALL;
+USE ieee.numeric_std.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.PCK_FIO.all;
+use work.fixed_pkg.all;
+use work.fixed_util_pkg.all;
+
+ENTITY tb_cic_i_pipe IS
+	Generic
+	(
+		max_width		: integer := 32;
+		max_width_frac	: integer := 20;
+		in_width		: integer := 32;
+		in_width_frac	: integer := 20;
+		out_width		: integer := 32;
+		out_width_frac	: integer := 20
+	);
+END tb_cic_i_pipe;
+
+ARCHITECTURE behavior OF tb_cic_i_pipe IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT cic_i_pipe
+	GENERIC
+	(
+		max_width		: integer;
+		max_width_frac	: integer;
+		in_width		: integer;
+		in_width_frac	: integer;
+		out_width		: integer;
+		out_width_frac	: integer
+	);
+	PORT
+	(
+		clk			: in std_logic;
+		rst			: in std_logic;
+		vld_in		: in std_logic;
+		din			: in sfixed;
+		dout		: out sfixed;
+		vld_out 	: out std_logic
+	);
+	END COMPONENT;
+
+	--Constants
+	constant PERIOD : time := 10 ns;
+	
+
+	--Inputs
+	SIGNAL clk			: std_logic := '0';
+	SIGNAL srst			: std_logic := '1';
+	SIGNAL vld_in		: std_logic := '0';
+	SIGNAL din			: sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
+	
+	--Outputs
+	SIGNAL dout			: sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
+	SIGNAL vld_out		: std_logic;
+	
+	SIGNAL fileout_enable   : std_logic := '0';
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: cic_i_pipe 
+	GENERIC MAP
+	(
+		max_width		=> max_width,
+		max_width_frac	=> max_width_frac,
+		in_width		=> in_width,
+		in_width_frac	=> in_width_frac,
+		out_width		=> out_width,
+		out_width_frac	=> out_width_frac
+	)
+	PORT MAP
+	(
+		clk				=> clk,
+		rst				=> srst,
+		vld_in			=> vld_in,
+		din				=> din,
+		dout			=> dout,
+		vld_out			=> vld_out
+	);
+
+
+ 	tb_clk : PROCESS
+	BEGIN
+		clk <= not clk;
+		wait for PERIOD/2;
+	END PROCESS;
+
+	tb : PROCESS
+
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 4*PERIOD;
+		srst <= '0';
+		------------------------------------------
+		wait for 2*PERIOD;
+		wait until rising_edge(clk);
+		din		<= to_sfixed(0.0, din, false, true);
+		vld_in	<= '1';
+
+		wait for 9*PERIOD;
+		wait until rising_edge(clk);
+
+		din		<= to_sfixed(0.5, din, false, true);
+
+		wait for 9*PERIOD;
+		wait until rising_edge(clk);
+		vld_in	<= '0';
+
+		wait for 20*PERIOD;
+
+		assert false report "Test finished" severity error;
+		wait; 
+	END PROCESS;
+	
+END;