- Intital revision
git-svn-id: http://moon:8086/svn/vhdl/trunk@166 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,13 @@
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../../fixed/fixed_pkg_c.vhd"
|
||||
vcom -explicit -93 "../../../../fixed/fixed_util_pkg.vhd"
|
||||
vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
|
||||
vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
|
||||
vcom -explicit -93 "../src/cic_c_pipe.vhd"
|
||||
vcom -explicit -93 "../src/tb_cic_c_pipe.vhd"
|
||||
vsim -t 1ps -lib work tb_cic_c_pipe
|
||||
do {tb_cic_c_pipe.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 500ns
|
||||
@@ -0,0 +1,26 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cic_c_pipe/clk
|
||||
add wave -noupdate -format Logic /tb_cic_c_pipe/srst
|
||||
add wave -noupdate -format Logic /tb_cic_c_pipe/vld_in
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/din
|
||||
add wave -noupdate -format Literal /tb_cic_c_pipe/diff_delay
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/dout
|
||||
add wave -noupdate -format Logic /tb_cic_c_pipe/vld_out
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_c_pipe/uut/word_pipe
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {250000 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {500608 ps}
|
||||
@@ -0,0 +1,15 @@
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../../fixed/fixed_pkg_c.vhd"
|
||||
vcom -explicit -93 "../../../../fixed/fixed_util_pkg.vhd"
|
||||
vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
|
||||
vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
|
||||
vcom -explicit -93 "../src/cic_i_pipe.vhd"
|
||||
vcom -explicit -93 "../src/cic_c_pipe.vhd"
|
||||
vcom -explicit -93 "../src/cic_decim_pipe.vhd"
|
||||
vcom -explicit -93 "../src/tb_cic_decim_pipe.vhd"
|
||||
vsim -t 1ps -lib work tb_cic_decim_pipe
|
||||
do {tb_cic_decim_pipe.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 140us
|
||||
@@ -0,0 +1,42 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cic_decim_pipe/clk
|
||||
add wave -noupdate -format Logic /tb_cic_decim_pipe/srst
|
||||
add wave -noupdate -format Literal /tb_cic_decim_pipe/shift_in
|
||||
add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_in
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/din
|
||||
add wave -noupdate -format Literal /tb_cic_decim_pipe/diff_delay
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/ratio
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/dout
|
||||
add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_out
|
||||
add wave -noupdate -divider Debug
|
||||
add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_cic_decim_pipe/xr
|
||||
add wave -noupdate -format Analog-Step -height 50 -scale 50.0 /tb_cic_decim_pipe/yr
|
||||
add wave -noupdate -divider -height 50 Trenn
|
||||
add wave -noupdate -format Literal -radix decimal -expand /tb_cic_decim_pipe/uut/word_i_pipe
|
||||
add wave -noupdate -format Literal /tb_cic_decim_pipe/uut/vld_i_pipe
|
||||
add wave -noupdate -format Logic /tb_cic_decim_pipe/clk
|
||||
add wave -noupdate -format Logic /tb_cic_decim_pipe/srst
|
||||
add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_in
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/din
|
||||
add wave -noupdate -format Literal /tb_cic_decim_pipe/diff_delay
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/ratio
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/dout
|
||||
add wave -noupdate -format Logic /tb_cic_decim_pipe/vld_out
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_decim_pipe/uut/word_c_pipe
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {52266667 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {147 us}
|
||||
@@ -0,0 +1,13 @@
|
||||
vlib work
|
||||
vcom -explicit -93 "../../../../fixed/fixed_pkg_c.vhd"
|
||||
vcom -explicit -93 "../../../../fixed/fixed_util_pkg.vhd"
|
||||
vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd"
|
||||
vcom -explicit -93 "../../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd"
|
||||
vcom -explicit -93 "../src/cic_i_pipe.vhd"
|
||||
vcom -explicit -93 "../src/tb_cic_i_pipe.vhd"
|
||||
vsim -t 1ps -lib work tb_cic_i_pipe
|
||||
do {tb_cic_i_pipe.wdo}
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run 500ns
|
||||
@@ -0,0 +1,30 @@
|
||||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -format Logic /tb_cic_i_pipe/srst
|
||||
add wave -noupdate -format Logic /tb_cic_i_pipe/clk
|
||||
add wave -noupdate -format Logic /tb_cic_i_pipe/vld_in
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/din
|
||||
add wave -noupdate -format Logic /tb_cic_i_pipe/vld_out
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/dout
|
||||
add wave -noupdate -format Logic /tb_cic_i_pipe/srst
|
||||
add wave -noupdate -format Logic /tb_cic_i_pipe/clk
|
||||
add wave -noupdate -format Logic /tb_cic_i_pipe/vld_in
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/din
|
||||
add wave -noupdate -format Logic /tb_cic_i_pipe/vld_out
|
||||
add wave -noupdate -format Literal -radix decimal /tb_cic_i_pipe/dout
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {373333 ps} 0}
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 100
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 1
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {1050 ns}
|
||||
@@ -0,0 +1,105 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:16:14 10/02/05
|
||||
-- Design Name:
|
||||
-- Module Name: cordic_stage_pre - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.fixed_util_pkg.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity cic_c_pipe is
|
||||
Generic
|
||||
(
|
||||
max_diff_delay : integer := 1;
|
||||
max_width : integer := 32;
|
||||
max_width_frac : integer := 20;
|
||||
in_width : integer := 32;
|
||||
in_width_frac : integer := 20;
|
||||
out_width : integer := 32;
|
||||
out_width_frac : integer := 20
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
diff_delay : in natural range 1 to max_diff_delay;
|
||||
din : in sfixed;
|
||||
dout : out sfixed;
|
||||
vld_out : out std_logic
|
||||
);
|
||||
end cic_c_pipe;
|
||||
|
||||
architecture Behavioral of cic_c_pipe is
|
||||
|
||||
subtype word_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
|
||||
type word_pipe_t is array (1 to max_diff_delay) of word_t;
|
||||
|
||||
signal word_pipe : word_pipe_t;
|
||||
|
||||
------------------------------------------------------------
|
||||
begin
|
||||
|
||||
------------------------------------------------------------
|
||||
delay_pipe_proc:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if rst = '1' then
|
||||
-- for i in 1 to max_diff_delay loop
|
||||
-- word_pipe(i) <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
|
||||
-- end loop;
|
||||
elsif vld_in = '1' then
|
||||
word_pipe(1) <= resize(din, word_pipe(1));
|
||||
for i in 2 to max_diff_delay loop
|
||||
word_pipe(i) <= word_pipe(i-1);
|
||||
end loop;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
comb_proc:
|
||||
process(clk)
|
||||
variable x0, x1 : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
|
||||
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
vld_out <= '0';
|
||||
x0 := resize(din, x0);
|
||||
x1 := word_pipe(diff_delay);
|
||||
if rst = '1' then
|
||||
dout <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
|
||||
elsif vld_in = '1' then
|
||||
vld_out <= '1';
|
||||
dout <= resize(x0 - x1, shi(out_width, out_width_frac), slo(out_width, out_width_frac));
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,203 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.fixed_util_pkg.all;
|
||||
|
||||
ENTITY cic_decim_pipe IS
|
||||
Generic
|
||||
(
|
||||
nstages : integer := 3;
|
||||
max_ratio : integer := 64;
|
||||
max_diff_delay : integer := 2;
|
||||
max_width : integer := 32;
|
||||
max_width_frac : integer := 20;
|
||||
in_width : integer := 32;
|
||||
in_width_frac : integer := 20;
|
||||
out_width : integer := 32;
|
||||
out_width_frac : integer := 20
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
ratio : in natural range 1 to max_ratio;
|
||||
diff_delay : in natural range 1 to max_diff_delay;
|
||||
shift_in : in natural range 0 to max_width-1;
|
||||
din : in sfixed;
|
||||
dout : out sfixed;
|
||||
vld_out : out std_logic
|
||||
);
|
||||
END cic_decim_pipe;
|
||||
|
||||
ARCHITECTURE behavior OF cic_decim_pipe IS
|
||||
|
||||
COMPONENT cic_i_pipe
|
||||
GENERIC
|
||||
(
|
||||
max_width : integer;
|
||||
max_width_frac : integer;
|
||||
in_width : integer;
|
||||
in_width_frac : integer;
|
||||
out_width : integer;
|
||||
out_width_frac : integer
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
din : in sfixed;
|
||||
dout : out sfixed;
|
||||
vld_out : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT cic_c_pipe
|
||||
GENERIC
|
||||
(
|
||||
max_diff_delay : integer;
|
||||
max_width : integer;
|
||||
max_width_frac : integer;
|
||||
in_width : integer;
|
||||
in_width_frac : integer;
|
||||
out_width : integer;
|
||||
out_width_frac : integer
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
diff_delay : in natural range 1 to max_diff_delay;
|
||||
din : in sfixed;
|
||||
dout : out sfixed;
|
||||
vld_out : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
subtype word_i_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
|
||||
type word_i_pipe_t is array (0 to nstages) of word_i_t;
|
||||
|
||||
signal word_i_pipe : word_i_pipe_t;
|
||||
signal vld_i_pipe : unsigned (0 to nstages);
|
||||
signal vld_i : std_logic;
|
||||
|
||||
subtype word_c_t is sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
|
||||
type word_c_pipe_t is array (0 to nstages) of word_c_t;
|
||||
|
||||
signal word_c_pipe : word_c_pipe_t;
|
||||
signal vld_c_pipe : unsigned (0 to nstages);
|
||||
signal vld_c : std_logic;
|
||||
|
||||
signal resample_cnt : natural range 1 to max_ratio;
|
||||
signal resample_vld : std_logic;
|
||||
|
||||
BEGIN
|
||||
|
||||
word_i_pipe(0) <= resize(din, shi(max_width, max_width_frac), slo(max_width, max_width_frac));
|
||||
vld_i_pipe(0) <= vld_in;
|
||||
vld_i <= vld_i_pipe(nstages);
|
||||
|
||||
gen_i_stages:
|
||||
for i in 1 to nstages generate
|
||||
begin
|
||||
inst_cic_i_pipe: cic_i_pipe
|
||||
GENERIC MAP
|
||||
(
|
||||
max_width => max_width,
|
||||
max_width_frac => max_width_frac,
|
||||
in_width => max_width,
|
||||
in_width_frac => max_width_frac,
|
||||
out_width => max_width,
|
||||
out_width_frac => max_width_frac
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
vld_in => vld_i_pipe(i-1),
|
||||
din => word_i_pipe(i-1),
|
||||
dout => word_i_pipe(i),
|
||||
vld_out => vld_i_pipe(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
word_c_pipe(0) <= word_i_pipe(nstages);
|
||||
vld_c_pipe(0) <= resample_vld;
|
||||
vld_c <= vld_c_pipe(nstages);
|
||||
|
||||
vld_out <= vld_c;
|
||||
|
||||
gen_c_stages:
|
||||
for i in 1 to nstages generate
|
||||
begin
|
||||
inst_cic_c_pipe: cic_c_pipe
|
||||
GENERIC MAP
|
||||
(
|
||||
max_diff_delay => max_diff_delay,
|
||||
max_width => max_width,
|
||||
max_width_frac => max_width_frac,
|
||||
in_width => max_width,
|
||||
in_width_frac => max_width_frac,
|
||||
out_width => max_width,
|
||||
out_width_frac => max_width_frac
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
vld_in => vld_c_pipe(i-1),
|
||||
diff_delay => diff_delay,
|
||||
din => word_c_pipe(i-1),
|
||||
dout => word_c_pipe(i),
|
||||
vld_out => vld_c_pipe(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
resampler_proc:
|
||||
process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
resample_vld <= '0';
|
||||
if rst = '1' then
|
||||
resample_cnt <= 1;
|
||||
elsif vld_i = '1' then
|
||||
if resample_cnt = ratio then
|
||||
resample_vld <= '1';
|
||||
resample_cnt <= 1;
|
||||
else
|
||||
resample_cnt <= resample_cnt + 1;
|
||||
end if ;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
dout_registers:
|
||||
process(clk)
|
||||
variable y : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
y := resize(word_c_pipe(nstages) sra shift_in, y);
|
||||
dout <= y;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,82 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 12:16:14 10/02/05
|
||||
-- Design Name:
|
||||
-- Module Name: cordic_stage_pre - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY IEEE;
|
||||
USE IEEE.STD_LOGIC_1164.ALL;
|
||||
USE IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.fixed_util_pkg.all;
|
||||
|
||||
---- Uncomment the following library declaration if instantiating
|
||||
---- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity cic_i_pipe is
|
||||
Generic
|
||||
(
|
||||
max_width : integer := 32;
|
||||
max_width_frac : integer := 20;
|
||||
in_width : integer := 32;
|
||||
in_width_frac : integer := 20;
|
||||
out_width : integer := 32;
|
||||
out_width_frac : integer := 20
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
din : in sfixed;
|
||||
dout : out sfixed;
|
||||
vld_out : out std_logic
|
||||
);
|
||||
end cic_i_pipe;
|
||||
|
||||
architecture Behavioral of cic_i_pipe is
|
||||
|
||||
signal accu : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
|
||||
|
||||
------------------------------------------------------------
|
||||
begin
|
||||
|
||||
dout <= resize(accu, shi(out_width, out_width_frac), slo(out_width, out_width_frac));
|
||||
|
||||
------------------------------------------------------------
|
||||
integ_proc:
|
||||
process(clk)
|
||||
variable x : sfixed(shi(max_width, max_width_frac) downto slo(max_width, max_width_frac));
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
vld_out <= '0';
|
||||
if rst = '1' then
|
||||
accu <= (shi(max_width, max_width_frac) downto slo(max_width, max_width_frac) => '0');
|
||||
elsif vld_in = '1' then
|
||||
vld_out <= '1';
|
||||
x := resize(din, x);
|
||||
accu <= resize(x + accu, accu);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
------------------------------------------------------------
|
||||
end Behavioral;
|
||||
|
||||
@@ -0,0 +1,107 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.fixed_util_pkg.all;
|
||||
|
||||
entity syn_cic_c_pipe is
|
||||
Generic
|
||||
(
|
||||
max_diff_delay : integer := 2;
|
||||
max_width : integer := 32;
|
||||
max_width_frac : integer := 20;
|
||||
in_width : integer := 32;
|
||||
in_width_frac : integer := 20;
|
||||
out_width : integer := 32;
|
||||
out_width_frac : integer := 20
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
diff_delay : in natural range 1 to max_diff_delay;
|
||||
din : in signed(in_width-1 downto 0);
|
||||
dout : out signed(out_width-1 downto 0);
|
||||
vld_out : out std_logic
|
||||
);
|
||||
end syn_cic_c_pipe;
|
||||
|
||||
ARCHITECTURE behavior OF syn_cic_c_pipe IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT cic_c_pipe
|
||||
GENERIC
|
||||
(
|
||||
max_diff_delay : integer;
|
||||
max_width : integer;
|
||||
max_width_frac : integer;
|
||||
in_width : integer;
|
||||
in_width_frac : integer;
|
||||
out_width : integer;
|
||||
out_width_frac : integer
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
diff_delay : in natural range 1 to max_diff_delay;
|
||||
din : in sfixed;
|
||||
dout : out sfixed;
|
||||
vld_out : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Inputs
|
||||
SIGNAL sdin : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
|
||||
|
||||
--Outputs
|
||||
SIGNAL sdout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: cic_c_pipe
|
||||
GENERIC MAP
|
||||
(
|
||||
max_diff_delay => max_diff_delay,
|
||||
max_width => max_width,
|
||||
max_width_frac => max_width_frac,
|
||||
in_width => in_width,
|
||||
in_width_frac => in_width_frac,
|
||||
out_width => out_width,
|
||||
out_width_frac => out_width_frac
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
vld_in => vld_in,
|
||||
diff_delay => diff_delay,
|
||||
din => sdin,
|
||||
dout => sdout,
|
||||
vld_out => vld_out
|
||||
);
|
||||
|
||||
sdin <= to_sfixed(din, shi(in_width, in_width_frac), slo(in_width, in_width_frac));
|
||||
dout <= signed(sdout);
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,104 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.fixed_pkg.all;
|
||||
use work.fixed_util_pkg.all;
|
||||
|
||||
entity syn_cic_i_pipe is
|
||||
Generic
|
||||
(
|
||||
max_width : integer := 32;
|
||||
max_width_frac : integer := 20;
|
||||
in_width : integer := 32;
|
||||
in_width_frac : integer := 20;
|
||||
out_width : integer := 32;
|
||||
out_width_frac : integer := 20
|
||||
);
|
||||
Port
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
shamt : in natural range 0 to max_width-1;
|
||||
din : in signed(in_width-1 downto 0);
|
||||
dout : out signed(out_width-1 downto 0);
|
||||
vld_out : out std_logic
|
||||
);
|
||||
end syn_cic_i_pipe;
|
||||
|
||||
ARCHITECTURE behavior OF syn_cic_i_pipe IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT cic_i_pipe
|
||||
GENERIC
|
||||
(
|
||||
max_width : integer;
|
||||
max_width_frac : integer;
|
||||
in_width : integer;
|
||||
in_width_frac : integer;
|
||||
out_width : integer;
|
||||
out_width_frac : integer
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
shamt : in natural range 0 to max_width-1;
|
||||
din : in sfixed;
|
||||
dout : out sfixed;
|
||||
vld_out : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Inputs
|
||||
SIGNAL sdin : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
|
||||
|
||||
--Outputs
|
||||
SIGNAL sdout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: cic_i_pipe
|
||||
GENERIC MAP
|
||||
(
|
||||
max_width => max_width,
|
||||
max_width_frac => max_width_frac,
|
||||
in_width => in_width,
|
||||
in_width_frac => in_width_frac,
|
||||
out_width => out_width,
|
||||
out_width_frac => out_width_frac
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
vld_in => vld_in,
|
||||
shamt => shamt,
|
||||
din => sdin,
|
||||
dout => sdout,
|
||||
vld_out => vld_out
|
||||
);
|
||||
|
||||
sdin <= to_sfixed(din, shi(in_width, in_width_frac), slo(in_width, in_width_frac));
|
||||
dout <= signed(sdout);
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,145 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.PCK_FIO.all;
|
||||
use work.fixed_pkg.all;
|
||||
use work.fixed_util_pkg.all;
|
||||
|
||||
ENTITY tb_cic_c_pipe IS
|
||||
Generic
|
||||
(
|
||||
max_width : integer := 32;
|
||||
max_width_frac : integer := 20;
|
||||
in_width : integer := 32;
|
||||
in_width_frac : integer := 20;
|
||||
out_width : integer := 32;
|
||||
out_width_frac : integer := 20
|
||||
);
|
||||
END tb_cic_c_pipe;
|
||||
|
||||
ARCHITECTURE behavior OF tb_cic_c_pipe IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT cic_c_pipe
|
||||
GENERIC
|
||||
(
|
||||
max_diff_delay : integer;
|
||||
max_width : integer;
|
||||
max_width_frac : integer;
|
||||
in_width : integer;
|
||||
in_width_frac : integer;
|
||||
out_width : integer;
|
||||
out_width_frac : integer
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
diff_delay : in natural range 1 to max_diff_delay;
|
||||
din : in sfixed;
|
||||
dout : out sfixed;
|
||||
vld_out : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL vld_in : std_logic := '0';
|
||||
SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
|
||||
SIGNAL diff_delay : natural := 1;
|
||||
|
||||
--Outputs
|
||||
SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
|
||||
SIGNAL vld_out : std_logic;
|
||||
|
||||
SIGNAL fileout_enable : std_logic := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: cic_c_pipe
|
||||
GENERIC MAP
|
||||
(
|
||||
max_diff_delay => 2,
|
||||
max_width => max_width,
|
||||
max_width_frac => max_width_frac,
|
||||
in_width => in_width,
|
||||
in_width_frac => in_width_frac,
|
||||
out_width => out_width,
|
||||
out_width_frac => out_width_frac
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
rst => srst,
|
||||
vld_in => vld_in,
|
||||
diff_delay => diff_delay,
|
||||
din => din,
|
||||
dout => dout,
|
||||
vld_out => vld_out
|
||||
);
|
||||
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
din <= to_sfixed(0.0, din, false, true);
|
||||
vld_in <= '1';
|
||||
|
||||
wait for 9*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
din <= to_sfixed(0.5, din, false, true);
|
||||
|
||||
wait for 9*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
din <= to_sfixed(0.0, din, false, true);
|
||||
|
||||
wait for 9*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
vld_in <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,165 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.PCK_FIO.all;
|
||||
use work.fixed_pkg.all;
|
||||
use work.fixed_util_pkg.all;
|
||||
|
||||
ENTITY tb_cic_decim_pipe IS
|
||||
Generic
|
||||
(
|
||||
nstages : integer := 3;
|
||||
max_ratio : integer := 4096;
|
||||
max_diff_delay : integer := 2;
|
||||
max_width : integer := 36;
|
||||
max_width_frac : integer := 16;
|
||||
in_width : integer := 18;
|
||||
in_width_frac : integer := 16;
|
||||
out_width : integer := 18;
|
||||
out_width_frac : integer := 16
|
||||
);
|
||||
END tb_cic_decim_pipe;
|
||||
|
||||
ARCHITECTURE behavior OF tb_cic_decim_pipe IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT cic_decim_pipe
|
||||
GENERIC
|
||||
(
|
||||
nstages : integer;
|
||||
max_ratio : integer;
|
||||
max_diff_delay : integer;
|
||||
max_width : integer;
|
||||
max_width_frac : integer;
|
||||
in_width : integer;
|
||||
in_width_frac : integer;
|
||||
out_width : integer;
|
||||
out_width_frac : integer
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
ratio : in natural range 1 to max_ratio;
|
||||
diff_delay : in natural range 1 to max_diff_delay;
|
||||
shift_in : in natural range 0 to max_width-1;
|
||||
din : in sfixed;
|
||||
dout : out sfixed;
|
||||
vld_out : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL vld_in : std_logic := '0';
|
||||
SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
|
||||
SIGNAL diff_delay : natural := 1;
|
||||
SIGNAL ratio : natural := 64;
|
||||
SIGNAL shift_in : natural := 18;
|
||||
|
||||
--Outputs
|
||||
SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
|
||||
SIGNAL vld_out : std_logic;
|
||||
|
||||
SIGNAL fileout_enable : std_logic := '0';
|
||||
|
||||
signal XR, YR : real;
|
||||
|
||||
BEGIN
|
||||
|
||||
XR <= to_real(din);
|
||||
YR <= to_real(dout);
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut : cic_decim_pipe
|
||||
GENERIC MAP
|
||||
(
|
||||
nstages => nstages,
|
||||
max_ratio => max_ratio,
|
||||
max_diff_delay => max_diff_delay,
|
||||
max_width => max_width,
|
||||
max_width_frac => max_width_frac,
|
||||
in_width => in_width,
|
||||
in_width_frac => in_width_frac,
|
||||
out_width => out_width,
|
||||
out_width_frac => out_width_frac
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
rst => srst,
|
||||
vld_in => vld_in,
|
||||
ratio => ratio,
|
||||
diff_delay => diff_delay,
|
||||
shift_in => shift_in,
|
||||
din => din,
|
||||
dout => dout,
|
||||
vld_out => vld_out
|
||||
);
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
din <= to_sfixed(0.0, din, false, true);
|
||||
vld_in <= '1';
|
||||
|
||||
wait for 49*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
din <= to_sfixed(0.5, din, false, true);
|
||||
|
||||
wait for 4999*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
din <= to_sfixed(-0.5, din, false, true);
|
||||
|
||||
wait for 99*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
din <= to_sfixed(0.0, din, false, true);
|
||||
|
||||
wait for 499*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
vld_in <= '0';
|
||||
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
END;
|
||||
@@ -0,0 +1,135 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 17:16:42 13.05.2007
|
||||
-- Design Name: tb_mix_cpx
|
||||
-- Module Name: tb_mix_cpx.vhd
|
||||
-- Project Name: mix_cpx
|
||||
-- Target Device:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
LIBRARY ieee;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.MATH_REAL.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
use std.textio.all; -- Imports the standard textio package.
|
||||
|
||||
library work;
|
||||
use work.PCK_FIO.all;
|
||||
use work.fixed_pkg.all;
|
||||
use work.fixed_util_pkg.all;
|
||||
|
||||
ENTITY tb_cic_i_pipe IS
|
||||
Generic
|
||||
(
|
||||
max_width : integer := 32;
|
||||
max_width_frac : integer := 20;
|
||||
in_width : integer := 32;
|
||||
in_width_frac : integer := 20;
|
||||
out_width : integer := 32;
|
||||
out_width_frac : integer := 20
|
||||
);
|
||||
END tb_cic_i_pipe;
|
||||
|
||||
ARCHITECTURE behavior OF tb_cic_i_pipe IS
|
||||
|
||||
-- Component Declaration for the Unit Under Test (UUT)
|
||||
COMPONENT cic_i_pipe
|
||||
GENERIC
|
||||
(
|
||||
max_width : integer;
|
||||
max_width_frac : integer;
|
||||
in_width : integer;
|
||||
in_width_frac : integer;
|
||||
out_width : integer;
|
||||
out_width_frac : integer
|
||||
);
|
||||
PORT
|
||||
(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
din : in sfixed;
|
||||
dout : out sfixed;
|
||||
vld_out : out std_logic
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
--Constants
|
||||
constant PERIOD : time := 10 ns;
|
||||
|
||||
|
||||
--Inputs
|
||||
SIGNAL clk : std_logic := '0';
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL vld_in : std_logic := '0';
|
||||
SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
|
||||
|
||||
--Outputs
|
||||
SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
|
||||
SIGNAL vld_out : std_logic;
|
||||
|
||||
SIGNAL fileout_enable : std_logic := '0';
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Instantiate the Unit Under Test (UUT)
|
||||
uut: cic_i_pipe
|
||||
GENERIC MAP
|
||||
(
|
||||
max_width => max_width,
|
||||
max_width_frac => max_width_frac,
|
||||
in_width => in_width,
|
||||
in_width_frac => in_width_frac,
|
||||
out_width => out_width,
|
||||
out_width_frac => out_width_frac
|
||||
)
|
||||
PORT MAP
|
||||
(
|
||||
clk => clk,
|
||||
rst => srst,
|
||||
vld_in => vld_in,
|
||||
din => din,
|
||||
dout => dout,
|
||||
vld_out => vld_out
|
||||
);
|
||||
|
||||
|
||||
tb_clk : PROCESS
|
||||
BEGIN
|
||||
clk <= not clk;
|
||||
wait for PERIOD/2;
|
||||
END PROCESS;
|
||||
|
||||
tb : PROCESS
|
||||
|
||||
BEGIN
|
||||
|
||||
-- Wait 100 ns for global reset to finish
|
||||
wait for 4*PERIOD;
|
||||
srst <= '0';
|
||||
------------------------------------------
|
||||
wait for 2*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
din <= to_sfixed(0.0, din, false, true);
|
||||
vld_in <= '1';
|
||||
|
||||
wait for 9*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
|
||||
din <= to_sfixed(0.5, din, false, true);
|
||||
|
||||
wait for 9*PERIOD;
|
||||
wait until rising_edge(clk);
|
||||
vld_in <= '0';
|
||||
|
||||
wait for 20*PERIOD;
|
||||
|
||||
assert false report "Test finished" severity error;
|
||||
wait;
|
||||
END PROCESS;
|
||||
|
||||
END;
|
||||
Reference in New Issue
Block a user