jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- SDRAM can now operate at different speed than BUS clock

Browse Source 
- separated bus-clock (sys_clk) and SDRAM-clocks
  - added async. FIFOs for clock domain separation
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@578 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-03 20:42:27 +00:00
parent 88d3bd6607
commit d908ae0e9e
5 changed files with 121 additions and 105 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd
+13 -9
View File
@@ -40,8 +40,9 @@ entity sdram_ctrl_frontend64_wb is
(
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
CLK270_I : in STD_LOGIC;
CLK270VAR_I : in STD_LOGIC;
SDRAM_CLK0_I : in STD_LOGIC;
SDRAM_CLK270_I : in STD_LOGIC;
SDRAM_CLK270VAR_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
@@ -155,7 +156,7 @@ begin
);
-- Instantiate synchronous FIFO
inst_write_fifo: entity work.fifo_sync
inst_write_fifo: entity work.fifo_async
GENERIC MAP
(
addr_width => fifo_depth,
@@ -164,7 +165,8 @@ begin
PORT MAP
(
rst => RST_I,
clk => CLK_I,
clk_w => CLK_I,
clk_r => SDRAM_CLK0_I,
we => write_fifo_we,
re => write_fifo_re,
fifo_full => write_fifo_full,
@@ -176,7 +178,7 @@ begin
);
-- Instantiate synchronous FIFO
inst_read_fifo: entity work.fifo_sync
inst_read_fifo: entity work.fifo_async
GENERIC MAP
(
addr_width => fifo_depth,
@@ -185,7 +187,8 @@ begin
PORT MAP
(
rst => RST_I,
clk => CLK_I,
clk_w => SDRAM_CLK0_I,
clk_r => CLK_I,
we => read_fifo_we,
re => read_fifo_re,
fifo_full => read_fifo_full,
@@ -207,10 +210,11 @@ begin
(
sys_rst_in => RST_I,
sys_clk0_in => CLK_I,
sys_clk_in => CLK_I,
sys_clk270_in => CLK270_I,
capture_clk270_in => CLK270VAR_I,
sdram_clk0_in => SDRAM_CLK0_I,
sdram_clk270_in => SDRAM_CLK270_I,
sdram_clk270_rd_in => SDRAM_CLK270VAR_I,
-- User interface
u_data_vld => u_data_vld,
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd
+13 -9
View File
@@ -40,8 +40,9 @@ entity sdram_ctrl_frontend_wb is
(
RST_I : in STD_LOGIC;
CLK_I : in STD_LOGIC;
CLK270_I : in STD_LOGIC;
CLK270VAR_I : in STD_LOGIC;
SDRAM_CLK0_I : in STD_LOGIC;
SDRAM_CLK270_I : in STD_LOGIC;
SDRAM_CLK270VAR_I : in STD_LOGIC;
CYC_I : in STD_LOGIC;
STB_I : in STD_LOGIC;
@@ -155,7 +156,7 @@ begin
);
-- Instantiate synchronous FIFO
inst_write_fifo: entity work.fifo_sync
inst_write_fifo: entity work.fifo_async
GENERIC MAP
(
addr_width => fifo_depth,
@@ -164,7 +165,8 @@ begin
PORT MAP
(
rst => RST_I,
clk => CLK_I,
clk_w => CLK_I,
clk_r => SDRAM_CLK0_I,
we => write_fifo_we,
re => write_fifo_re,
fifo_full => write_fifo_full,
@@ -176,7 +178,7 @@ begin
);
-- Instantiate synchronous FIFO
inst_read_fifo: entity work.fifo_sync
inst_read_fifo: entity work.fifo_async
GENERIC MAP
(
addr_width => fifo_depth,
@@ -185,7 +187,8 @@ begin
PORT MAP
(
rst => RST_I,
clk => CLK_I,
clk_w => SDRAM_CLK0_I,
clk_r => CLK_I,
we => read_fifo_we,
re => read_fifo_re,
fifo_full => read_fifo_full,
@@ -207,10 +210,11 @@ begin
(
sys_rst_in => RST_I,
sys_clk0_in => CLK_I,
sys_clk_in => CLK_I,
sys_clk270_in => CLK270_I,
capture_clk270_in => CLK270VAR_I,
sdram_clk0_in => SDRAM_CLK0_I,
sdram_clk270_in => SDRAM_CLK270_I,
sdram_clk270_rd_in => SDRAM_CLK270VAR_I,
-- User interface
u_data_vld => u_data_vld,
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+23 -20
View File
@@ -37,9 +37,11 @@ entity sdram_ctrl_top is
Port
(
sys_rst_in : in STD_LOGIC;
sys_clk0_in : in STD_LOGIC;
sys_clk270_in : in STD_LOGIC;
capture_clk270_in : in STD_LOGIC;
sys_clk_in : in STD_LOGIC;
sdram_clk0_in : in STD_LOGIC;
sdram_clk270_in : in STD_LOGIC;
sdram_clk270_rd_in : in STD_LOGIC;
-- User interface
u_data_vld : out STD_LOGIC;
@@ -94,7 +96,7 @@ architecture rtl of sdram_ctrl_top is
-- SD command FIFO
constant CMD_FIFO_ADDR_WIDTH : positive := 2;
constant CMD_FIFO_ADDR_WIDTH : positive := 2; -- lower than 3 won't give sustained throuhput (for sys_clk == sdram_clk)
constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length;
signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
@@ -108,10 +110,10 @@ architecture rtl of sdram_ctrl_top is
alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
alias sd_tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length);
alias sd_cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4);
alias sd_mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length);
alias sd_col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0);
begin
@@ -124,13 +126,13 @@ begin
---------------------------------
sd_cmd_we <= not cmd_fifo_empty;
cmd_fifo_in <= to_unsigned(sd_cmd_in, 4);
sd_cmd <= sdr_cmd_t(to_integer(cmd_fifo_out));
sd_cmd <= sdr_cmd_t(to_integer(sd_cmd_fifo_out));
---------------------------------
inst_reset: entity work.reset
port map
(
clk => sys_clk0_in,
clk => sys_clk_in,
rst_in => sys_rst_in,
rst_out => ctrl_rst
);
@@ -145,7 +147,7 @@ begin
Port map
(
rst => ctrl_rst,
clk => sys_clk0_in,
clk => sys_clk_in,
u_busy => u_busy,
u_tag_in => u_tag_in,
u_tag_out => tag_fifo_in,
@@ -161,7 +163,7 @@ begin
);
-- Instantiate synchronous FIFO
inst_sd_cmd_fifo: entity work.fifo_sync
inst_sd_cmd_fifo: entity work.fifo_async
GENERIC MAP
(
addr_width => CMD_FIFO_ADDR_WIDTH,
@@ -172,7 +174,8 @@ begin
PORT MAP
(
rst => ctrl_rst,
clk => sys_clk0_in,
clk_w => sys_clk_in,
clk_r => sdram_clk0_in,
we => cmd_fifo_we,
re => cmd_fifo_re,
fifo_full => cmd_fifo_full,
@@ -192,8 +195,8 @@ begin
Port map
(
rst => ctrl_rst,
clk => sys_clk0_in,
u_tag_in => tag_fifo_out,
clk => sdram_clk0_in,
u_tag_in => sd_tag_fifo_out,
u_tag_out => u_tag,
phy_ctrl => phy_ctrl,
enable => cke,
@@ -201,8 +204,8 @@ begin
cmd_we => sd_cmd_we,
cmd_ack => cmd_fifo_re,
sdr_cmd_ctrl => cmd_ctrl,
col_addr => col_fifo_out,
mode_word => mode_fifo_out,
col_addr => sd_col_fifo_out,
mode_word => sd_mode_fifo_out,
sdr_ba => ba,
sdr_addr => addr
);
@@ -212,12 +215,12 @@ begin
Port map
(
sys_rst => ctrl_rst,
sys_clk0 => sys_clk0_in,
sys_clk270 => sys_clk270_in,
sys_clk0 => sdram_clk0_in,
sys_clk270 => sdram_clk270_in,
u_tag_in => u_tag,
u_tag_rd => u_tag_rd,
u_tag_wr => u_tag_wr,
read_clk => capture_clk270_in,
read_clk => sdram_clk270_rd_in,
phy_ctrl => phy_ctrl,
part_ctrl => part_ctrl,
sdr_data_req_w => u_data_req_w,
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend64_wb.vhd
+36 -34
View File
@@ -58,6 +58,7 @@ architecture struct of tb_sdram_ctrl_frontend64_wb is
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal CLK_O : std_logic;
signal CLK0_O : std_logic;
signal CLK270_O : std_logic;
signal CLK270VAR_O : std_logic;
signal RST_O : std_logic;
@@ -119,8 +120,9 @@ begin
inst_clockgen : entity work.clockgen
GENERIC MAP
(
sys1_phaseshift => 0,
frequency_hz => 100E6
clk_in_freq_hz => 100E6,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
PORT MAP
(
@@ -128,16 +130,16 @@ inst_clockgen : entity work.clockgen
rst => rst, -- external async reset, low active
clk_in => clk, -- system clock (e.g. 100MHz), from board
clk_fb_in => clk_fb, -- feedback clock
sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sys1_clk270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sys0_clk0_out => CLK_O, -- System clock #0, dcm#0 output 0°
sys0_clk270_out => CLK270_O, -- System clock #0, dcm#0 output 270°
clk0_0_out => CLK0_O, -- System clock #0, dcm#0 output 0°
clk0_270_out => CLK270_O, -- System clock #0, dcm#0 output 270°
clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
clk1_270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => locked, -- DCM locked status
error_out => error
);
clk_fb <= part_clk_p after 1 ns;
CLK_O <= clk;
RST_O <= not locked;
DAT_O <= X"DEADBEEF" & sddat;
SEL_O <= "0000" & sdsel;
@@ -152,35 +154,35 @@ inst_clockgen : entity work.clockgen
)
PORT MAP
(
RST_I => RST_O,
CLK_I => CLK_O,
CLK270_I => CLK270_O,
CLK270VAR_I => CLK270VAR_O,
CYC_I => CYC_O,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_I,
RST_I => RST_O,
CLK_I => CLK_O,
SDRAM_CLK0_I => CLK0_O,
SDRAM_CLK270_I => CLK270_O,
SDRAM_CLK270VAR_I => CLK270VAR_O,
CYC_I => CYC_O,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_I,
-- SDRAM signals
sd_clk_p => part_clk_p,
sd_clk_n => part_clk_n,
sd_cke => part_cke,
sd_cs_n => part_cs_n,
sd_cas_n => part_cas_n,
sd_ras_n => part_ras_n,
sd_we_n => part_we_n,
sd_addr => part_addr,
sd_ba => part_ba,
sd_dm => part_dm,
sd_dqs => part_dqs,
sd_data => part_data
sd_clk_p => part_clk_p,
sd_clk_n => part_clk_n,
sd_cke => part_cke,
sd_cs_n => part_cs_n,
sd_cas_n => part_cas_n,
sd_ras_n => part_ras_n,
sd_we_n => part_we_n,
sd_addr => part_addr,
sd_ba => part_ba,
sd_dm => part_dm,
sd_dqs => part_dqs,
sd_data => part_data
);
lib/SDRAM/ddr_sdr_v1_5/src/tb_sdram_ctrl_frontend_wb.vhd
+36 -33
View File
@@ -58,6 +58,7 @@ architecture struct of tb_sdram_ctrl_frontend_wb is
signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0');
signal CLK_O : std_logic;
signal CLK0_O : std_logic;
signal CLK270_O : std_logic;
signal CLK270VAR_O : std_logic;
signal RST_O : std_logic;
@@ -116,8 +117,9 @@ begin
inst_clockgen : entity work.clockgen
GENERIC MAP
(
sys1_phaseshift => 0,
frequency_hz => 100E6
clk_in_freq_hz => 100E6,
clk0_out_phaseshift => 0,
clk1_out_phaseshift => 0
)
PORT MAP
(
@@ -125,17 +127,17 @@ inst_clockgen : entity work.clockgen
rst => rst, -- external async reset, low active
clk_in => clk, -- system clock (e.g. 100MHz), from board
clk_fb_in => clk_fb, -- feedback clock
sys1_clk0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
sys1_clk270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
sys0_clk0_out => CLK_O, -- System clock #0, dcm#0 output 0°
sys0_clk270_out => CLK270_O, -- System clock #0, dcm#0 output 270°
clk0_0_out => CLK0_O, -- System clock #0, dcm#0 output 0°
clk0_270_out => CLK270_O, -- System clock #0, dcm#0 output 270°
clk1_0_out => open, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 0°
clk1_270_out => CLK270VAR_O, -- System clock #1 (e.g. clock for DDR-SDRAM data capture), dcm#1 output 270°
locked_out => locked, -- DCM locked status
error_out => error
);
clk_fb <= part_clk_p after 1 ns;
RST_O <= not locked;
CLK_O <= clk;
-- DDR SDRAM Controller Core
sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb
@@ -147,35 +149,36 @@ inst_clockgen : entity work.clockgen
)
PORT MAP
(
RST_I => RST_O,
CLK_I => CLK_O,
CLK270_I => CLK270_O,
CLK270VAR_I => CLK270VAR_O,
RST_I => RST_O,
CLK_I => CLK_O,
SDRAM_CLK0_I => CLK0_O,
SDRAM_CLK270_I => CLK270_O,
SDRAM_CLK270VAR_I => CLK270VAR_O,
CYC_I => CYC_O,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_I,
CYC_I => CYC_O,
STB_I => STB_O,
SEL_I => SEL_O,
WE_I => WE_O,
ACK_O => ACK_I,
SRDY_O => SRDY_I,
MRDY_I => MRDY_O,
ADDR_I => ADDR_O,
DAT_I => DAT_O,
DAT_O => DAT_I,
-- SDRAM signals
sd_clk_p => part_clk_p,
sd_clk_n => part_clk_n,
sd_cke => part_cke,
sd_cs_n => part_cs_n,
sd_cas_n => part_cas_n,
sd_ras_n => part_ras_n,
sd_we_n => part_we_n,
sd_addr => part_addr,
sd_ba => part_ba,
sd_dm => part_dm,
sd_dqs => part_dqs,
sd_data => part_data
sd_clk_p => part_clk_p,
sd_clk_n => part_clk_n,
sd_cke => part_cke,
sd_cs_n => part_cs_n,
sd_cas_n => part_cas_n,
sd_ras_n => part_ras_n,
sd_we_n => part_we_n,
sd_addr => part_addr,
sd_ba => part_ba,
sd_dm => part_dm,
sd_dqs => part_dqs,
sd_data => part_data
);